CN103928527B - 一种横向高压功率半导体器件的结终端结构 - Google Patents

一种横向高压功率半导体器件的结终端结构 Download PDF

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CN103928527B
CN103928527B CN201410174942.1A CN201410174942A CN103928527B CN 103928527 B CN103928527 B CN 103928527B CN 201410174942 A CN201410174942 A CN 201410174942A CN 103928527 B CN103928527 B CN 103928527B
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junction termination
termination structures
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drift region
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乔明
文帅
张昕
薛腾飞
齐钊
吴文杰
张波
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University of Electronic Science and Technology of China
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Abstract

本发明涉及半导体功率器件技术领域，具体的说是涉及一种横向高压功率半导体器件的结终端结构。本发明通过增加器件在曲率结终端处P型衬底和N型漂移区的总面积，从而防止器件在P型衬底区发生提前耗尽，保证器件在曲率结终端处的耐压。本发明的有益效果为，能够明显的降低曲率结终端对整个器件耐压的影响，使器件在过渡区的电场不会过大，并且通过改变漂移区或者P型衬底的面积使得器件的耐压达到最优化，保证器件的耐压。本发明尤其适用于横向高压功率半导体器件的结终端结构。

Description

一种横向高压功率半导体器件的结终端结构
技术领域
本发明涉及半导体功率器件技术领域，具体的说是涉及一种横向高压功率半导体器件的结终端结构。
背景技术
随着工业的电动化程度日益提高，对高电压大电流器件的要求越来越高。为了提高器件的耐压，出现了各种结终端结构以满足器件的耐压要求。
高压功率集成电路的发展离不开可集成的横向高压功率半导体器件。横向高压功率半导体器件通常为闭合结构，包括圆形、跑道型和叉指状等结构。对于闭合的跑道型结构和叉指状结构，在弯道部分和指尖部分会出现小曲率终端，电场线容易在小曲率半径处发生集中，从而导致器件在小曲率半径处电场较高，提前发生雪崩击穿。而采用直线结终端结构和曲率结终端结构所结合的跑道型终端结构以及包含有弯道结构的终端结构的设计，可避免器件在曲率结终端处提前击穿，提高器件的耐压，但是由于在曲率终端结构处，器件的等势线相对于直线终端结构会比较容易集中，因此导致电场较高于其它地方，发生提前击穿，降低器件的耐压；并且高压功率器件在曲率结终端结构处，主要用来承受耐压的漂移区会相对于直线终端处的漂移区较少，这会导致在在曲率终端处的漂移区提前耗尽，影响器件的耐压。
发明内容
本发明所要解决的，就是针对上述传统横向高压功率半导体器件在曲率结终端处提前击穿的问题，提出一种横向高压功率半导体器件的结终端结构。
本发明解决上述技术问题所采用的技术方案是：一种横向高压功率半导体器件的结终端结构，如图5所示，包括直线结终端结构和曲率结终端结构；所述直线结终端结构与横向高压功率半导体器件有源区结构相同，包括漏极N+接触区1、N型漂移区2、P型衬底3、栅极多晶硅4、栅氧化层5、P-well区6、源极N+接触区7、源极P+接触区8；P-well区6与N型漂移区2位于P型衬底3的上层，其中P-well区6位于中间，两边是N型漂移区2，且P-well区6与N型漂移区2相连；N型漂移区2中远离P-well区6的两侧是漏极N+接触区1，P-well区6的上层具有与金属化源极相连的源极N+接触区7和源极P+接触区8，其中源极P+接触区8位于中间，源极N+接触区7位于源极P+接触区8两侧；源极N+接触区7和源极P+接触区8与N型漂移区2之间的P-well区6表面是栅氧化层5，栅氧化层5的表面是栅极多晶硅4；
所述曲率结终端结构包括漏极N+接触区1、N型漂移区2、P型衬底3、栅极多晶硅4、栅氧化层5、P-well区6、源极P+接触区8；P-well区6表面是栅氧化层5，栅氧化层5的表面是栅极多晶硅4；曲率结终端结构中的N+接触区1和N型漂移区2分别与直线结终端结构中的N+接触区1和N型漂移区2相连并形成环形结构；曲率结终端结构中的栅氧化层5和栅极多晶硅4分别与直线结终端结构中的栅氧化层5和栅极多晶硅4相连并形成弧形或三角形；其中，曲率结终端结构中的环形N+接触区1包围环形N型漂移区2，曲率结终端结构中的环形N型漂移区2包围栅极多晶硅4和栅氧化层5；与“直线结终端结构中的P-well区6与N型漂移区2相连”不同的是，曲率结终端结构中的P-well区6与N型漂移区2不相连；
其特征在于，源极N+接触区7与曲率结终端结构之间的P-well区6的横向尺寸从远离曲率结终端结构的一端到靠近曲率结终端结构的一端逐渐减小，源极N+接触区7与曲率结终端结构之间的P-well区6表面的栅氧化层5和栅极多晶硅4之间的间距从远离曲率结终端结构的一端到靠近曲率结终端结构的一端逐渐减小，曲率结终端结构中的栅氧化层5和栅极多晶硅4分别与直线结终端结构中的栅氧化层5和栅极多晶硅4相连并形成弧形或三角形。
本发明的有益效果为，能够明显的降低曲率结终端对整个器件耐压的影响，使器件在过渡区的电场不会过大，并且通过改变漂移区或者P型衬底的面积使得器件的耐压达到最优化，保证器件的耐压，同时与现有的各种结终端技术相比，本发明没有额外引入一些新的终端结构，因此能够在不增加工艺步骤和成本的情况下，改善器件在曲率结终端处的耐压问题。
附图说明
图1为传统横向高压功率半导体器件的结终端结构示意图；
图2为传统横向高压功率半导体器件的结终端结构俯视图；
图3为图2中沿AA`线的器件截面示意图；
图4为图2中沿BB`线的器件截面示意图；
图5为本发明的横向高压功率半导体器件的结终端结构示意图；
图6为本发明的横向高压功率半导体器件的结终端结构俯视图；
图7为图6中沿AA`线的器件截面示意图；
图8为图6中沿BB`线的器件截面示意图；
图9为图6中沿CC`线的器件截面示意图；
图10为实施例1的器件结构示意图；
图11为实施例2的器件结构示意图；
图12为实施例3的器件结构示意图；
图13为实施例4的器件结构示意图；
图14为实施例5的器件结构示意图；
图15为实施例6的器件结构示意图。
具体实施方式
下面结合附图和实施例，详细描述本发明的技术方案：
本发明针对传统直线结终端结构和曲率结终端结构所构成的一种横向高压功率半导体器件，提出新的曲率终端结构，进一步改善器件在曲率结终端处的耐压问题；且工艺简单，易于实现。本发明解决问题采用的主要技术方案是增加器件在曲率结终端处P型衬底和N型漂移区的总面积，对应不同的器件以及掺杂浓度可以通过改变P型衬底和N型漂移区的面积来防止器件在P型衬底区或者N型漂移区发生提前耗尽，使器件在曲率结终端处的耐压达到最优，保证器件在曲率结终端处的耐压。
如图1和图2所示，为传统的横向高压功率半导体器件的结终端结构，包括直线结终端结构和曲率结终端结构；如图3所示，直线结终端结构与横向高压功率半导体器件有源区结构相同，包括漏极N+接触区1、N型漂移区2、P型衬底3、栅极多晶硅4、栅氧化层5、P-well区6、源极N+接触区7、源极P+接触区8；P-well区6与N型漂移区2位于P型衬底3的上层，其中P-well区6位于中间，两边是N型漂移区2，且P-well区6与N型漂移区2相连；N型漂移区2中远离P-well区6的两侧是漏极N+接触区1，P-well区6的上层具有与金属化源极相连的源极N+接触区7和源极P+接触区8，其中源极P+接触区8位于中间，源极N+接触区7位于源极P+接触区8两侧；源极N+接触区7与N型漂移区2之间的P-well区6表面是栅氧化层5，栅氧化层5的表面是栅极多晶硅4；
如图4所示，曲率结终端结构包括漏极N+接触区1、N型漂移区2、P型衬底3、栅极多晶硅4、栅氧化层5、P-well区6、源极P+接触区8；P-well区6表面是栅氧化层5，栅氧化层5的表面是栅极多晶硅4；曲率结终端结构中的N+接触区1、N型漂移区2、栅氧化层5和栅极多晶硅4分别与直线结终端结构中的N+接触区1、N型漂移区2、栅氧化层5和栅极多晶硅4相连并形成环形结构；其中，曲率结终端结构中的环形N+接触区1包围环形N型漂移区2，曲率结终端结构中的环形N型漂移区2包围栅极多晶硅4和栅氧化层5；与“直线结终端结构中的P-well区6与N型漂移区2相连”不同的是，曲率结终端结构中的P-well区6与N型漂移区2不相连且相互间距为LPsub；N型漂移区2的长度为LNdrift。
如图5和图6所示，为本发明的横向高压功率半导体器件的结终端结构，如图7-9所示，本发明的结构与传统结构不同的地方在于，本发明通过一个过渡区连接直线结终端结构和曲率结终端结构，由于过渡区不含有源极N+接触区7，因此在过渡区缩小了P-well区6的面积，实现了曲率结终端结构处P-well区6面积的减小(即实现了曲率结终端结构处P型衬底和N型漂移区总面积的增加)。由于曲率结终端结构与横向高压功率半导体器件有源区结构有所不同，在曲率结终端结构处，器件的耐压主要由低掺杂漂移区和衬底共同决定，等势线在曲率结上的分布对器件在曲率结终端处的耐压影响较大；此外，由于衬底的掺杂很低，漂移区和衬底形成的冶金结处，耗尽区主要向衬底方向扩展，因此，漂移区和衬底的面积对曲率结终端结构处的耐压影响很大，在本发明中，由于在曲率结终端结构处，并没有做器件的源极N+接触区7，使源极P+接触区8两边的栅氧化层5和栅极多晶硅4的间距从源极N+接触区7末端到曲率结终端结构逐渐减小，从而可以减少P-well区6的面积，增加了曲率结终端结构处的漂移区和衬底的总面积。通过增加漂移区或者衬底区的长度，可以使器件承受更高的耐压。
实施例1：
如图10所示，本例包括直线结终端结构和曲率结终端结构；所述直线结终端结构与横向高压功率半导体器件有源区结构相同，包括漏极N+接触区1、N型漂移区2、P型衬底3、栅极多晶硅4、栅氧化层5、P-well区6、源极N+接触区7、源极P+接触区8；P-well区6与N型漂移区2位于P型衬底3的上层，其中P-well区6位于中间，两边是N型漂移区2，且P-well区6与N型漂移区2相连；N型漂移区2中远离P-well区6的两侧是漏极N+接触区1，P-well区6的上层具有与金属化源极相连的源极N+接触区7和源极P+接触区8，其中源极P+接触区8位于中间，源极N+接触区7位于源极P+接触区8两侧；源极N+接触区7和源极P+接触区8与N型漂移区2之间的P-well区6表面是栅氧化层5，栅氧化层5的表面是栅极多晶硅4；源极N+接触区7与曲率结终端结构之间的源极P+接触区8两边的栅氧化层5和栅极多晶硅4的间距小于源极N+接触区7之间的间距；源极N+接触区7与曲率结终端结构不连接，源极N+接触区7与曲率结终端结构之间的源极P+接触区8两边的栅氧化层5和栅极多晶硅4的间距从源极N+接触区7末端到曲率结终端结构逐渐减小；
所述曲率结终端结构包括漏极N+接触区1、N型漂移区2、P型衬底3、栅极多晶硅4、栅氧化层5、P-well区6、源极P+接触区8；P-well区6表面是栅氧化层5，栅氧化层5的表面是栅极多晶硅4；曲率结终端结构中的N+接触区1和N型漂移区2分别与直线结终端结构中的N+接触区1和N型漂移区2相连并形成环形结构；曲率结终端结构中的栅氧化层5和栅极多晶硅4分别与直线结终端结构中的栅氧化层5和栅极多晶硅4相连并形成弧形或三角形；其中，曲率结终端结构中的环形N+接触区1包围环形N型漂移区2，曲率结终端结构中的环形N型漂移区2包围栅极多晶硅4和栅氧化层5；与“直线结终端结构中的P-well区6与N型漂移区2相连”不同的是，曲率结终端结构中的P-well区6与N型漂移区2不相连且相互间距为LPsub+ΔL；N型漂移区2的长度为LNdrift。其中曲率结终端结构中的P-well区6与N型漂移区2的间距LPsub和N型漂移区2的长度LNdrift的总长度在数微米至数十微米之间。
本例中，源极N+接触区7与曲率结终端结构之间的P-well区6的横向尺寸从远离曲率结终端结构的一端到靠近曲率结终端结构的一端逐渐减小，源极N+接触区7与曲率结终端结构之间的P-well区6表面的栅氧化层5和栅极多晶硅4之间的间距从远离曲率结终端结构的一端到靠近曲率结终端结构的一端逐渐减小，减少P-well区6的面积，增加了曲率结终端结构处的漂移区和衬底的总面积，同时保持器件在曲率结终端处原有LNdrift的长度不变的情况下，增加了LPsub的长度，变为LPsub+ΔL，从而增加P型衬底区的面积，当衬底掺杂浓度较低时，耗尽区将很快向P型衬底区延伸，此时可以通过增加P型衬底区的面积防止P型衬底区提前耗尽，保证器件在曲率结终端处的耐压。
实施例2：
如图11所示，本例与实施例1不同的地方在于，保持器件在曲率结终端处原有LPsub的长度不变的情况下，增加了LNdrift的长度，变为LNdrift+ΔL，从而增加N型漂移区的面积，本例的工作原理为：当衬底掺杂浓度较高时，可以适当的增加N型漂移区的面积，这样可以保证P型衬底和N型漂移区的耐压达到最大。
实施例3：
如图12所示，本例与实施例1不同的地方在于，同时增加LPsub的长度和LNdrift的长度，使其变为LPsub+ΔL1和LNdrift+ΔL2，其中ΔL1与ΔL2之和等于ΔL，从而同时增加P型衬底区和N型漂移区的面积，使器件的耐压能达到最优化。
实施例4：
如图13所示，本例与实施例1不同的地方在于，源极P+接触区8两边的栅氧化层5和栅极多晶硅4的间距从源极N+接触区7末端到曲率结终端结构逐渐减小的渐变度较小，从而增加P-well区的面积。由于在过渡区并没有做源极N+接触区7，使得过渡区源极P+接触区8的面积增加，这样可能会使得在过渡区的N型漂移区2提前耗尽，通过对过渡区渐变度的改变，可以改变P-well区的面积，有效的防止N型漂移区提前耗尽，保证器件的耐压。
实施例5：
如图14所示，本例与实施例1不同的地方在于，增加了曲率结终端结构中栅氧化层5和栅极多晶硅4形成的圆弧的弧度，相当于增加了曲率结终端结构中源极P+接触区8的面积。在实际应用中，考虑到器件的导通电阻，要求导通电阻越低越好，因此在满足器件要求的情况下N型漂移区的掺杂浓度会适当的增大，N型漂移区浓度的增加会使得P型衬底提前耗尽，降低器件在曲率结终端结构处的耐压，而通过增加曲率结终端结构中源极P+接触区8的面积，即增加了曲率结终端结构处P型掺杂的总掺杂量，可以防止P型衬底提前耗尽，保证耐压达到最大。
实施例6：
如图14所示，本例与实施例1不同的地方在于，曲率结终端结构中栅氧化层5和栅极多晶硅4与直线结终端结构中栅氧化层5和栅极多晶硅4形成三角形，使得曲率结终端结构处源极P+接触区面积减小。在高压功率器件的应用中，由于对器件的耐压要求较高，漂移区的掺杂浓度会比较低，此时如果曲率结终端结构处的掺杂总量较高时，会使得N型漂移区提前耗尽，降低器件的耐压。本实例通过对曲率结终端结构处源极P+接触区面积减小，实现了曲率结终端结构处P型掺杂的总掺杂量的减少，防止N型漂移区提前耗尽，保证器件的耐压。

Claims (1)

1.一种横向高压功率半导体器件的结终端结构，包括直线结终端结构和曲率结终端结构；所述直线结终端结构与横向高压功率半导体器件有源区结构相同，包括漏极N+接触区(1)、N型漂移区(2)、P型衬底(3)、栅极多晶硅(4)、栅氧化层(5)、P-well区(6)、源极N+接触区(7)、源极P+接触区(8)；P-well区(6)与N型漂移区(2)位于P型衬底(3)的上层，其中P-well区(6)位于中间，两边是N型漂移区(2)，且P-well区(6)与N型漂移区(2)相连；N型漂移区(2)中远离P-well区(6)的两侧是漏极N+接触区(1)，P-well区(6)的上层具有与金属化源极相连的源极N+接触区(7)和源极P+接触区(8)，其中源极P+接触区(8)位于中间，源极N+接触区(7)位于源极P+接触区(8)两侧；源极N+接触区(7)与N型漂移区(2)之间的P-well区(6)表面是栅氧化层(5)，栅氧化层(5)的表面是栅极多晶硅(4)；
所述曲率结终端结构包括漏极N+接触区(1)、N型漂移区(2)、P型衬底(3)、栅极多晶硅(4)、栅氧化层(5)、P-well区(6)、源极P+接触区(8)；P-well区(6)表面是栅氧化层(5)，栅氧化层(5)的表面是栅极多晶硅(4)；曲率结终端结构中的N+接触区(1)和N型漂移区(2)分别与直线结终端结构中的N+接触区(1)和N型漂移区(2)相连并形成环形结构；其中，曲率结终端结构中的环形N+接触区(1)包围环形N型漂移区(2)，曲率结终端结构中的环形N型漂移区(2)包围栅极多晶硅(4)和栅氧化层(5)；与“直线结终端结构中的P-well区(6)与N型漂移区(2)相连”不同的是，曲率结终端结构中的P-well区(6)与N型漂移区(2)不相连；
其特征在于，源极N+接触区(7)与曲率结终端结构之间的P-well区(6)的横向尺寸从远离曲率结终端结构的一端到靠近曲率结终端结构的一端逐渐减小，P-well区(6)表面的栅氧化层(5)和栅极多晶硅(4)之间的间距从远离曲率结终端结构的一端到靠近曲率结终端结构的一端逐渐减小，曲率结终端结构中的栅氧化层(5)和栅极多晶硅(4)分别与直线结终端结构中的栅氧化层(5)和栅极多晶硅(4)相连，且曲率结终端结构中的栅氧化层(5)和栅极多晶硅(4)为弧形或三角形。
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