CN103872028B - 半导体组合件、堆叠式半导体装置及制造半导体组合件及堆叠式半导体装置的方法 - Google Patents

半导体组合件、堆叠式半导体装置及制造半导体组合件及堆叠式半导体装置的方法 Download PDF

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CN103872028B
CN103872028B CN201410106536.1A CN201410106536A CN103872028B CN 103872028 B CN103872028 B CN 103872028B CN 201410106536 A CN201410106536 A CN 201410106536A CN 103872028 B CN103872028 B CN 103872028B
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nude film
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bad
chip
stacked
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CN103872028A (zh
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戴维·A·普拉特
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明揭示堆叠式半导体装置、半导体组合件、制造堆叠式半导体装置的方法及制造半导体组合件的方法。半导体组合件的一个实施例包括经薄化的半导体晶片，所述半导体晶片具有以可释放方式附接到临时载体的作用侧、后侧及位于所述作用侧处的多个第一裸片。个别第一裸片具有集成电路、电连接到所述集成电路的第一贯通裸片互连件及暴露在所述晶片的所述后侧处的互连触点。所述组合件进一步包含多个分离的第二裸片，所述第二裸片使其前侧附接到对应的第一裸片的后侧，其中个别第二裸片具有集成电路、电连接到所述集成电路的贯通裸片互连件及后侧处的接触点，且其中所述个别第二裸片具有大约小于100微米的厚度。

Description

半导体组合件、堆叠式半导体装置及制造半导体组合件及堆 叠式半导体装置的方法
本申请是一件分案申请，其母案的申请日为2008年5月30日、进入中国国家阶段的申请号为200880019833.5、发明名称为“半导体组合件、堆叠式半导体装置及制造半导体组合件及堆叠式半导体装置的方法”。
技术领域
本发明涉及堆叠式半导体装置及用于制造堆叠式半导体装置的方法。
背景技术
经封装的半导体装置用于蜂窝式电话、寻呼机、个人数字助理、计算机及许多其它类型的消费者电子产品或工业电子产品中。微电子制造商正在研发具有较小大小的更精密的装置。为符合当前的设计标准，半导体组件在印刷电路板上日益减小的“占用面积”(即，所述装置在印刷电路板上所占的高度及表面积)内具有越来越密集的输入/输出端子阵列。
通常使用同时处理大量裸片(即，芯片)的方法在半导体晶片或其它类型的工件上制作半导体装置。微电子装置通常具有裸片，所述裸片包含具有高密度的极小组件的集成电路。所述裸片通常包含接合垫阵列或其它外部电端子阵列以用于向及从所述集成电路传输电源电压、信号等。所述接合垫通常非常小且组装成在接合垫之间具有精细间距的密集阵列。
一种用于增加给定占用面积内微电子装置的密度的技术是将一个微电子裸片堆叠于另一个微电子裸片顶部上。举例来说，贯通衬底互连件可将下部裸片前侧处的接合垫与所述下部裸片后侧处的触点电连接，使得顶部裸片的接合垫可电耦合到所述下部裸片的所述后侧触点。用于堆叠此类裸片的现有工艺包含通过从晶片的后侧移除材料来薄化第一晶片及第二晶片以(1)暴露所述裸片的后侧上的互连接触点且(2)减少所述裸片的厚度。通常将所述第二晶片薄化到不小于300微米。在薄化之后，将所述第二晶片单个化(即，切割)且将来自所述第二晶片的分离的裸片堆叠到所述第一晶片上的裸片上。随后在单个的第二裸片之间安置囊封剂，且切割所述第一晶片及囊封剂以分离堆叠式装置。
附图说明
图1是示意性地图解说明根据本发明实施例的堆叠式半导体装置的横截面图。
图2A到2F是示意性地图解说明用于制造半导体组合件的方法的阶段的横截面图。
图3是如图2F中所示的堆叠式装置的一部分的横截面图，其图解说明三个经堆叠的微电子裸片。
图4是图解说明用于制造堆叠式裸片半导体组合件的方法的流程图。
图5是图解说明用于制造堆叠式裸片半导体组合件的另一方法的流程图。
图6是并入有堆叠式半导体装置的***的示意图。
具体实施方式
下文参照半导体组合件、堆叠式半导体装置、制造半导体组合件的方法及形成堆叠式半导体装置的方法描述本揭示内容的数个实施例的具体细节。在半导体晶片上制造所述装置，所述半导体晶片可包含可在其上及/或其中制作微电子装置、微机械装置、数据存储元件、光学器件、读取/写入组件及其它特征的衬底。举例来说，可在半导体晶片上构造SRAM、DRAM(例如，DDR/SDRAM)、快闪存储器(例如，NAND/存储器)、处理器、成像器及其它类型的装置。尽管下文参照半导体晶片描述所述实施例中的许多实施例，但在其它类型的衬底(例如，介电衬底或导电衬底)上制造的其它类型的装置可涵盖于本发明的范围内。此外，相比于本章节中下文所描述的那些实施例，本发明的数个其它实施例可具有不同配置、组件或程序。因此，所属领域的技术人员将相应地理解本发明的其它实施例可具有额外元件，或又一些实施例可不具有下文参照图1到6显示并描述的特征及元件中的数者。
图1是示意性地图解说明半导体组合件100的横截面图。在此实施例中，半导体组合件100包含半导体晶片110，所述半导体晶片具有多个第一微电子裸片120(通过参考编号120a及120b单个地识别)、以可释放方式附接到晶片110的作用侧112的临时载体130及多个经单个化的第二微电子裸片140(通过参考编号140a及140b单个地识别)。单个的第二裸片140a及140b以分别对应于第一裸片120a及120b的布置的裸片图案附接到晶片110的后侧114。经堆叠的第一/第二裸片120a/140a及120b/140b分别形成堆叠式微电子装置150a及150b。晶片110可使用粘合剂层132(例如，粘合剂膜、环氧树脂、胶带、软膏或在处理期间将晶片110紧固在适当位置的其它适合材料)以可释放方式附接到临时载体130(例如，载体衬底)。粘合剂132应具有适合的释放特性以用于从晶片110及/或单个化之后的堆叠式微电子装置150移除载体130。
在所图解说明的组合件100的实施例中，第一裸片120位于晶片110的作用侧112处。单个的第一裸片120可包含第一集成电路122(示意性地显示)及电耦合到第一集成电路122且暴露于晶片110的作用侧112处的多个第一端子124(例如，接合垫)。在所显示的具体实施例中，第一端子124与粘合剂层132接触；然而，在其它布置中，单个的第一裸片120可包含介于第一端子124与粘合剂层132中间的再分布结构。单个的第一裸片120进一步包含第一贯通裸片互连件125，所述第一贯通裸片互连件将第一端子124电耦合到对应的第一后侧触点126。举例来说，多个第一裸片120可具有第一导通孔127，所述第一导通孔可与第一端子124的至少一部分对准地延伸穿过晶片衬底110的最终厚度T1。接着，可用导电材料(例如，铜)至少部分地填充第一导通孔127以形成第一贯通裸片互连件125。从而，第一互连件125可在第一端子124与第一触点126之间携载电信号及电力。在一些实施例中，可在将临时载体130附接到晶片110的作用侧112之前单个的地测试第一裸片120。根据所述测试，可确定并标记多个已知良好第一裸片120a及多个已知不良第一裸片120b以供参考。
在图1中所示的实施例中，可通过适合的处理步骤(例如，背向研磨、化学机械平面化、抛光等)将晶片110薄化到最终厚度T1。从晶片110的后侧114移除材料可暴露第一后侧触点126，且蚀刻或其它进一步处理可从晶片110的后侧114移除额外材料以使得经暴露的触点126越过晶片110的后侧114凸出。在一些实施例中，薄化晶片110可形成大约小于100微米的最终晶片厚度T1。在其它实施例中，晶片厚度T1可大约小于50微米，且在进一步的实施例中，晶片110可具有大约为20微米到150微米的厚度T1。
在图1中所示的具体实施例中，第二裸片140可与第一裸片120相同，或第二裸片140可与第一裸片120不同。单个的的第二裸片140可包含第二作用侧142、第二后侧144、第二集成电路145及电耦合到第二集成电路145的位于第二作用侧142处的第二端子146。分离的第二裸片140可进一步包含多个第二贯通裸片互连件147，所述第二贯通裸片互连件延伸穿过从位于第二作用侧142处的第二端子146到位于第二后侧144处的第二后侧触点148的第二导通孔149。
多个第二裸片140具有最终裸片厚度T2。如所图解说明，单个的第二裸片140的最终裸片厚度T2是均匀的。此外，第二贯通裸片互连件147的导电材料延伸越过厚度T2以在第二裸片140的第二后侧144处提供螺柱形第二触点148。第二裸片厚度T2可以是大约小于100微米。然而，在其它实施例中，最终第二裸片厚度T2可以是大约小于50微米，且在进一步的实施例中，多个第二裸片140可具有大约为20微米到150微米的最终厚度T2。
第二裸片140附接到对应的第一裸片120以使得第二端子146电耦合到位于晶片110的后侧114处的第一触点126。在安装第二裸片140之前，可通过凸块底部冶金(UBM)处理镀敷软性可锻造金属(例如，镍与铝)以在第二裸片140的第二作用侧142处形成经电镀垫152。UBM铝经电镀垫152可与用于形成第一及第二贯通裸片互连件125、147的铜及其它导电材料形成适合的电连接。UBM经电镀垫152结合螺柱形第一触点126将第二裸片140与晶片110的后侧114间隔开基准距高度。可在晶片110的后侧114与多个经堆叠的第二裸片140之间安置底填充材料154以填充所述基准距间隔且为经堆叠的第二裸片140提供支撑。
在将第二裸片140堆叠到第一裸片120上之前，还可单个的地测试第二裸片140以确定已知良好第二裸片140a及已知不良第二裸片140b。如图1中所示，将已知良好第二裸片140a安装到对应的已知良好第一裸片120a以形成多个已知良好堆叠式装置150a。同样地，将已知不良第二裸片140b安装到对应的已知不良第一裸片120b以形成已知不良堆叠式装置150b。
将经单个化的第二裸片140彼此间隔开，从而形成多个间隙156。在所图解说明的实施例中，在第二裸片140之间的间隙156中安置囊封剂材料158(例如，环氧树脂)。可通过沿线A-A切穿中间间隙156中的囊封剂材料158且切穿晶片110来将单个的堆叠式微电子装置150彼此分离开。在单个化之后，可丢弃已知不良堆叠式装置150b。
图1中所图解说明的堆叠式装置150的实施例具有通过单个的经堆叠的裸片120及140两者的薄的最终厚度T1及T2实现的超薄轮廓。如先前所描述，半导体制造商中存在减少半导体组件的“占用面积”及高度的持续动力。在常规装置中，使用临时载体以在背向研磨及其它薄化技术期间供应结构支撑来将第一及第二裸片两者完全薄化到其在晶片级下的最终厚度。在常规装置中，将完全经薄化的第二裸片相应地单个化且以其最终厚度堆叠在对应的第一裸片上。本发明者认识到处置薄化及单个化之后的第二裸片富有挑战性，因为经薄化的单个的第二裸片是脆弱的且易遭受碎裂。因此，不将常规第二裸片或顶部裸片薄化到小于300微米的最终厚度。随着发现本问题及常规技术的限制，本发明者研发了用于形成具有大致小于300微米厚的顶部裸片的堆叠式裸片组合件100的新工艺。
图2A到2F图解说明用于制造半导体组合件100的方法的具体实施例的阶段。图2A图解说明所述方法的其中通过粘合剂层132将晶片110的前侧112以可释放方式附接到临时载体130的阶段。在此时，晶片110在前侧112与后侧114之间具有初始厚度Ti。晶片110的初始厚度Ti可以是大约500微米到1000微米(例如，在任何薄化之前的全厚度)。在其它实施例中，可在将晶片110附接到载体衬底130之前部分地薄化所述晶片(例如，大约300微米到700微米的Ti)。在此处理阶段，可在中间深度D1处将用于贯通裸片互连件125的导电材料嵌入于晶片110的衬底内。
图2B图解说明已将晶片110从初始厚度Ti薄化到所需厚度T1之后的阶段。举例来说，可使用其中将临时载体130及晶片110安装在研磨机器中的适合的背向研磨工艺从晶片110的后侧114移除材料。在图2B中所示的实施例中，已从晶片110的后侧114移除材料达到至少中间深度D1处以暴露第一贯通裸片互连件125的第一后侧触点126。如上文参照图1所描述，厚度T1可小于大约150微米、100微米甚或小于大约50微米。举例来说，厚度T1可以是约20微米到150微米。进一步的处理(例如蚀刻)可从晶片110的后侧114移除额外材料以使得第一触点126越过所述衬底的表面凸出且具有升高的螺柱形状。在一些实施例中，第一触点126可越过晶片110的后侧114的表面凸出5微米到10微米。
接下来参照图2C，在晶片110的后侧114上堆叠多个经单个化的第二裸片140且彼此间隔开中间间隙156，使得将第二裸片140布置成第一裸片120的所述裸片图案。在此阶段，单个的第二裸片140在第一侧142(例如，图1的第二作用侧142)与和第一侧142相对的第二侧144(例如，图1的第二后侧144)之间具有处置厚度Th。第二裸片140在附接到晶片110时可以是全厚度；然而，在一些布置中，第二裸片140在附接到晶片110时可经部分地薄化。举例来说，处置厚度Th可大约大于300微米。在其它实施例中，处置厚度Th可以是大约500微米到1000微米。第二裸片140的处置厚度Th大体如此，使得第二贯通裸片互连件147的第二触点148位于中间深度D2处，在此深度处所述第二触点在第二裸片140堆叠在第一裸片120上时不暴露在第二侧144上。
可通过使第二端子146与上覆经电镀垫152和对应的第一触点126接触且使用回流工艺或其它加热工艺将第二裸片140以电方式及物理方式耦合到对应的第一裸片120来将第二裸片140附接到对应的第一裸片120。如先前所提及，可单个的地测试第二裸片140以确保将已知良好第二裸片140a附接到已知良好第一裸片120a以形成已知良好堆叠式装置150a，且确保将已知不良第二裸片140b附接到已知不良第一裸片120b以形成已知不良堆叠式装置150b。
图2D图解说明所述方法的其中已在经薄化的晶片110与多个经堆叠的第二裸片140之间分配底填充材料154的后续阶段。接下来参照图2E，在经堆叠的第二裸片140之间的间隙156中沉积囊封剂材料158以至少部分地囊封堆叠式微电子装置150。可使用针状分配器、镂花涂装、模制、水滴型分配工艺或其它适合的技术在间隙156中沉积囊封剂材料158。囊封剂材料158通常是聚合物或保护堆叠式装置150的其它适合材料。囊封剂材料158可将间隙156填充到以下程度：囊封剂材料158与第二裸片140的第二侧144大体共面或低于所述第二裸片140的第二侧144。然而，只要囊封剂材料158不干扰后续背向研磨/薄化工艺，囊封剂材料158的上表面便可凸出而高于第二侧144。
图2F图解说明所述方法的已将第二裸片140从处置厚度Th薄化到所需厚度T2之后的阶段。可将半导体组合件100安装在研磨机器中且可使用背向研磨、化学机械平面化或其它适合工艺将第二裸片140的第二侧144同时薄化到所需厚度T2。因此，在已将第二裸片140安装到第一裸片120之后，薄化第二裸片140。通过背向研磨工艺从第二裸片140的第二侧144移除材料可跨越多个第二裸片140产生均匀厚度T2，且底填充物154及囊封剂材料158可在所述研磨工艺期间支撑经堆叠的第一及第二裸片120、140且保护其免受向下压力影响。
如图所示，将第二裸片140薄化到至少深度D2以暴露第二贯通裸片互连件147的第二触点148。如上文参照图1所描述，厚度T2可小于大约150微米、100微米或在一些实施例中小于大约50微米。举例来说，厚度T2可以是约20微米到150微米。
在形成半导体组合件100之后，可将临时载体130从晶片110的作用侧112移除且可通过沿线A-A切穿囊封剂材料158并切穿晶片110来将堆叠式微电子装置150彼此分离开。或者，也可沿线A-A切割临时载体130且在分离堆叠式装置150之后将所述临时载体从堆叠式装置150移除。此外，可在所述分离工艺之后丢弃已知不良堆叠式装置150b。
第二触点148还可为额外经堆叠的裸片提供电连接以使得可在第二裸片140上安装额外多个裸片(未显示)，随后进行如上文所述的同时薄化工艺。举例来说，图3图解说明具有附接到第二裸片140的第二侧144的第三裸片302的半导体组合件100一的部分(在图2F中以虚线指示)。图3显示第一贯通裸片互连件125的扩大部分，所述第一贯通裸片互连件延伸穿过晶片110到达接合到经电镀垫152的第一触点126。接着，可通过第二端子146及第二贯通裸片互连件147将电力及信号路由到第二触点148。接着，可将第二触点148接合到第二经电镀垫304，所述第二经电镀垫电连接到第三端子306及第三贯通裸片互连件308。
在所图解说明的实施例中，第三贯通裸片互连件308从第三裸片302的前侧310延伸到第三裸片302的后侧312且在第三裸片302的后侧312上的第三触点314中终止。可在第二与第三裸片140、302之间分散额外的底填充材料316。此外，第三裸片302可具有初始厚度(未显示)，所述初始厚度可在已将第三裸片302附接到第二裸片140之后通过背向研磨工艺薄化到所需厚度T3。在一个实施例中，所需厚度T3小于大约150微米、100微米或50微米。厚度T3可相应地为约20微米到150微米。
图4是用于制造堆叠式半导体组合件的方法400的实施例的流程图。方法400可包含将半导体晶片安装到临时载体(框410)。所述晶片可具有在所述晶片上布置成裸片图案的多个第一裸片。方法400可进一步包含薄化所述晶片(框420)。另外，方法400可包含将多个经单个化的第二裸片附接到对应的第一裸片，其中将所述第二裸片布置成所述裸片图案且所述第二裸片彼此间隔开间隙(框430)。在将所述第二裸片附接到所述第一裸片之后，方法400可进一步包含在所述第二裸片之间的所述间隙中安置囊封剂材料(框440)及薄化所述第二裸片(框450)。
图5是用于制造堆叠式半导体组合件的方法500的另一实施例的流程图。方法500可包含测试多个第一裸片以确定已知良好第一裸片及已知不良第一裸片(框510)。方法500还可包含测试多个第二裸片以确定已知良好第二裸片及已知不良第二裸片(框520)。另外，方法500可包含将已知良好第二裸片附接到已知良好第一裸片以形成多个良好堆叠式装置(框530)。此外，方法500可包含将已知不良第二裸片附接到已知不良第一裸片以形成多个不良堆叠式装置(框540)。
可将所图解说明的经堆叠的第一及第二裸片120、140的实施例薄化到比使用常规裸片堆叠技术制造的装置大的程度。举例来说，通过将第二裸片140堆叠到第一裸片120上同时第二裸片140是充分厚以经受处置而不碎裂，且接着，随后薄化第二裸片140，可在最终装置中将第一及第二裸片120、140两者薄化到小于300微米(例如，20微米到150微米)。此外，在一些布置中，可添加处于强健厚度的数个裸片层且接着将其薄化。由于所述经堆叠裸片极薄，因此可堆叠数个裸片层(例如，三个、四个、五个等等)以在低轮廓封装中形成若干多层堆叠式微电子装置。
还可在堆叠所述裸片之前测试单个的第一及第二裸片120、140。可检测有缺陷的裸片(已知不良裸片)且将其堆叠在一起以使得可丢弃整个有缺陷的堆叠式装置150b。此外，通过将经单个化的已知不良第二裸片140b堆叠到已知不良第一裸片120b上，第二已知不良裸片140b可支撑抛光垫或研磨垫以使得能够在将第二裸片140堆叠到第一裸片120上之后实现晶片级薄化。因此，由于单个的已知良好裸片将仅组装其它已知良好裸片，因此良好堆叠式装置150a的生产量可增加。
所图解说明的微电子装置150的实施例还实现制造过程期间可使用的广范的安装参数，包含各种各样的适合的底填充材料154。与由堆叠经预薄化的第二裸片形成的连接相比，第一触点126与经电镀垫152之间的电连接可增强。举例来说，由于处置厚度Th大，因此第二裸片140相当坚固且在将厚的第二裸片140安装到对应的第一裸片120时可承受高下压力。此外，在第二裸片140的所述薄化期间施加的下压力还将第二裸片140按压在第一裸片120上。高下压力产生较好的连接以避免不期望的连接断开。
图6图解说明包含如上文参照图1到5描述的堆叠式半导体装置的***600。更具体来说，如上文参照图1到5描述的堆叠式半导体装置可并入到无数更大及/或更复杂的***中的任一者中，且***600仅是此类***的代表性样本。***600可包含处理器601、存储器602(例如，SRAM、DRAM、快闪或其它存储器装置)、输入/输出装置603及/或子***及其它组件604。所述堆叠式半导体装置可包含于图6中所示的组件中的任一者中。所得的***600可执行各种各样的计算处理、存储、感测、成像及/或其它功能中的任一者。因此，无限制地，***600可以是计算机及/或其它数据处理器，例如，桌上型计算机、膝上型计算机、因特网器具、手持装置、多处理器***、基于处理器的或可编程的消费者电子器件、网络计算机及/或小型计算机。用于所述***的适合的手持装置可包含掌上型计算机、可穿戴计算机、蜂窝式电话或移动电话、个人数字助理等。***600可进一步是相机、光或其它辐射传感器、服务器及相关联的服务器子***及/或任一显示装置。在此类***中，单个的裸片可包含成像器阵列，例如CMOS成像器。***600的组件可容纳在单个单元中或分布在多个互连式单元上方(例如，通过通信网络)。因此，***600的组件可包含本地及/或远程存储器存储装置及各种各样的计算机可读媒体中的任一者。
依据前文所述，将了解，本文中已出于图解说明目的描述了本发明的具体实施例，但可在不背离本发明的精神及范围的前提下做出各种修改。举例来说，前述实施例中的任一者的具体元件可组合或替代其它实施例中的元件。因此，本发明不受除以上权利要求书之外的任何限制。

Claims (13)

1.一种半导体组合件，其包括：
晶片，其包含多个已知良好第一裸片及多个已知不良第一裸片；
多个经分离的已知良好第二裸片，其附接到对应的已知良好第一裸片，及多个经分离的已知不良第二裸片，所述多个经分离的已知不良第二裸片附接到对应的已知不良第一裸片，其中所述第二裸片彼此间隔开间隙；及
位于所述间隙中的囊封剂材料。
2.根据权利要求1所述的组合件，其中所述晶片具有小于100微米的厚度。
3.根据权利要求1所述的组合件，其中所述经分离的第二裸片具有小于100微米的厚度。
4.根据权利要求1所述的组合件，其中所述已知良好第一裸片各自地包括电耦合到第一端子及贯通裸片互连件的第一集成电路，且其中已知良好第二裸片各自地包括电耦合到第二集成电路及对应的贯通裸片互连件的互联接触点的第二端子。
5.根据权利要求1所述的组合件，其中所述已知不良第一裸片和所述已知不良第二裸片是有缺陷的。
6.根据权利要求1所述的组合件，其中所有的所述已知良好第二裸片均安装在所述已知良好第一裸片上。
7.根据权利要求1所述的组合件，其中所述已知不良第一裸片和所述已知不良第二裸片形成有缺陷的堆叠。
8.根据权利要求1所述的组合件，其中：
所述已知良好第一裸片和所述已知良好第二裸片形成已知良好堆叠式装置；且
所述已知不良第一裸片和所述已知不良第二裸片形成已知不良堆叠式装置。
9.根据权利要求1所述的组合件，其中所述第一裸片各自地包括第一集成电路和贯通裸片互连件，所述第一集成电路电耦合到位于所述晶片的作用侧上的第一端子，所述贯通裸片互连件电耦合到所述第一端子，且朝所述第二裸片凸出至越过所述晶片的后侧。
10.一种制造堆叠式半导体组合件的方法，其包括：
晶片，其包含多个已知良好第一裸片及多个已知不良第一裸片；
将多个经分离的已知良好第二裸片附接到对应的已知良好第一裸片，
将多个经分离的已知不良第二裸片附接到对应的已知不良第一裸片，其中所述第二裸片彼此间隔开间隙；及
在所述间隙中设置囊封剂材料。
11.根据权利要求10所述的方法，在将所述多个第二裸片附接到对应的第一裸片之前，所述方法进一步包括测试单个的第一裸片及单个的第二裸片以确定已知良好第一裸片及第二裸片以及已知不良第一裸片及第二裸片。
12.根据权利要求10所述的方法，进一步包括在将所述第二裸片附接到所述第一裸片之前，将所述晶片安装到临时载体上。
13.根据权利要求10所述的方法，其中所述已知良好第一裸片和所述已知良好第二裸片形成已知良好堆叠式装置，且其中所述已知不良第一裸片和所述已知不良第二裸片形成已知不良堆叠式装置。
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US20150194415A1 (en) 2015-07-09
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WO2008157001A1 (en) 2008-12-24
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