CN103839825A - 一种低温多晶硅薄膜晶体管、阵列基板及其制作方法 - Google Patents

一种低温多晶硅薄膜晶体管、阵列基板及其制作方法 Download PDF

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CN103839825A
CN103839825A CN201410062345.XA CN201410062345A CN103839825A CN 103839825 A CN103839825 A CN 103839825A CN 201410062345 A CN201410062345 A CN 201410062345A CN 103839825 A CN103839825 A CN 103839825A
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layer
ohmic contact
contact layer
amorphous silicon
silicon layer
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毛雪
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201410062345.XA priority Critical patent/CN103839825A/zh
Priority to US14/434,856 priority patent/US20160043114A1/en
Priority to EP14859331.2A priority patent/EP3113217B1/en
Priority to PCT/CN2014/073615 priority patent/WO2015123903A1/zh
Publication of CN103839825A publication Critical patent/CN103839825A/zh
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Abstract

本发明公开了一种低温多晶硅薄膜晶体管、阵列基板及其制作方法，用以简化薄膜晶体管的制作工艺流程。所述方法包括：在衬底基板上形成有源层和欧姆接触层的过程；其中，形成所述有源层和欧姆接触层，具体为：在衬底基板上形成非晶硅层；采用离子注入法对所述非晶硅层至少在待形成欧姆接触层的区域进行杂质离子的注入，待形成的欧姆接触层的区域形成初始欧姆接触层；对杂质离子注入工艺后的非晶硅层进行准分子激光退火工艺；准分子激光退火工艺后的非晶硅层晶化为多晶硅层，初始欧姆接触层形成最终的欧姆接触层；对准分子激光退火工艺后的多晶硅层进行构图工艺，形成所述有源层。

Description

一种低温多晶硅薄膜晶体管、阵列基板及其制作方法
技术领域
本发明涉及薄膜晶体管工艺制作领域，尤其涉及一种低温多晶硅薄膜晶体管、阵列基板及其制作方法。
背景技术
在各种显示装置的像素单元中，通过施加驱动电压来驱动显示装置的薄膜晶体管（Thin Film Transistor，TFT）被大量使用。在TFT的有源层一直使用稳定性和加工性较好的非晶硅（a-Si）材料，但是a-Si材料的载流子迁移率较低，不能满足大尺寸、高分辨率显示器件的要求，特别是不能满足下一代有源矩阵式有机发光显示器件（Active Matrix Organic Light Emitting Device，AMOLED）的要求。与非晶硅（a-Si）薄膜晶体管相比，多晶硅尤其是低温多晶硅薄膜晶体管具有更高的电子迁移率、更好的液晶特性以及较少的漏电流，已经逐渐取代非晶硅薄膜晶体管，成为薄膜晶体管的主流。
现有技术，形成有源区的步骤在形成多晶硅的步骤之后，形成有源区的过程经离子注入工艺完成，离子注入后，有源区的掺杂杂质通常位于晶格的间隙，无法起到提供载流子的作用。还需要采用热退火工艺使得注入多晶硅层中的离子激活，同时进行晶格完整性的恢复。由此可见，本发明实施例形成多晶硅、有源区，通过三个步骤形成，形成工艺较复杂。现有技术采用热退火工艺温度较高，不适用于在柔性基板上形成薄膜晶体管。
发明内容
本发明实施例提供一种低温多晶硅薄膜晶体管、阵列基板及其制作方法，用以简化低温多晶硅薄膜晶体管的制作工艺流程。
本发明实施例提供的一种低温多晶硅薄膜晶体管的制作方法包括：
在衬底基板上形成有源层和欧姆接触层的过程；
其中，形成所述有源层和欧姆接触层，具体为：
在衬底基板上形成非晶硅层；
采用离子注入法对所述非晶硅层至少在待形成欧姆接触层的区域进行杂质离子的注入，待形成的欧姆接触层的区域形成初始欧姆接触层；
对杂质离子注入工艺后的非晶硅层进行准分子激光退火工艺；准分子激光退火工艺后的非晶硅层晶化为多晶硅层，初始欧姆接触层形成最终的欧姆接触层；
对准分子激光退火工艺后的多晶硅层进行构图工艺，形成所述有源层。
较佳地，所述准分子激光退火工艺的条件为：激光脉冲频率为100～400Hz，激光重叠率为90%～98%，激光脉冲宽度<100ns，激光能量密度为100～600mJ/cm2。
较佳地，在形成所述非晶硅层之后，杂质离子注入之前，还包括：对所述非晶硅层进行热退火工艺处理。
较佳地，在形成所述非晶硅层之前还包括：在所述衬底基板上形成一层覆盖整个衬底基板的缓冲层。
较佳地，所述采用离子注入法对所述非晶硅层待形成欧姆接触层的区域进行杂质离子的注入，具体为：采用离子注入法对所述非晶硅层待形成欧姆接触层的区域进行硼或磷杂质离子的注入，形成初始欧姆接触层。
本发明实施例提供一种阵列基板的制作方法，包括：
在衬底基板上形成低温多晶硅薄膜晶体管的过程以及形成存储电容的下电极的过程；
所述低温多晶硅薄膜晶体管的形成过程包括如下步骤：
在衬底基板上形成有源层和欧姆接触层的过程；
其中，形成所述有源层和欧姆接触层，具体为：
在衬底基板上形成非晶硅层；
采用离子注入法对所述非晶硅层至少在待形成欧姆接触层的区域进行杂质离子的注入，待形成的欧姆接触层的区域形成初始欧姆接触层；
对杂质离子注入工艺后的非晶硅层进行准分子激光退火工艺；准分子激光退火工艺后的非晶硅层晶化为多晶硅层，初始欧姆接触层形成最终的欧姆接触层；
对准分子激光退火工艺后的多晶硅层进行构图工艺，形成所述有源层。
较佳地，所述采用离子注入法对所述非晶硅层的待形成欧姆接触层的区域进行杂质离子的注入的同时，还包括：在非晶硅层上待形成的存储电容的下电极对应的区域进行杂质离子的注入，待形成的存储电容的下电极对应的区域形成初始存储电容的下电极。
本发明实施例提供一种低温多晶硅薄膜晶体管，采用上述低温多晶硅薄膜晶体管的制作方法制作而成。
本发明实施例提供一种阵列基板，采用上述阵列基板的制作方法制作而成。
本发明实施例提供的低温多晶硅薄膜晶体管的制作方法，在形成多晶硅层之前进行离子注入工艺，在形成多晶硅层的过程中同时形成欧姆接触层，即进行准分子激光退火工艺时形成欧姆接触层，简化了制作工艺，并且形成欧姆接触层的掺杂离子通过准分子激光退火驱入的方式形成，避免了通过离子注入引起薄膜晶体管的相关缺陷和不良现象，提高了薄膜晶体管的性能。
附图说明
图1为本发明实施例提供的阵列基板的制作方法流程示意图；
图2为本发明实施例提供的形成有缓冲层的衬底基板的结构示意图；
图3为本发明实施例提供的形成有非晶硅的衬底基板的结构示意图；
图4为本发明实施例提供的形成有初始欧姆接触层的衬底基板的结构示意图；
图5为本发明实施例提供的形成有有源层的衬底基板的结构示意图；
图6为本发明实施例提供的形成有栅极绝缘层、栅极和存储电容的上电极的衬底基板的结构示意图；
图7为本发明实施例提供的形成有第一绝缘层、欧姆接触层、下电极引线的衬底基板的结构示意图；
图8为本发明实施例提供的形成有第二绝缘层和像素电极的衬底基板的结构示意图。
具体实施方式
本发明实施例提供一种低温多晶硅薄膜晶体管、阵列基板及其制作方法，用以简化低温多晶硅薄膜晶体管的制作工艺流程，同时提高低温多晶硅薄膜晶体管的性能。
本发明实施例提供的低温多晶硅薄膜晶体管的制作方法，在非晶硅层形成多晶硅层之前，对非晶硅进行离子注入形成初始欧姆接触层，在由非晶硅层形成多晶硅层的过程中同时形成离子激活后的欧姆接触层，简化了制作工艺流程。
本发明所述的欧姆接触层也称源漏极掺杂层，欧姆接触层包括两个相互独立的区域，分别用于与后续形成的源极和漏极电性相连。
本发明提供的方法整体包括以下步骤：
在衬底基板上形成有源层、欧姆接触层的过程；
其中，形成所述有源层、欧姆接触层，具体为：
在衬底基板上形成非晶硅层；
采用离子注入法对所述非晶硅层至少在待形成欧姆接触层的区域进行杂质离子的注入，待形成的欧姆接触层的区域形成初始欧姆接触层；
对杂质离子注入工艺后的非晶硅层进行准分子激光退火工艺；准分子激光退火工艺后的非晶硅层晶化为多晶硅层，初始欧姆接触层形成最终的欧姆接触层；
对准分子激光退火工艺后的多晶硅层进行构图工艺，形成所述有源层。
需要说明的是，本领域技术人员能够明白，形成所述薄膜晶体管至少还包括：在衬底基板上形成栅极绝缘层和栅极的过程，这里不再详述。
本发明实施例还提供一种阵列基板的制作方法，包括：
在衬底基板上形成低温多晶硅薄膜晶体管的过程以及形成存储电容的下电极的过程；
所述低温多晶硅薄膜晶体管的形成过程至少包括如下步骤：
在衬底基板上形成有源层和欧姆接触层的过程；
其中，形成所述有源层和欧姆接触层，具体为：
在衬底基板上形成非晶硅层；
采用离子注入法对所述非晶硅层至少在待形成欧姆接触层的区域进行杂质离子的注入，待形成的欧姆接触层的区域形成初始欧姆接触层；
对杂质离子注入工艺后的非晶硅层进行准分子激光退火工艺；准分子激光退火工艺后的非晶硅层晶化为多晶硅层，初始欧姆接触层形成最终的欧姆接触层；
对准分子激光退火工艺后的多晶硅层进行构图工艺，形成所述有源层。
较佳地，所述采用离子注入法对所述非晶硅层的待形成欧姆接触层的区域进行杂质离子的注入的同时，还包括：在非晶硅层上待形成的存储电容的下电极对应的区域进行杂质离子的注入，待形成的存储电容的下电极对应的区域形成初始存储电容的下电极。
由于阵列基板上存储电容的下电极的制作过程与薄膜晶体管制作过程中的部分工艺在同一次制图工艺中形成，以下将具体说明阵列基板上的薄膜晶体管以及存储电容的下电极的制作过程。
参见图1，为阵列基板制作过程的其中一种较佳的实施例。
S11、在衬底基板上形成缓冲层。
当衬底基板的洁净度不满足要求时，首先对衬底基板进行预清洗。通过镀膜工艺在衬底基板上形成一层覆盖整个衬底基板的缓冲层。
具体地，参见图2，在衬底基板1上形成一层缓冲层11。
该步骤S11为可选项，步骤S11形成的缓冲层可以提高待形成的非晶硅与衬底基板之间的附着程度。同时，还可以防止衬底基板中的金属离子扩散至欧姆接触层降低缺陷中心，并且可以减少漏电流的产生。
衬底基板的材质不限，可以为玻璃基板或柔性基板等。
其中一种实施方式为，在玻璃基板上利用等离子体化学气相沉积法（PECVD）沉积一层厚度在
Figure BDA0000469009670000061
范围内的缓冲层(Buffer)；沉积材料可以为单层的氧化硅（SiOx）膜层或氮化硅（SiNx）膜层，或者为氧化硅（SiOx）和氮化硅（SiNx）的叠层。
形成SiNx膜层的反应气体可以为硅烷（SiH4）、氨气（NH3）、氮气（N2）的混合气体，或者为二氯化硅（SiH2Cl2）、NH3、N2的混合气体；形成SiOx膜层的反应气体可以为SiH4、NH3、氧气（O2）的混合气体，或者为SiH2Cl2、NH3、O2的混合气体。
S12、形成非晶硅层。
通过镀膜工艺在衬底基板上形成覆盖整个衬底基板的非晶硅层。
具体地，通过镀膜工艺在图2所示的缓冲层11上，形成如图3所示的覆盖整个衬底基板1的非晶硅层（a-Si层）12；
具体地，沉积厚度为的a-Si层，对应的反应气体可以为SiH4和H2的混合气体或者SiH2Cl2和H2的混合气体。
步骤S12形成的非晶硅层用于在以下步骤S15中形成多晶硅层。
S13、对非晶硅层进行热退火工艺。
对衬底基板上的非晶硅层进行热退火工艺，以实现去除非晶硅层中的氢气的目的，防止在后续步骤在激光退火时发生氢爆。
上述除氢步骤采用热退火工艺，热退火工艺的温度范围可以根据实际需求设定，如果衬底基板为玻璃基板，热退火工艺的温度可适当高一些，如果衬底基板为柔性基板，热退火工艺的温度范围可适当低一些，保证不影响柔性基板的作为正常的基板即可。
步骤S13为可选项。
S14、离子注入法对待形成的欧姆接触层的区域进行离子注入。
通过构图工艺在图3所示的非晶硅上形成n型或p型掺杂区图形，通过离子注入法对所述n型或p型掺杂区进行离子注入，形成图4所示的第一初始欧姆接触层14和第二初始欧姆接触层15图形；
离子注入法注入的离子可以为硼（B）或磷（P）离子。图4中箭头所示的方向为离子注入时的注入方向。
此时注入非晶硅层中的离子为未激活的离子，即离子不能够起到施主或受主的作用。
具体地，参见图4，通过光刻胶层29作为掩膜，对待形成的第一初始欧姆接触层和第二初始欧姆接触层进行离子注入。
本发明所述对应区域为正对的区域。
S15、同时形成多晶硅层、欧姆接触层。
对形成有所述非晶硅层以及第一初始欧姆接触层和第二初始欧姆接触层，或者还包括初始存储电容的下电极的衬底基板进行准分子激光退火工艺，第一初始欧姆接触层和第二初始欧姆接触层统称为初始欧姆接触层，使得所述非晶硅层转化为多晶硅层，所述初始欧姆接触层中的离子激活，形成欧姆接触层。
该步骤S15通过一次准分子激光退火工艺实现多晶硅层和离子激活，避免准分子激光退火后采用热退火工艺造成工艺步骤复杂的问题，以及避免热退火工艺进行离子激活导致衬底基板整体受热限制形成柔性显示装置的问题，此外准分子激光退火工艺局部高温还可以提高多晶硅的晶格完整性。
通过该步骤简化了低温多晶硅薄膜晶体管制作工艺流程，还提高了TFT的性能，还可以实现柔性显示装置。
本发明实施例提供的准分子激光退火可以采用例如氯化氙（XeCl）、氟化氪KrF、氟化氩ArF等准分子激光器（波长308nm）来进行准分子激光退火。激光光束经过光学***后为线性光源。
优选地，所述准分子激光退火工艺的条件为：激光脉冲频率为100～400Hz，激光重叠率为90%～98%，激光脉冲宽度<100ns，激光能量密度为100～600mJ/cm2。
相比较通过热退火工艺，本发明经准分子激光退火工艺进行非晶硅向多晶硅的转化，可以实现柔性基板上制作低温多晶硅晶体管，且晶体管的性能稳定性较好。
具体ELA实施过程中，激光光束位置固定，基板固定在位移台上，通过基板移动控制激光照射的范围，使得激光束在基板的预设位置扫描。非晶硅及硼（B）分子或磷（P）分子在激光辐照下，吸收激光能量发生熔融，硼（B）分子或磷（P）分子扩散进熔融的硅中，在冷却的过程中，非晶硅变成多晶硅的同时，完成激光辅助掺杂，形成掺杂硼（B）或磷（P）离子的多晶硅区。掺杂硼（B）或磷（P）离子的多晶硅区为欧姆接触层区域。该过程由于非晶硅及硼（B）分子或磷（P）分子在激光辐照下，吸收激光能量发生熔融，硼（B）分子或磷（P）分子扩散进熔融的硅中的速率较快，且靠近硅表层的硼（B）分子或磷（P）分子的分布密度与远离硅表层的硼（B）分子或磷（P）分子的分布密度相近，即硼（B）分子或磷（P）分子从硅表层到底层的分布密度梯度较小，形成的欧姆接触层的导电性较好。
S16、形成有源层。
对步骤S15形成的多晶硅层进行图形化工艺（即构图工艺）形成设定区域的有源层。
具体实施时，参见图5，将采用光刻的方式形成对应有源层17；在实施过程中，利用光刻胶作为掩膜，进行干法刻蚀及光刻胶剥离后，形成有源层17。
本发明所述的有源层也称为多晶硅岛状物。
S17、形成栅极绝缘层。
参见图6，采用PECVD沉积一层栅极绝缘层18（Gate Insulator，GI），厚度为
Figure BDA0000469009670000091
材料可以是SiNx的单层或者是SiNx和SiOx的叠层。
S18、栅极的形成过程。
参见图6，采用溅射法（Sputter）沉积一层栅极（Gate）金属或合金层，厚度为
Figure BDA0000469009670000092
所述金属或合金层可以由金属钼（Mo）、金属铝（Al）、金属铜（Cu）、金属钨（W）或者金属钼（Mo）、金属铝（Al）、金属铜（Cu）、金属钨（W）中至少两种合金形成，然后通过构图工艺形成栅极19图形。
S19、形成第一绝缘层。
位于栅极上方覆盖整个衬底基板的第一绝缘层，如图7所示的第一绝缘层21。
具体地，采用PECVD沉积一层绝缘层，厚度为绝缘层成分可以是SiNx、SiOx；然后进行光刻，干法刻蚀，最终形成用于与第一欧姆接触层14和第二欧姆接触层15相连的过孔。
步骤S11至步骤S19为薄膜晶体管的形成过程。
进一步地，在上述步骤S11至步骤S19薄膜晶体管的形成过程之后，阵列基板的形成过程还包括：
形成存储电容的下电极16和存储电容的上电极图形20的过程。
优选地，在步骤S14中对待形成的第一初始欧姆接触层和第二初始欧姆接触层进行离子注入之后，进一步地，还对待形成的存储电容的下电极对应区域进行离子注入，形成初始存储电容的下电极16。
所述存储电容的下电极通过在非晶硅中掺杂实现，即在非晶硅层中对应区域注入杂质离子（硼（B）或磷（P）离子），使得半导体性质的非晶硅层变为导电层。
优选地，在步骤S18中，通过构图工艺形成栅极19图形的过程中，进一步地还可以同时形成位于存储电容的下电极正上方用于与存储电容的下电极形成存储电容的上电极图形20。
S20、还包括用于与第一欧姆接触层14和第二欧姆接触层15电性相连的源极、漏极的形成过程。
通过溅射或者热蒸镀的方法沉积金属或合金层，厚度为
Figure BDA0000469009670000103
材料可以选用Mo、Al、Cu、W等金属，或者是几种金属的合金，经过光刻并刻蚀以后形成如图7所示的源极22、漏极23、存储电容的下电极引线24。
S21、形成第二绝缘层。
如图8所示，还包括位于源极22、漏极23、存储电容的下电极引线24上方的第二绝缘层25。具体地，利用PECVD沉积第二层绝缘层，厚度为
Figure BDA0000469009670000101
Figure BDA0000469009670000102
成分可以是SiNx、SiOx，然后进行光刻，干法刻蚀，最终形成与漏极23和下电极引线24相接触的过孔。第二绝缘层也可以用感光的绝缘树脂代替。
S22、形成像素电极。
参见图8，位于第二绝缘层25上方通过过孔与漏极和存储电容的下电极相连的像素电极26。具体地，利用磁控溅射设备（Sputter）沉积一层透明导电膜，成分可以是氧化铟锡（ITO）、氧化铟锌（IZO）或氧化铝锌等材料，厚度为
Figure BDA0000469009670000104
然后用普通的掩模板进行曝光工艺，显影并湿法刻蚀后，生成像素电极。
本发明实施例提供一种薄膜晶体管，采用上述实施例提供的低温多晶硅薄膜晶体管的制作方法制作而成。
本发明实施例还提供一种阵列基板，采用上述阵列基板的制作方法制作而成。
本发明实施例提供的低温多晶硅薄膜晶体管的制作方法，在形成多晶硅层之前进行离子注入工艺，在形成多晶硅层的过程中同时形成欧姆接触层，即进行准分子激光退火工艺时形成欧姆接触层，简化了制作工艺，并且形成欧姆接触层的掺杂离子通过准分子激光退火驱入的方式形成，避免了通过离子注入引起薄膜晶体管的相关缺陷和不良现象，提高了薄膜晶体管的性能。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

1.一种低温多晶硅薄膜晶体管的制作方法，其特征在于，包括：在衬底基板上形成有源层和欧姆接触层的过程；
其中，形成所述有源层和欧姆接触层，具体为：
在衬底基板上形成非晶硅层；
采用离子注入法对所述非晶硅层至少在待形成欧姆接触层的区域进行杂质离子的注入，待形成的欧姆接触层的区域形成初始欧姆接触层；
对杂质离子注入工艺后的非晶硅层进行准分子激光退火工艺；准分子激光退火工艺后的非晶硅层晶化为多晶硅层，初始欧姆接触层形成最终的欧姆接触层；
对准分子激光退火工艺后的多晶硅层进行构图工艺，形成所述有源层。
2.根据权利要求1所述的制作方法，其特征在于，所述准分子激光退火工艺的条件为：激光脉冲频率为100～400Hz，激光重叠率为90%～98%，激光脉冲宽度<100ns，激光能量密度为100～600mJ/cm2。
3.根据权利要求1所述的制作方法，其特征在于，在形成所述非晶硅层之后，杂质离子注入之前，还包括：对所述非晶硅层进行热退火工艺处理。
4.根据权利要求1所述的制作方法，其特征在于，在形成所述非晶硅层之前还包括：在所述衬底基板上形成一层覆盖整个衬底基板的缓冲层。
5.根据权利要求1所述的制作方法，其特征在于，所述采用离子注入法对所述非晶硅层待形成欧姆接触层的区域进行杂质离子的注入，具体为：采用离子注入法对所述非晶硅层待形成欧姆接触层的区域进行硼或磷杂质离子的注入，形成初始欧姆接触层。
6.一种阵列基板的制作方法，其特征在于，包括：
在衬底基板上形成低温多晶硅薄膜晶体管的过程以及形成存储电容的下电极的过程；
所述低温多晶硅薄膜晶体管的形成过程至少包括如下步骤：
在衬底基板上形成有源层和欧姆接触层的过程；
其中，形成所述有源层和欧姆接触层，具体为：
在衬底基板上形成非晶硅层；
采用离子注入法对所述非晶硅层至少在待形成欧姆接触层的区域进行杂质离子的注入，待形成的欧姆接触层的区域形成初始欧姆接触层；
对杂质离子注入工艺后的非晶硅层进行准分子激光退火工艺；准分子激光退火工艺后的非晶硅层晶化为多晶硅层，初始欧姆接触层形成最终的欧姆接触层；
对准分子激光退火工艺后的多晶硅层进行构图工艺，形成所述有源层。
7.根据权利要求6所述的方法，其特征在于，所述采用离子注入法对所述非晶硅层的待形成欧姆接触层的区域进行杂质离子的注入的同时，还包括：在非晶硅层上待形成的存储电容的下电极对应的区域进行杂质离子的注入，待形成的存储电容的下电极对应的区域形成初始存储电容的下电极。
8.根据权利要求6或7所述的方法，其特征在于，所述低温多晶硅薄膜晶体管的形成过程还包括权利要求2-5任一所述的低温多晶硅薄膜晶体管的制作方法。
9.一种低温多晶硅薄膜晶体管，其特征在于，采用权利要求1-5任一权项所述的低温多晶硅薄膜晶体管的制作方法制作而成。
10.一种阵列基板，其特征在于，采用权利要求6-8任一所述的阵列基板的制作方法制作而成。
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