CN105655407A - 多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置 - Google Patents

多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置 Download PDF

Info

Publication number
CN105655407A
CN105655407A CN201610140453.3A CN201610140453A CN105655407A CN 105655407 A CN105655407 A CN 105655407A CN 201610140453 A CN201610140453 A CN 201610140453A CN 105655407 A CN105655407 A CN 105655407A
Authority
CN
China
Prior art keywords
electrode
layer
intermediate insulating
insulating layer
drain electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610140453.3A
Other languages
English (en)
Inventor
刘政
李小龙
皇甫鲁江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201610140453.3A priority Critical patent/CN105655407A/zh
Publication of CN105655407A publication Critical patent/CN105655407A/zh
Priority to EP16854586.1A priority patent/EP3427302B1/en
Priority to PCT/CN2016/105065 priority patent/WO2017152644A1/en
Priority to US15/519,313 priority patent/US10312311B2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Inorganic Chemistry (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明实施例提供了一种多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置，涉及显示技术领域，在保证沟道长度的基础上，可降低薄膜晶体管的尺寸。该多晶硅薄膜晶体管包括设置在衬底上的源电极和漏电极、有源层、栅绝缘层以及栅电极；其中，位于所述源电极和所述漏电极之间的所述有源层的长度大于所述源电极和所述漏电极之间的直线距离。用于对沟道长度具有较高要求的多晶硅薄膜晶体管以及对尺寸要求较高的多晶硅薄膜晶体管。

Description

多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置。
背景技术
低温多晶硅薄膜晶体管(LowTemperaturePoly-Silicon-ThinFilmTransistor，简称LTPS-TFT)显示器具有高分辨率、反应速度快、高亮度、高开口率等优点，加上由于LTPS的特点，使得其具有高的电子移动率。
如图1所示，目前低温多晶硅薄膜晶体管包括设置在衬底10上的有源层11、设置在有源层11上的栅绝缘层12、设置在栅绝缘层12上的栅电极13、设置在栅电极13上的中间绝缘层14、以及设置在中间绝缘层14上的源电极15和漏电极16，源电极15和漏电极16通过中间绝缘层14和栅绝缘层12上的过孔与有源层11接触。基于该结构，可通过四次构图工艺形成。
对于薄膜晶体管来说，沟道长度是一个较为关键的指标，特别是对有机电致发光二极管显示器中的驱动薄膜晶体管来说，其沟道长度需要达到几十微米，因而导致现有技术中的低温多晶硅薄膜晶体管的尺寸较大，不利于高分辨率的实现。
发明内容
本发明的实施例提供一种多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置，在保证沟道长度的基础上，可降低薄膜晶体管的尺寸。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，提供一种多晶硅薄膜晶体管，包括设置在衬底上的源电极和漏电极、有源层、栅绝缘层以及栅电极；其中，位于所述源电极和所述漏电极之间的所述有源层的长度大于所述源电极和所述漏电极之间的直线距离。
优选的，所述多晶硅薄膜晶体管包括中间绝缘层，所述中间绝缘层设置在所述有源层的靠近所述衬底的一侧；其中，所述中间绝缘层中与所述源电极和所述漏电极之间的区域对应的部分区域镂空。
进一步优选的，所述源电极和所述漏电极设置在所述有源层的靠近所述衬底的一侧，所述中间绝缘层设置在所述源电极和所述漏电极与所述有源层之间；所述栅绝缘层和所述栅电极设置在所述有源层的远离所述衬底的一侧。
优选的，所述中间绝缘层的厚度为
优选的，在所述中间绝缘层的镂空区域处，所述中间绝缘层的坡度角在30°～60°之间。
第二方面，提供一种阵列基板，包括上述第一方面的多晶硅薄膜晶体管以及与所述多晶硅薄膜晶体管的漏电极电联接的第一电极。
优选的，所述第一电极为像素电极；或者，所述第一电极为底电极，在此情况下，所述阵列基板还包括顶电极，以及位于所述底电极和所述顶电极之间的有机材料功能层。
第三方面，提供一种显示装置，包括上述第二方面的阵列基板。
第四方面，提供一种多晶硅薄膜晶体管的制备方法，包括在衬底上形成源电极和漏电极、有源层、栅绝缘层以及栅电极；位于所述源电极和所述漏电极之间的所述有源层的长度大于所述源电极和所述漏电极之间的直线距离。
优选的，在形成所述有源层之前，所述方法还包括：形成中间绝缘层，所述中间绝缘层中与所述源电极和所述漏电极之间的区域对应的部分区域被刻蚀，形成镂空区域。
在此基础上，所述制备方法具体包括：
在衬底上通过一次构图工艺形成所述源电极和所述漏电极；在形成有所述源电极和所述漏电极的衬底上，通过一次构图工艺形成所述中间绝缘层；在形成有所述中间绝缘层的衬底上，通过一次构图工艺形成多晶硅层；在形成有所述多晶硅层的衬底上，形成所述栅绝缘层，并通过一次构图工艺形成所述栅电极；以所述栅电极为掩模，对所述多晶硅层进行离子注入，形成所述有源层。
优选的，所述中间绝缘层的厚度为
优选的，在所述中间绝缘层的所述镂空区域处，所述中间绝缘层的坡度角在30°～60°之间。
本发明实施例提供了一种多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置，通过使位于源电极和漏电极之间的有源层的长度大于源电极和漏电极之间的直线距离，可以在保证沟道长度的基础上，降低薄膜晶体管的尺寸，此外，也可以在与现有技术中源电极和漏电极之间的直线距离相同的情况下，提高沟道的长度，以适用于较长沟道长度要求的薄膜晶体管。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的一种低温多晶硅薄膜晶体管的结构示意图；
图2为本发明实施例提供的一种多晶硅薄膜晶体管的结构示意图一；
图3为本发明实施例提供的一种多晶硅薄膜晶体管的结构示意图二；
图4为本发明实施例提供的一种阵列基板的结构示意图一；
图5为本发明实施例提供的一种阵列基板的结构示意图二；
图6为本发明实施例提供的一种阵列基板的结构示意图三；
图7为本发明实施例提供的一种阵列基板的结构示意图四；
图8a-图8c为形成图2所示的多晶硅薄膜晶体管的过程示意图。
附图标记：
1-多晶硅薄膜晶体管；2-像素电极；3-公共电极；4-阳极；5-阴极；6-有机材料功能层；10-衬底；11-有源层；12-栅绝缘层；13-栅电极；14-中间绝缘层；141-镂空区域；142-过孔；15-源电极；16-漏电极；17-多晶硅层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种多晶硅薄膜晶体管1，如图2和图3所示，包括设置在衬底10上的源电极15和漏电极16、有源层11、栅绝缘层12以及栅电极13；其中，位于源电极15和漏电极16之间的有源层11的长度大于源电极15和漏电极16之间的直线距离。
其中，有源层11的材料包括多晶硅，为了提高源电极15和漏电极16与有源层11之间的欧姆接触，可进行相应的n型或p型掺杂。即，有源层11可以包括与源电极15和漏电极16分别对应且经过掺杂的源极区和漏极区，以及位于源极区和漏极区之间的沟道区。
为了增大源电极15和漏电极16之间的有源层11的长度而避免增大源电极15和漏电极16之间的间距(即源电极15和漏电极16之间的直线距离)，可以使有源层11在源电极15和漏电极16之间的相对衬底10的高度呈不同变化，在此基础上，可在源电极15和漏电极16之间，有源层11的下方设置特定的图案来实现，具体在此不做限定。
需要说明的是，本领域技术人员应该明白，位于源电极15和漏电极16之间的有源层11的实际长度，即为沟道长度。
此外，本发明实施例的多晶硅薄膜晶体管1可以是任意结构的薄膜晶体管，例如可以是底栅型、顶栅型、双栅型等结构。
本发明实施例提供了一种多晶硅薄膜晶体管1，通过使位于源电极15和漏电极16之间的有源层11的长度大于源电极15和漏电极16之间的直线距离，可以在保证沟道长度的基础上，降低薄膜晶体管的尺寸，此外，也可以在与现有技术中源电极15和漏电极16之间的直线距离相同的情况下，提高沟道的长度，以适用于较长沟道长度要求的薄膜晶体管。
优选的，如图2和图3所示，所述多晶硅薄膜晶体管1包括中间绝缘层14，该中间绝缘层14设置在有源层11的靠近衬底10的一侧；其中，中间绝缘层14中与源电极15和漏电极16之间的区域对应的部分区域镂空。
此处，可通过将中间绝缘层14中与源电极15和漏电极16之间的区域对应的部分区域刻蚀掉，形成镂空区域141，以使该有源层11形成类似“M”形状的结构，即，使有源层11在源电极15和漏电极16之间的高度呈不同变化，而使其实际长度大于镂空区域141的宽度。
需要说明的是，上述“M”形状只是为便于理解进行的类比，不是必须形成严格的“M”形状，如“M”的底端可以形成一段平台。
本发明实施例中，通过在有源层11下方设置中间绝缘层14，且使中间绝缘层11的部分区域镂空，这样在形成有源层11时，可使其形状类似“M”形状，因而在与现有技术相同薄膜晶体管尺寸的情况下，可以提供更长的沟道长度，或者在相同沟道长度要求时比现技术的薄膜晶体管尺寸更小，且多晶硅薄膜晶体管的结构简单。
进一步优选的，如图2所示，源电极15和漏电极16设置在有源层11的靠近衬底10的一侧，中间绝缘层14设置在源电极15和漏电极16与有源层11之间；栅绝缘层12和栅电极13设置在有源层11的远离衬底10的一侧。
其中，当有源层11的形状类似“M”形状时，栅电极13的形状则类似“V”形状。
这里，“V”形状也只是为便于理解进行的类比，不是必须形成严格的“V”形状，如“V”的底端可以形成一段平台，即形成近似“U”形状)。
基于此，则可通过四次构图工艺形成该多晶硅薄膜晶体管1，具体的，通过第一次构图工艺形成源电极15和漏电极16，通过第二次构图工艺形成中间绝缘层14，通过第三次构图工艺形成有源层11，通过第四次构图工艺形成栅电极13。这样，与现有技术相比，不会导致构图工艺次数以及工艺复杂度的增加。
优选的，中间绝缘层14的厚度为
其中，中间绝缘层14的材料可以为无机材料，例如氮化硅和/或氧化硅，当包括氮化硅或氧化硅时，中间绝缘层14可以只包括单层的氮化硅或氧化硅，当包括氮化硅和氧化硅时，中间绝缘层14可以包括一层氮化硅和一层氧化硅。在此情况下，中间绝缘层14厚度优选为
中间绝缘层14的材料也可以为有机材料，例如亚克力或聚酰亚胺等有机材料。在此情况下，中间绝缘层14厚度优选为
当然，中间绝缘层14也可以采用无机材料和有机材料的叠层形成。在此情况下，中间绝缘层14厚度优选为
本发明实施例中，通过设置中间绝缘层14的厚度，可在不同的多晶硅薄膜晶体管1尺寸要求的情况下，满足对沟道长度的要求。
优选的，在中间绝缘层14的镂空区域141处，中间绝缘层14的坡度角在30°～60°之间。即，镂空区域141的侧壁的坡度角应在30°～60°之间。
这样，可避免由于中间绝缘层14的镂空区域141的坡度角太大而导致后续工艺中发生的薄膜开裂的问题。
本发明实施例还提供一种阵列基板，其包括多个像素单元，每个像素单元均包括上述的多晶硅薄膜晶体管1以及与该多晶硅薄膜晶体管1的漏电极16电联接的第一电极。
具体的，如图4所示，当所述阵列基板为液晶显示器(LiquidCrystalDisplay，简称LCD)的阵列基板时，上述第一电极为像素电极2。
进一步的，如图5和图6所示，该阵列基板还可以包括公共电极3。在此情况下，对于高级超维场转换型(Advanced-superDimensionalSwitching，简称ADS)阵列基板而言，如图5所示，像素电极2和公共电极3可以不同层设置，其中在上的电极为条状电极，在下的电极为板状电极。或者，对于共平面切换型(In-PlaneSwitch，简称IPS)阵列基板而言，如图6所示，像素电极2和公共电极3可以同层间隔设置，且均为条状电极。
当所述阵列基板为有机电致发光二极管(OrganicLight-EmittingDiode，简称OLED)显示器的阵列基板时，上述第一电极为底电极，在此情况下，该阵列基板还包括顶电极，以及位于顶电极和顶电极之间的有机材料功能层。具体的，如图7所示，对于正置型有机电致发光二极管显示器的阵列基板，底电极可以为阳极4，顶电极为阴极5，有机材料功能层6位于阳极4和阴极5之间；当然，对于反置型有机电致发光二极管显示器的阵列基板，底电极可以为阴极，顶电极为阳极，有机材料功能层位于阴极和阳极之间。
其中，有机材料功能层6至少包括发光层，进一步的还可以包括电子传输层和空穴传输层。在此基础上，为了能够提高电子和空穴注入发光层的效率，有机材料功能层6还可以包括设置在阴极5与电子传输层之间的电子注入层，以及在发光层与空穴注入层之间的空穴传输层。
具体的，根据阳极4和阴极5的材料的不同，上述阵列基板可以分为单面发光型和双面发光型；即：当阳极4和阴极5中其中一个电极的材料为不透明材料时，上述阵列基板为单面发光型；当阳极4和阴极5的材料均为透明材料时，上述阵列基板为双面发光型。
对于单面发光型阵列基板，根据阳极4和阴极5的材料的不同，又可以分为上发光型和下发光型。具体的，当阳极4靠近衬底10设置，阴极5远离衬底10设置，且阳极4的材料为透明导电材料，阴极5的材料为不透明导电材料时，由于光从阳极4、再经衬底10一侧出射，因此，可以称为下发光型；当阳极4的材料为不透明导电材料，阴极5的材料为透明或半透明导电材料时，由于光从阴极5一侧出射，因此，可以称为上发光型。当然，也可以将上述阳极4和阴极5的相对位置进行替换，在此再赘述。
本发明实施例提供了一种阵列基板，通过将其包括的多晶硅薄膜晶体管1中位于源电极15和漏电极16之间的有源层11的长度，设计为大于源电极15和漏电极16之间的直线距离，可以在保证沟道长度的基础上，降低薄膜晶体管的尺寸，从而可提高该阵列基板应用的显示装置的分辨率。此外，在应用于OLED时，可避免由于沟道长度的要求而导致薄膜晶体管尺寸的增加。
本发明实施例还提供一种显示装置，包括上述的阵列基板。
具体的，显示装置可以是LCD电视、笔记本电脑、平板电脑，智能手机等。也可以是OLED电视、笔记本电脑、平板电脑，智能手机等。
本发明实施还提供一种多晶硅薄膜晶体管的制备方法，参考图2和图3所示，包括：在衬底10上形成源电极15和漏电极16、有源层11、栅绝缘层12以及栅电极13；其中，位于源电极15和漏电极16之间的有源层11的长度大于源电极15和漏电极16之间的直线距离。
其中，在形成有源层11之前，需先形成多晶硅层，然后通过对多晶硅层的与源电极15和漏电极16分别对应的区域进行n型或p型掺杂而形成有源层11。
为了增大源电极15和漏电极16之间的有源层11的长度而避免增大源电极15和漏电极16之间的间距(即源电极15和漏电极16之间的直线距离)，可以使有源层11在源电极15和漏电极16之间的相对衬底10的高度呈不同变化，在此基础上，可在源电极15和漏电极16之间，有源层11的下方设置特定的图案来实现，具体在此不做限定。
本发明实施例提供了一种多晶硅薄膜晶体管1的制备方法，通过使位于源电极15和漏电极16之间的有源层11的长度大于源电极15和漏电极16之间的直线距离，可以在保证沟道长度的基础上，降低薄膜晶体管的尺寸，此外，也可以在与现有技术中源电极15和漏电极16之间的直线距离相同的情况下，提高沟道的长度，以适用于较长沟道长度要求的薄膜晶体管。
优选的，参考图2和图3所示，在形成有源层11之前，所述方法还包括：形成中间绝缘层14，该中间绝缘层14中与源电极15和漏电极16之间的区域对应的部分区域被刻蚀，形成镂空区域141。
即，可将有源层11的两端垫高，并使有源层11的与源电极15和漏电极16之间的区域对应的部分区域被刻蚀形成镂空区域141，而使有源层11形成类似“M”形状的结构，从而使其实际长度大于镂空区域141的宽度。
本发明实施例中，通过在有源层11下方形成中间绝缘层14，且使中间绝缘层11的部分区域镂空，这样在形成有源层11时，可使其形状类似“M”形状，因而在与现有技术相同薄膜晶体管尺寸的情况下，可以提供更长的沟道长度，或者在相同沟道长度要求时比现技术的薄膜晶体管尺寸更小，且多晶硅薄膜晶体管的结构简单。
在此基础上，所述多晶硅薄膜晶体管1的制备方法具体可以包括如下步骤：
S10、如图8a所示，在衬底10上通过一次构图工艺形成源电极15和漏电极16。
其中，源电极15和漏电极16可以为单层、两层或两层以上结构，其材料包括金属、金属合金如钼、铝、钼钨等，厚度可以为 优选厚度为
具体的，可先在衬底10上通过溅射、等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、大气压化学气相沉积(APCVD)、电子回旋谐振化学气相沉积(ECR-CVD)等方法形成源漏金属薄膜，之后通过光刻工艺形成源电极15和漏电极16。
此处，在衬底10可以为预先清洗的玻璃等透明基板。
S11、如图8b所示，在形成有源电极15和漏电极16的衬底10上，通过一次构图工艺形成中间绝缘层14。
其中，中间绝缘层14可以为单层、两层或两层以上结构，其厚度可以为中间绝缘层14的材料可以为无机材料例如氧化硅、氮化硅等，此时厚度优选为中间绝缘层14的材料也可以为有机材料，例如亚克力或聚酰亚胺等有机材料，此时厚度优选为中间绝缘层14也可以采用上述无机和有机材料叠层形成，此时厚度优选为
具体的，可采用PECVD、LPCVD、APCVD或ECR-CVD等方法形成绝缘薄膜，之后通过光刻工艺形成中间绝缘层14。
需要说明的是，中间绝缘层14除包括上述的镂空区域141外，还应该包括用于使后续形成的有源层11与源电极15和漏电极16接触的过孔142。
其中，为了防止后续工艺中可能发生的薄膜开裂问题，中间绝缘层14的镂空区域141的侧壁的坡度角需做得尽可能小，优选为30°～60°之间。
S12、如图8c所示，在形成有中间绝缘层14的衬底10上，通过一次构图工艺形成多晶硅层17。
该多晶硅层17通过中间绝缘层14上的过孔142与源电极15和漏电极16接触。由于中间绝缘层14中镂空区域141的存在，该多晶硅层17的形状类似“M”形状。
其中，多晶硅层17的厚度可以为优选厚度为
形成多晶硅层17例如可以为：采用PECVD、LPCVD、APCVD或ECR-CVD等方法在形成有中间绝缘层14的衬底10上沉积非晶硅薄膜，之后通过光刻工艺在有源层区域形成非晶硅层，然后采用高温烤箱对非晶硅层进行脱氢工艺处理，以防止在晶化过程中出现氢爆现象以及降低晶化后薄膜内部的缺陷态密度作用。脱氢工艺完成后，进行低温多晶硅(LowTemperaturePoly-Silicon，LTPS)工艺过程，采用激光退火工艺(ELA)、金属诱导结晶工艺(MIC)、固相结晶工艺(SPC)等结晶化手段对非晶硅层进行结晶化处理，形成多晶硅层17。
此处，也可以先对非晶硅薄膜进行结晶化处理，形成多晶硅薄膜，然后通过光刻工艺在有源层区域形成多晶硅层17。
其中，本发明实施例并不限于是上述的低温多晶硅工艺过程，也可以是高温多晶硅，具体在此不做限定，只要能形成所述多晶硅层即可。
当然，也可以直接在形成有中间绝缘层14的衬底10上采用PECVD、LPCVD或者溅射方法，形成多晶硅层17，此时，优选沉积温度控制在600℃以下。
S13、参考图2所示，在形成有所述多晶硅层17的衬底10上，形成栅绝缘层12，并通过一次构图工艺所述栅电极13。
由于上述多晶硅层17的形状类似“M”形状，因此，形成的栅电极13的形状则类似“V”形状。
其中，栅绝缘层12可以为单层、两层或两层以上结构，例如采用单层的氧化硅、氮化硅或者二者的叠层。栅绝缘层12的厚度可以为优选厚度为
栅电极13可以为单层、两层或两层以上结构，其材料包括金属、金属合金如钼、铝、钼钨等，厚度可以为优选厚度为
具体的，可采用PECVD、LPCVD、APCVD或ECR-CVD等方法形成栅绝缘层12，并形成栅金属薄膜，之后通过光刻工艺形成栅电极13。
S14、参考图2所示，以栅电极13为掩模，对多晶硅层17进行离子注入，形成有源层11。
即，对多晶硅层17的与源电极15和漏电极16相对应的区域进行离子注入工艺，而使有源层11包括源极区和漏极区，未经过离子注入的多晶硅层17的区域则形成沟道区(即，沟道区位于源极区和漏极区之间)。
具体的，离子注入工艺可采用具有质量分析仪的离子注入、不具有质量分析仪的离子云式注入、等离子注入或者固态扩散式注入等方法，优选采用主流的离子云式注入。可根据设计需要采用含硼如B2H6/H2，或者含磷如PH3/H2的混合气体进行注入，离子注入能量可为10～200keV，优选能量在40～100keV，注入剂量可在1x1011～1x1020atoms/cm3范围内，优选剂量在1x1014～8x1018atoms/cm3。
此外，在离子注入之后可通过快速热退火、激光退火或炉退火的方法进行激活。其中，炉退火的方法较为经济、简单，均匀性较佳。
基于上述S10-S14，通过四次构图工艺便可制备形成如图2所示的多晶硅薄膜晶体管1。这样，与现有技术相比，不会导致构图工艺次数以及工艺复杂度的增加。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (13)

1.一种多晶硅薄膜晶体管，包括设置在衬底上的源电极和漏电极、有源层、栅绝缘层以及栅电极；其特征在于，位于所述源电极和所述漏电极之间的所述有源层的长度大于所述源电极和所述漏电极之间的直线距离。
2.根据权利要求1所述的多晶硅薄膜晶体管，其特征在于，所述多晶硅薄膜晶体管包括中间绝缘层，所述中间绝缘层设置在所述有源层的靠近所述衬底的一侧；
其中，所述中间绝缘层中与所述源电极和所述漏电极之间的区域对应的部分区域镂空。
3.根据权利要求2所述的多晶硅薄膜晶体管，其特征在于，所述源电极和所述漏电极设置在所述有源层的靠近所述衬底的一侧，所述中间绝缘层设置在所述源电极和所述漏电极与所述有源层之间；
所述栅绝缘层和所述栅电极设置在所述有源层的远离所述衬底的一侧。
4.根据权利要求2或3所述的多晶硅薄膜晶体管，其特征在于，所述中间绝缘层的厚度为
5.根据权利要求2或3所述的多晶硅薄膜晶体管，其特征在于，在所述中间绝缘层的镂空区域处，所述中间绝缘层的坡度角在30°～60°之间。
6.一种阵列基板，其特征在于，包括权利要求1-5任一项所述的多晶硅薄膜晶体管以及与所述多晶硅薄膜晶体管的漏电极电联接的第一电极。
7.根据权利要求6所述的阵列基板，其特征在于，所述第一电极为像素电极；或者，
所述第一电极为底电极，所述阵列基板还包括顶电极，以及位于所述底电极和所述顶电极之间的有机材料功能层。
8.一种显示装置，其特征在于，包括权利要求6或7所述的阵列基板。
9.一种多晶硅薄膜晶体管的制备方法，包括在衬底上形成源电极和漏电极、有源层、栅绝缘层以及栅电极；其特征在于，位于所述源电极和所述漏电极之间的所述有源层的长度大于所述源电极和所述漏电极之间的直线距离。
10.根据权利要求9所述的制备方法，其特征在于，在形成所述有源层之前，所述方法还包括：形成中间绝缘层，所述中间绝缘层中与所述源电极和所述漏电极之间的区域对应的部分区域被刻蚀，形成镂空区域。
11.根据权利要求10所述的制备方法，其特征在于，所述制备方法具体包括：
在衬底上通过一次构图工艺形成所述源电极和所述漏电极；
在形成有所述源电极和所述漏电极的衬底上，通过一次构图工艺形成所述中间绝缘层；
在形成有所述中间绝缘层的衬底上，通过一次构图工艺形成多晶硅层；
在形成有所述多晶硅层的衬底上，形成所述栅绝缘层，并通过一次构图工艺形成所述栅电极；
以所述栅电极为掩模，对所述多晶硅层进行离子注入，形成所述有源层。
12.根据权利要求10或11所述的制备方法，其特征在于，所述中间绝缘层的厚度为
13.根据权利要求10或11所述的制备方法，其特征在于，在所述中间绝缘层的所述镂空区域处，所述中间绝缘层的坡度角在30°～60°之间。
CN201610140453.3A 2016-03-11 2016-03-11 多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置 Pending CN105655407A (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201610140453.3A CN105655407A (zh) 2016-03-11 2016-03-11 多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置
EP16854586.1A EP3427302B1 (en) 2016-03-11 2016-11-08 Thin film transistor, fabrication method thereof, array substrate, and display device
PCT/CN2016/105065 WO2017152644A1 (en) 2016-03-11 2016-11-08 Thin film transistor, fabrication method thereof, array substrate, and display device
US15/519,313 US10312311B2 (en) 2016-03-11 2016-11-08 Thin film transistor, fabrication method thereof, array substrate, and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610140453.3A CN105655407A (zh) 2016-03-11 2016-03-11 多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置

Publications (1)

Publication Number Publication Date
CN105655407A true CN105655407A (zh) 2016-06-08

Family

ID=56493514

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610140453.3A Pending CN105655407A (zh) 2016-03-11 2016-03-11 多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置

Country Status (4)

Country Link
US (1) US10312311B2 (zh)
EP (1) EP3427302B1 (zh)
CN (1) CN105655407A (zh)
WO (1) WO2017152644A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017152644A1 (en) * 2016-03-11 2017-09-14 Boe Technology Group Co., Ltd. Thin film transistor, fabrication method thereof, array substrate, and display device
CN108803171A (zh) * 2018-06-27 2018-11-13 深圳市华星光电技术有限公司 阵列基板、液晶显示屏及阵列基板制造方法
CN109411545A (zh) * 2018-09-30 2019-03-01 南京中电熊猫平板显示科技有限公司 一种薄膜晶体管及其制造方法
CN114005881A (zh) * 2021-10-27 2022-02-01 云谷（固安）科技有限公司 薄膜晶体管及其制备方法、像素电路

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102586145B1 (ko) * 2018-12-10 2023-10-05 엘지디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 이를 포함하는 전자장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567958A (en) * 1995-05-31 1996-10-22 Motorola, Inc. High-performance thin-film transistor and SRAM memory cell
JP2003273364A (ja) * 2002-03-19 2003-09-26 Matsushita Electric Ind Co Ltd 薄膜トランジスタ及び液晶表示装置
CN102782822A (zh) * 2010-03-08 2012-11-14 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06216390A (ja) * 1993-01-19 1994-08-05 Sony Corp 薄膜トランジスタおよびその製造方法
JP3645755B2 (ja) * 1999-09-17 2005-05-11 日本電気株式会社 薄膜トランジスタおよびその製造方法
KR101189279B1 (ko) * 2006-01-26 2012-10-09 삼성디스플레이 주식회사 표시장치와 이의 제조방법
KR101284697B1 (ko) * 2006-06-30 2013-07-23 엘지디스플레이 주식회사 액정표시장치용 어레이 기판과 그 제조방법
US7419858B2 (en) * 2006-08-31 2008-09-02 Sharp Laboratories Of America, Inc. Recessed-gate thin-film transistor with self-aligned lightly doped drain
KR101391964B1 (ko) * 2010-04-02 2014-05-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US9040981B2 (en) * 2012-01-20 2015-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2014212191A (ja) * 2013-04-18 2014-11-13 セイコーエプソン株式会社 半導体装置、電気光学装置、半導体装置の製造方法、電気光学装置の製造方法、及び電子機器
TWI566405B (zh) * 2013-11-08 2017-01-11 元太科技工業股份有限公司 有機無機混合型電晶體
CN103928474B (zh) * 2014-03-28 2017-03-15 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示面板
KR102261642B1 (ko) * 2014-08-07 2021-06-08 삼성디스플레이 주식회사 박막 트랜지스터 및 그 제조방법
KR20160066580A (ko) * 2014-12-02 2016-06-13 삼성디스플레이 주식회사 표시 장치
CN105655407A (zh) * 2016-03-11 2016-06-08 京东方科技集团股份有限公司 多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567958A (en) * 1995-05-31 1996-10-22 Motorola, Inc. High-performance thin-film transistor and SRAM memory cell
JP2003273364A (ja) * 2002-03-19 2003-09-26 Matsushita Electric Ind Co Ltd 薄膜トランジスタ及び液晶表示装置
CN102782822A (zh) * 2010-03-08 2012-11-14 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017152644A1 (en) * 2016-03-11 2017-09-14 Boe Technology Group Co., Ltd. Thin film transistor, fabrication method thereof, array substrate, and display device
US10312311B2 (en) 2016-03-11 2019-06-04 Boe Technology Group Co., Ltd Thin film transistor, fabrication method thereof, array substrate, and display device
CN108803171A (zh) * 2018-06-27 2018-11-13 深圳市华星光电技术有限公司 阵列基板、液晶显示屏及阵列基板制造方法
CN108803171B (zh) * 2018-06-27 2021-03-26 Tcl华星光电技术有限公司 阵列基板、液晶显示屏及阵列基板制造方法
CN109411545A (zh) * 2018-09-30 2019-03-01 南京中电熊猫平板显示科技有限公司 一种薄膜晶体管及其制造方法
CN114005881A (zh) * 2021-10-27 2022-02-01 云谷（固安）科技有限公司 薄膜晶体管及其制备方法、像素电路

Also Published As

Publication number Publication date
WO2017152644A1 (en) 2017-09-14
US20180138254A1 (en) 2018-05-17
EP3427302A1 (en) 2019-01-16
EP3427302A4 (en) 2019-11-06
US10312311B2 (en) 2019-06-04
EP3427302B1 (en) 2022-08-17

Similar Documents

Publication Publication Date Title
JP6896627B2 (ja) Ｔｆｔアレイ基板及びその製造方法、表示装置
US9880439B2 (en) Array substrate, method for manufacturing the same, and display device
CN106206622A (zh) 一种阵列基板及其制备方法、显示装置
CN103499906B (zh) 一种阵列基板、其制备方法及显示装置
CN105390451B (zh) 低温多晶硅tft基板的制作方法
US10068809B2 (en) TFT backplane manufacturing method and TFT backplane
CN104538429B (zh) Amoled背板的制作方法及其结构
CN104393017B (zh) 阵列基板的制作方法、阵列基板及显示装置
CN104681628A (zh) 多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置
JP2019511831A5 (zh)
CN103050410B (zh) 低温多晶硅薄膜晶体管的制造方法、低温多晶硅薄膜晶体管
CN106910748A (zh) 一种阵列基板、显示装置及其制作方法
CN104659285A (zh) 适用于amoled的tft背板制作方法及结构
CN104810382A (zh) Amoled背板的制作方法及其结构
CN105655407A (zh) 多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置
CN105762196B (zh) 一种薄膜晶体管、其制作方法及相应装置
CN104966718A (zh) Amoled背板的制作方法及其结构
CN103745954B (zh) 显示装置、阵列基板及其制造方法
KR20120127318A (ko) 폴리실리콘 활성층을 함유한 박막트랜지스터, 그 제조방법 및 어레이 기판
WO2019165824A1 (zh) 薄膜晶体管及其制造方法、阵列基板和电子装置
WO2021041060A1 (en) Hydrogen trap layer for display device and the same
CN104377230B (zh) 像素结构及其制备方法、阵列基板、显示装置
CN104779300B (zh) 一种多晶硅薄膜晶体管及其制作方法和显示装置
CN106952928B (zh) 一种tft背板的制作方法及tft背板
US10249763B2 (en) Array substrate, and display device, and fabrication methods

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20160608