CN103606562A - Buried N-type layer partial silicon-on-insulator LDMOS transistor - Google Patents
Buried N-type layer partial silicon-on-insulator LDMOS transistor Download PDFInfo
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- 239000012212 insulator Substances 0.000 title abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 181
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 181
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 179
- 239000000758 substrate Substances 0.000 claims abstract description 26
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 31
- 229910052760 oxygen Inorganic materials 0.000 claims description 31
- 239000001301 oxygen Substances 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000002210 silicon-based material Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 24
- 230000015556 catabolic process Effects 0.000 abstract description 19
- 238000009826 distribution Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- VCUFZILGIRCDQQ-KRWDZBQOSA-N N-[[(5S)-2-oxo-3-(2-oxo-3H-1,3-benzoxazol-6-yl)-1,3-oxazolidin-5-yl]methyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C1O[C@H](CN1C1=CC2=C(NC(O2)=O)C=C1)CNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F VCUFZILGIRCDQQ-KRWDZBQOSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000006880 cross-coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003100 immobilizing effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- -1 thickness is 20 μ m Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- Condensed Matter Physics & Semiconductors (AREA)
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- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a buried N-type layer partial silicon-on-insulator LDMOS transistor. The transistor structure comprises a substrate layer, a partial oxide layer, a silicon film layer and a device top layer sequentially from bottom to top. The left half portion of the partial oxide layer is a silicon window, and the right half portion of the partial oxide layer is an oxygen-buried layer. In the buried N-type layer partial silicon-on-insulator LDMOS transistor, higher electric field intensity can be introduced into the oxygen-buried layer, and therefore the breakdown voltage of the transistor is increased; and through more electrons provided by a buried N-type layer, the current driving capability of the transistor is improved, and the on-resistance of the transistor is lowered.
Description
Technical field
The present invention's design belongs to semiconductor high-voltage power integrated circuit devices field, be specifically related to a kind of N-type silicon buried layer (Buried N-type Layer that has, BNL) (the Partial Silicon-on-Insulator of silicon on partial insulative layer, PSOI) lateral double diffusion metal oxide semiconductor (Lateral Double-diffused Metal-Oxide-Semiconductor, LDMOS), english abbreviation BNL PSOI-LDMOS.
Background technology
Power integrated circuit development is mainly divided into both direction, and one is high voltage integrated circuit, and another is smart-power IC.No matter but that power integrated circuit, its most crucial problem that continues development is exactly still how further to improve the performance of High voltage power device, and also two problems (1) device power is controlled capacity: puncture voltage and operating current; (2) device performance parameter index: conducting resistance, operating frequency and switching speed etc.Therefore, multiple high-voltage LDMOS new construction is suggested, such as ladder step oxygen buried layer LDMOS, super junction LDMOS, carborundum LDMOS etc.And silicon PSOI structure on partial insulative layer not only can be improved the heat dispersion of device, and can significantly improve device electric breakdown strength, the compatibility of it and existing technique is good in addition.So, silicon LDMOS(PSOI LDMOS on partial insulative layer) arise at the historic moment, and receive much concern.Thereby be necessary to study on the basis of existing PSOI LDMOS, further improve structure, thereby make the performance such as puncture voltage, operating current, conducting resistance of device more superior.
Summary of the invention
The object of the invention is provides a kind of ldmos transistor with high-breakdown-voltage, low on-resistance, high driving ability for the continuation development of power integrated circuit.
The technical solution used in the present invention is as follows:
Have a silicon ldmos transistor on the partial insulative layer of N-type silicon buried layer, it is characterized in that, described transistor arrangement contains from bottom to top successively:
One substrate layer;
Part oxide layer, wherein left-half is silicon window, right half part oxygen buried layer;
One silicon film, silicon film top left side is the cingens source region of silicon body, right side is drain region, remainder is drift region, raceway groove is provided by the silicon body between source region and drift region, is covered on silicon dioxide in drift region, has one deck doping content to be greater than the N-type silicon buried layer of drift region;
One device top layer, in device top layer, being positioned at raceway groove top is gate oxide, drift region is expansion oxide layer,, expansion oxidated layer thickness is greater than gate oxide, gate oxide is all covered by gate electrode, and expansion oxide layer is just covered by field plate near a part for raceway groove, forms ladder step gate electrode.
The doping type of described substrate layer is P type, and doping content is 4 * 10
14cm
-3silicon materials, doping content also can need to be readjusted according to device performance, occurrence is drafted according to designing requirement and technique.
The doping type of described silicon window is consistent with substrate layer with concentration, and described oxygen buried layer adopts thickness to be less than or equal to the silicon dioxide of 4 μ m, is preferably 3 μ m's.
Described silicon film All Ranges is all silicon materials, and silicon film thickness is below 20 μ m (containing 20 μ m) generally, is preferably 20 μ m, also can be larger, but the thicker meeting of silicon fiml causes some bad problems such as device preparation, heat radiation.
Described raceway groove is long is 1-5 μ m.
The long 5 μ m in described source region and drain region, doping type is N-type, generally adopt highly doped, 10
18cm
-3on magnitude, preferably doping content is 2 * 10
19cm
-3, the concrete numerical value setting of doping content, and the concrete numerical value of length, drafted according to design by designer.Described silicon body doping type is P type, and silicon body doping content is generally 10
17cm
-3magnitude, doping content is preferably 1 * 10
17cm
-3, concrete numerical value setting, is drafted according to design by designer.
Described drift region length is preferred 90 μ m, and doping type is N-type, and doping content is 4 * 10
14cm
-3.
The silicon dioxide of thick 20nm for gate oxide, expansion oxide layer adopts the silicon dioxide of thick 50nm, and field plate length is 40 μ m, its long too short device performance (puncture voltage etc.) that all can affect.
The doping type of described silicon window is consistent with substrate layer with concentration.
Described silicon film All Ranges is all silicon materials.
In described transistor arrangement, substrate layer, silicon window, silicon film are silicon materials.
Described transistorized following arbitrary parameter is all adjustable,
(1), source region, drain region, raceway groove, drift region length is adjustable;
(2), dopant material, the doping content of source region, drain region, raceway groove, drift region, silicon buried layer, silicon window and substrate layer are adjustable;
(3), material, the thickness of gate oxide, expansion oxide layer and oxygen buried layer are adjustable;
(4), the gate electrode field plate length of top, drift region is adjustable;
(5), at total device long regularly, the length of its silicon window and oxygen buried layer is adjustable.
Silicon LDMOS(BNL PSOI-LDMOS on the partial insulative layer with N-type silicon buried layer proposed by the invention), at source-drain area, channel region, the length of drift region and substrate, material, doping type and doping content are all identical, top silicon surface thickness is identical, the thickness of oxygen buried layer or part oxygen buried layer is identical, all insulation oxide material parameters are all under consistent condition, LDMOS (Conventional Silicon-on-Insulator LDMOS with silicon on traditional insulating barrier, CSOI LDMOS), (the Conventional Partial Silicon-on-Insulator LDMOS of silicon LDMOS on traditional partial insulative layer, CPSOI LDMOS) and there is silicon LDMOS (Buried N-type Layer Silicon-on-Insulator LDMOS on the insulating barrier of N-type silicon buried layer, BNL SOI-LDMOS) compare.The present invention is stronger because two kinds of structures of silicon PSOI and N-type silicon buried layer on while introducing portion insulating barrier make high-voltage LDMOS device silicon film hold the ability of charge carrier, thereby electric current is increased, and causes conducting resistance (On-resistance, the R of device
on) reduce; On the other hand, N-type silicon buried layer can be introduced more electric field in the oxygen buried layer of below, drain region, thereby improve the voltage endurance capability of device, the silicon window of simultaneously introducing due to PSOI, make substrate layer also can share part voltage, can further improve the voltage endurance capability of device, thereby its puncture voltage of the device that proposes (Breakdown Voltage, BV) is the highest.Therefore, the present invention is the further performance optimization of high pressure SOI-LDMOS, and high voltage integrated circuit design provides a new selection.
Accompanying drawing explanation
Fig. 1 is the schematic cross-section of BNL-PSOI LDMOS of the present invention;
Fig. 2 is that the silicon window length of BNL-PSOI is 50 microns, and the silicon window length of CPSOI is 70 microns, transistorized other parameters of fixed L DMOS, the impact that the partial insulative layer silicon-on with N-type silicon buried layer distributes on device drain terminal longitudinal electric field;
The silicon window length of Fig. 3: BNL-PSOI is 50 microns, and the silicon window length of CPSOI is 70 microns, transistorized other parameters of fixed L DMOS, the impact that the partial insulative layer silicon-on with N-type silicon buried layer distributes on device drain terminal longitudinal voliage;
The silicon window length of Fig. 4: BNL-PSOI is 50 microns, and the silicon window length of CPSOI is 70 microns, transistorized other parameters of fixed L DMOS, the impact of the partial insulative layer silicon-on with N-type silicon buried layer on device upper surface Electric Field Distribution;
The silicon window length of Fig. 5: BNL-PSOI is 50 microns, and the silicon window length of CPSOI is 70 microns, transistorized other parameters of fixed L DMOS, the impact of the partial insulative layer silicon-on with N-type silicon buried layer on device lower surface Electric Field Distribution;
Fig. 6: fixing other parameters of BNL-PSOI LDMOS, change silicon length of window L
wdevice electric breakdown strength BV, oxygen buried layer are born to voltage V
iand substrate is born voltage V
subimpact;
Fig. 7; Fixing other parameters of BNL-PSOI LDMOS, change the concentration N of N-type silicon buried layer
bNLand thickness t
bNLimpact on device electric breakdown strength;
Fig. 8: fixing other parameters of BNL-PSOI LDMOS, change the concentration N of N-type silicon buried layer
bNLthe impact that drain terminal longitudinal electric field under breakdown conditions is distributed;
Fig. 9: fixing other parameters of BNL-PSOI LDMOS, change the thickness t of N-type silicon buried layer
bNLthe impact that drain terminal longitudinal electric field under breakdown conditions is distributed;
Figure 10: fixing other parameters of BNL-PSOI LDMOS, at the concentration N of different N type silicon buried layer
bNLand thickness t
bNLunder conditional combination, along with the increase of silicon length of window, puncture voltage (Breakdown Voltage, BV) and conducting resistance (On-resistance, R
on) relation;
Other parameters of Figure 11: fixed L DMOS, the silicon window variable-length of two kinds of PSOI structures, the relatively puncture voltage of four kinds of device architectures and the relation of conducting resistance.
Embodiment
Below in conjunction with concrete embodiment, the present invention is further elaborated.
As shown in Figure 1, the present invention has silicon LDMOS(BNL PSOI-LDMOS on the partial insulative layer of N-type silicon buried layer) there are successively four layers from bottom to top:
(1), substrate layer 10, doping type is P type, doping content is 4 * 10
14cm
-3silicon materials, doping content also can need to be readjusted according to device performance, occurrence is drafted according to designing requirement and technique.
(2), partial oxidation layer 20, wherein left-half is silicon window 21, its doping type is consistent with substrate with concentration, right half part oxygen buried layer 22, adopting thickness is the silicon dioxide of 3 μ m;
(3), silicon film 30, described silicon film All Ranges is all silicon materials, thickness is 20 μ m, silicon film 30 top left side are the cingens source region 31 of silicon body 32, right side is drain region 34, and remainder is drift region 33, and raceway groove is provided by the silicon body 32 between 31He drift region, source region 33, raceway groove length is 5 μ m, drift region 33 is covered on silicon dioxide, has one deck doping content to be greater than the N-type silicon buried layer 35 of drift region 33, and 5 μ m are grown in 31He drain region, source region 34, doping type is N-type, and doping content is 2 * 10
19cm
-3; Silicon body 32 doping types are P type, and doping content is 1 * 10
17cm
-3; Drift region 33 length are 90 μ m, and doping type is N-type, and doping content is 4 * 10
14cm
-3;
(4), device top layer 40, in device top layer 40, being positioned at raceway groove top is thin gate oxide 41, adopt the silicon dioxide that thickness is 20nm, what be positioned at 33 tops, drift region is thick expansion oxide layer 42, adopts the silicon dioxide of thick 50nm, gate oxide 41 is all covered by gate electrode 43, expansion oxide layer 42 is just covered by field plate 44 near a part for raceway groove, and field plate 44 length are 40 μ m, thereby forms ladder step gate electrode.
On the partial insulative layer of N-type silicon buried layer, on silicon LDMOS, be provided with electrode 45,46.
The present invention has silicon LDMOS(BNL PSOI-LDMOS on the partial insulative layer of N-type silicon buried layer), its performance is that the Sentaurus TCAD software simulation research based on three-dimensional obtains, and in analog simulation research, substrate and source are all ground connection.
Embodiment 1:
The silicon window length of BNL-PSOI is 50 μ m, and the silicon window length of CPSOI is 70 μ m, and N-type silicon buried layer doping content is 9.2 * 10
15cm
-3thickness is 0.5 μ m, transistorized other parameters of fixed L DMOS, the impact that the partial insulative layer silicon-on with N-type silicon buried layer distributes on device drain terminal longitudinal electric field.
As shown in Figure 2, there is BNL-PSOI structure and the BNL-SOI structure of N-type silicon buried layer, can in oxygen buried layer, introduce high electric field, thereby can improve device electric breakdown strength.In addition the electric field that, BNL-PSOI introduces is lower by approximately 2 * 10 than BNL-SOI
4v/cm or 2.6%, this be because: hole on interface in order to keep electrical continuity to redistribute.In BNL-SOI, hole can form accumulation distribution in the bottom of silicon fiml (being also silicon/oxygen buried layer interface), but in BNL-PSOI structure, these holes can be driven into substrate by silicon window, so the hole number at silicon/oxygen buried layer interface of drain terminal below BNL-SOI is more more.But because hole is minority carrier, comparing with alms giver's ionized impurity of n type buried layer is the difference on the order of magnitude, so BNL-PSOI is only a little bit smaller than BNL-SOI, and can't be mutually far short of what is expected.
Embodiment 2:
The silicon window length of BNL-PSOI is 50 μ m, and the silicon window length of CPSOI is 70 μ m, and N-type silicon buried layer doping content is 9.2 * 10
15cm
-3thickness is 0.5 μ m, transistorized other parameters of fixed L DMOS, the impact that the partial insulative layer silicon-on with N-type silicon buried layer distributes on device drain terminal longitudinal voliage.
As shown in Figure 3, because the substrate of PSOI structure can be shared a part of puncture voltage, and the substrate of soi structure is not almost born voltage.Although for BNL-PSOI and BNL-SOI, the voltage V that oxygen buried layer is born
ibe respectively 225V and 230V, but the substrate of BNL-PSOI is born voltage V
subv for 120V BNL-SOI
subbe almost equal to zero, so generally, BNL-PSOI can obtain much higher puncture voltage than BNL-SOI.In addition the V of CPSOI and CSOI,
ionly have respectively 156V and 168V, compare with them, the V of BNL-PSOI
iimproved respectively 44.2% and 33.9%.Therefore,, in the LDMOS of these four kinds of structures, BNL-PSOI has obtained the highest puncture voltage.
Embodiment 3:
The silicon window length of BNL-PSOI is 50 μ m, and the silicon window length of CPSOI is 70 μ m, and N-type silicon buried layer doping content is 9.2 * 10
15cm
-3thickness is 0.5 μ m, transistorized other parameters of fixed L DMOS, the impact of the partial insulative layer silicon-on with N-type silicon buried layer on device upper surface Electric Field Distribution.
As shown in Figure 4, difference due to silicon and dioxide dielectric constant, intersection (being 50 μ m and 70 μ m places in silicon window length respectively) at silicon window and oxygen buried layer, CPSOI and BNL-PSOI upper surface have respectively one " projection ", this " projection " plays the electric field strength that drags down source drain terminal, thereby improves device electric breakdown strength.This means that PSOI structure can further strengthen reducing surface field (REduced SURface Field, RESURF) effect than SOI.
Embodiment 4:
The silicon window length of BNL-PSOI is 50 μ m, and the silicon window length of CPSOI is 70 μ m, and N-type silicon buried layer doping content is 9.2 * 10
15cm
-3thickness is 0.5 μ m, transistorized other parameters of fixed L DMOS, the impact of the partial insulative layer silicon-on with N-type silicon buried layer on device lower surface Electric Field Distribution.
As shown in Figure 5, for two kinds of PSOI structure devices, when the lower surface from top silicon surface rises to upper surface gradually, the spike in Fig. 5 can become the projection in Fig. 4.And corresponding spike or projection wants high in these spikes of BNL-PSOI or convexity CPSOI, illustrate that in BNL-PSOI, to drag down the effect of source drain terminal electric field stronger, this RESURF effect that also means BNL-PSOI is better than CPSOI.So the RESURF effect of BNL-PSOI is best in four kinds of device architectures.
Embodiment 5:
N-type silicon buried layer doping content is 9.2 * 10
15cm
-3thickness is 0.5 μ m, and fixedly other parameters of BNL-PSOI LDMOS, change silicon length of window L
wdevice electric breakdown strength BV, oxygen buried layer are born to voltage V
iand substrate is born voltage V
subimpact (because total device length is constant, so corresponding variation can occur the length of oxygen buried layer length and silicon buried layer thereupon).
As shown in Figure 6, in BNL-PSOI device, the length of silicon window is distributed with great impact to the voltage in the puncture voltage BV of device and each region, can know and see, puncture voltage first increases afterwards and reduces, with L
w=50 μ m are breakover point.At L
wbefore=50 μ m, oxygen buried layer voltage V
islowly reduce and underlayer voltage V
subincrease fast, now along with the increase depletion layer of silicon window length, to thrust substrate layer darker, and puncture voltage increases; Yet at L
wafter=50 μ m, along with the increase of silicon window length, oxygen buried layer voltage V
ireduce start to accelerate (precipitous) and underlayer voltage V
subincrease but start slack-off (flattening), this shows that substrate charge carrier now starts to stop depletion layer further to substrate region, to extend, thus the puncture voltage of BNL-PSOI starts to decline.
Embodiment 6:
Silicon window length is 50 μ m, and fixing other parameters of BNL-PSOI LDMOS change the doping content N of N-type silicon buried layer
bNLand thickness t
bNLimpact on device electric breakdown strength.
As shown in Figure 7, work as N
bNLin the time of fixedly, along with t
bNLincrease, puncture voltage is all first to increase afterwards and reduce; And work as t
bNLin the time of fixedly, along with N
bNLincrease, puncture voltage is all first to increase afterwards and reduce.Thickness t along with n type buried layer
bNLincrease, " the opening bore " of puncture voltage curve can be more and more less, puncture voltage maximum almost remains unchanged simultaneously, is about 660 volts.So for this example, in order to obtain optimized device performance, the thickness t of n type buried layer
bNLshould be less than 2 μ m, can provide more marginal space for the manufacturing and the work behavior of device like this, to guarantee high efficiency and the reliability of device.
Embodiment 7:
Silicon window length is 50 μ m, the thickness t of N-type silicon buried layer
bNLbe 0.5 μ m, fixing other parameters of BNL-PSOI LDMOS, change the doping content N of N-type silicon buried layer
bNLthe impact that drain terminal longitudinal electric field under breakdown conditions is distributed.
As shown in Figure 8, when N-type silicon buried layer thickness t
bNLwhile immobilizing, along with doping content N
bNLincrease, the electric field of silicon/oxygen buried layer interface also can increase.So, along with doping content N
bNLincrease, the puncture voltage of device is to be also first increase trend, when being increased to a certain degree, can reaching prematurely unit constant due to ionization integration, thereby device breakdown is occurred too early, causes puncture voltage to reduce.Because if from top silicon surface toward its basal surface (silicon/oxygen buried layer interface), the electric field of silicon/oxygen buried layer near interface is to raise rapidly, can be referring to Fig. 8 illustration, but, when doping content surpasses certain value, make the electric field in N-type silicon buried layer have too high increase, thereby ionization integration will more easily reach unit constant, so just reduced the puncture voltage of device.Now, device breakdown occurs in silicon/oxygen buried layer interface of drain terminal below.
Embodiment 8:
Silicon window length is 50 μ m, the thickness N of N-type silicon buried layer
bNLbe 9.2 * 10
15cm
-3, fixing other parameters of BNL-PSOILDMOS, change the thickness t of N-type silicon buried layer
bNLthe impact that drain terminal longitudinal electric field under breakdown conditions is distributed.
As shown in Figure 9, thicker N-type silicon buried layer is larger to the change of longitudinal electric field, and can introduce higher longitudinal electric field at silicon buried layer.All ionized donor ions in this explanation n type buried layer all have contribution to the high electric field on silicon/oxygen buried layer interface.So and Fig. 8 puncture voltage-silicon buried layer doping content " relation object seemingly, along with silicon buried layer thickness t
bNLincrease, puncture voltage can first increase, still, when silicon buried layer thickness t
bNLwhile surpassing certain value, the electric field of silicon/oxygen buried layer interface is too high, cause device to puncture in advance, thereby puncture voltage reduces.Now, device breakdown occurs in silicon/oxygen buried layer interface of drain terminal below equally.
Embodiment 9:
Fixing other parameters of BNL-PSOI LDMOS, at the concentration N of different N type silicon buried layer
bNLand thickness t
bNLunder conditional combination, along with the increase of silicon length of window, the relation of puncture voltage (Breakdown Voltage, BV) and conducting resistance (On-resistance, Ron).
As shown in figure 10, example 9 is chosen according to Fig. 7 so that device can reach maximum breakdown voltage.Can see, along with the increase of silicon window length, conducting resistance (R
on, sp) can increase together with puncture voltage (BV).One of reason be the electronics that provides due to shorter N-type silicon buried layer (larger silicon window length) still less, thereby cause work leakage current less, also mean that electric conduction resistive is large; Another one reason is that the increase due to silicon window can cause depleted region to become causing electric current to reduce greatly, and this is similar to " conducting resistance-silicon window length " relation in traditional PS OI structure.Conducting resistance curve in figure is whole along with the increase of N-type silicon buried layer thickness to be moved toward lower right, means that the BNL-PSOI that silicon buried layer thickness is larger has better device performance, i.e. larger puncture voltage and less conducting resistance.Be not difficult in the drawings to find, silicon buried layer thickness is together with two mutual cross-couplings of curve of 0.5 μ m and 1.0 μ m, illustrate that two curves respectively have quality in different working regions, for example: puncture voltage is in the region of 600～650V, and thickness is that the curve of 1.0 μ m is better than the curve that thickness is 0.5 μ m; The region at two ends is that thickness is that the curve of 0.5 μ m wants better in the drawings.In view of having wide in range optimum device performance scope as design reference, the scope of silicon buried layer thickness is chosen from 0.5 μ m to 1.0 μ m.
Embodiment 10:
The N-type silicon buried layer doping content N of BNL-PSOI and BNL-SOI
bNLbe respectively 1.1 * 10
16cm
-3with 9.2 * 10
15cm
-3, silicon buried layer thickness t
bNLbe 0.5 μ m, other parameters of fixed L DMOS, the silicon window variable-length of two kinds of PSOI structures, the relatively puncture voltage of four kinds of device architectures and the relation of conducting resistance.
As shown in figure 11, the performance of very clearly seeing BNL-PSOI is best in all device architectures.Compare with CPSOI with CSOI, BNL-PSOI not only can reach much higher 660V puncture voltage, and its conducting resistance has also reduced 13.6%～15.5%.And compare with BNL-SOI, although the corresponding conducting resistance of 660V puncture voltage of BNL-PSOI is than large 7.8% of BNL-SOI, but the puncture voltage of its 660V approximately than the height of BNL-SOI 20.4%, so final BNL-PSOI can obtain better device quality factor (Figure-of-merit ,=BV
2/ R
on)
From example 1-10, silicon LDMOS(BNL-PSOI LDMOS on the partial insulative layer with N-type silicon buried layer proposed by the invention) can in oxygen buried layer, introduce higher electric field strength, thus improve the puncture voltage of device; The more electronics providing by N-type silicon buried layer, strengthens transistorized current driving ability, and can reduce the conducting resistance of device; Due to the material impact of silicon buried layer, need to consider to select the parameter of silicon buried layer to obtain better device performance comprehensively.
In sum; although the specific embodiment of the present invention have been described in detail the present invention; but persons skilled in the art should be understood that; above-described embodiment is only the description to the preferred embodiments of the present invention; but not limiting the scope of the invention; persons skilled in the art are in the disclosed technical scope of the present invention, and the variation that can expect easily, all within protection scope of the present invention.
Claims (10)
1. have a silicon ldmos transistor on the partial insulative layer of N-type silicon buried layer, it is characterized in that, described transistor arrangement contains from bottom to top successively:
One substrate layer;
Part oxide layer, wherein left-half is silicon window, right half part is oxygen buried layer;
One silicon film, silicon film top left side is the cingens source region of silicon body, right side is drain region, remainder is drift region, raceway groove is provided by the silicon body between source region and drift region, is covered on silicon dioxide in drift region, has one deck doping content to be greater than the N-type silicon buried layer of drift region;
One device top layer, in device top layer, being positioned at raceway groove top is gate oxide, top, drift region is expansion oxide layer, expands oxidated layer thickness and is greater than gate oxide, and gate oxide is all covered by gate electrode, expansion oxide layer is just covered by field plate near a part for raceway groove, forms ladder step gate electrode.
2. silicon ldmos transistor on the partial insulative layer with N-type silicon buried layer as claimed in claim 1, is characterized in that: the doping type of described substrate layer is P type, and doping content is 4 * 10
14cm
-3silicon materials.
3. silicon ldmos transistor on the partial insulative layer with N-type silicon buried layer as claimed in claim 1, is characterized in that: the doping type of described silicon window is consistent with substrate layer with concentration, and described oxygen buried layer adopts thickness to be less than or equal to the silicon dioxide of 4 μ m.
4. silicon ldmos transistor on the partial insulative layer with N-type silicon buried layer as claimed in claim 1, is characterized in that: described silicon film All Ranges is all silicon materials, and thickness is less than or equal to 20 μ m.
5. silicon ldmos transistor on the partial insulative layer with N-type silicon buried layer as claimed in claim 1, is characterized in that: described raceway groove is long is 1-5 μ m.
6. silicon ldmos transistor on the partial insulative layer with N-type silicon buried layer as claimed in claim 1, is characterized in that: the long 5 μ m in described source region and drain region, and doping type is N-type, doping content is 2 * 10
19cm
-3, described silicon body doping type is P type, doping content is 1 * 10
17cm
-3.
7. silicon ldmos transistor on the partial insulative layer with N-type silicon buried layer as claimed in claim 1, is characterized in that: described drift region length is 90 μ m, and doping type is N-type, and doping content is 4 * 10
14cm
-3.
8. silicon ldmos transistor on the partial insulative layer with N-type silicon buried layer as claimed in claim 1, is characterized in that: described gate oxide is that thickness is the silicon dioxide of 20nm, and expansion oxide layer adopts the silicon dioxide of thick 50nm, and field plate length is 40 μ m.
9. silicon ldmos transistor on the partial insulative layer with N-type silicon buried layer as claimed in claim 1, is characterized in that: in described transistor arrangement, substrate layer, silicon window, silicon film are silicon materials.
10. silicon ldmos transistor on the partial insulative layer with N-type silicon buried layer as claimed in claim 1, is characterized in that: described transistorized following arbitrary parameter is all adjustable,
(1), source region, drain region, raceway groove, drift region length is adjustable;
(2), dopant material, the doping content of source region, drain region, raceway groove, drift region, silicon buried layer, silicon window and substrate layer are adjustable;
(3), material, the thickness of gate oxide, expansion oxide layer and oxygen buried layer are adjustable;
(4), the gate electrode field plate length of top, drift region is adjustable;
(5), at total device long regularly, the length of its silicon window and oxygen buried layer is adjustable.
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| CN112713193A (en) * | 2020-12-30 | 2021-04-27 | 杭州电子科技大学温州研究院有限公司 | Trench LDMOS transistor with convex extended buried oxide region |
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