WO2014000340A1 - Trench-gate semiconductor power device - Google Patents

Trench-gate semiconductor power device Download PDF

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Publication number
WO2014000340A1
WO2014000340A1 PCT/CN2012/081098 CN2012081098W WO2014000340A1 WO 2014000340 A1 WO2014000340 A1 WO 2014000340A1 CN 2012081098 W CN2012081098 W CN 2012081098W WO 2014000340 A1 WO2014000340 A1 WO 2014000340A1
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WIPO (PCT)
Prior art keywords
semiconductor
region
trench gate
dielectric
semiconductor region
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PCT/CN2012/081098
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French (fr)
Chinese (zh)
Inventor
罗小蓉
蒋永恒
蔡金勇
范叶
王沛
王骁伟
周坤
王�琦
罗尹春
张波
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电子科技大学
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Publication of WO2014000340A1 publication Critical patent/WO2014000340A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Definitions

  • This invention relates to semiconductor technology, and more particularly to low power semiconductor power devices having dielectric trench and trench gate structures.
  • a power MOSFET (metal oxide semiconductor Field-Effect Transistor) device and ⁇ high voltage requires a longer drift region and a lower drift region doping concentration, which makes the specific on-resistance R.
  • n , sp with the device withstand voltage BV according to R.
  • the relationship between n and sp -BV 2 ⁇ 2 - 6 increases, resulting in an increase in power consumption.
  • VDMOS vertical double diffusion metal oxide semiconductor
  • J ET junction field-effect transistor
  • the super junction is introduced into the power VDMOS, and the on-resistance is reduced on the basis of increasing the withstand voltage; however, in order to obtain a high-performance super-junction VDMOS, the process is difficult to implement.
  • the higher the withstand voltage of the VDMOS device the deeper the vertical P-column and N-column regions required.
  • the conventional "super-junction" structure is formed by multiple injection, multiple epitaxy and annealing.
  • the higher the VDMOS withstand voltage The more the number of epitaxy and implantation in the deep P-column region and the N-column region is formed, the more difficult the process is, and the higher the cost; moreover, multiple injections, multiple epitaxy, and annealing are used to form longitudinal alternating P-type and N-type In the column region, it is difficult to form a P-type or N-type column region with a high concentration and a narrow strip width.
  • the electrical properties of the "superjunction" device are sensitive to charge non-equilibrium, and the process must accurately control the P column region and the N column region.
  • the device Width and concentration, otherwise the device is electrically The performance degradation occurs; again, the device's body diode is reverse-recovered and hardened, and the breakdown voltage is lowered during high-current applications and the on-resistance is increased due to the expansion of the lateral PN junction depletion layer.
  • Improve the device performance is the electrical power and to improve the breakdown voltage than the contradictory relationship between on-resistance (R 0 ", sp ⁇ BV 23 ⁇ 2 5.)
  • the idea is: a silicon layer and a pressure-resistant closely spaced grooves of the high K dielectric permittivity ⁇ ⁇ equivalent to greater than, f ⁇ material higher value of the high [mu] [epsilon] greater, the slope of the electric field seen qN D / s M with high-K material in accordance with the Poisson equation K
  • the value increases and decreases, that is, the power device with high K dielectric reaches the same electric field peak in the case of larger drift region doping, so that the above contradiction relationship is improved and the high-K medium is applied to the drift region electric field modulation.
  • the auxiliary depletion effect is obvious in the case of small spacing and large density of the medium groove, but there are some disadvantages: 1.
  • the small spacing of the medium grooves makes the silicon column between the dielectric grooves become thin and brittle.
  • the stresses between high-k materials and silicon and their different thermal expansion coefficients lead to defects, deformations and even breaks in the device, which can affect the performance and reliability of the device and increase the process difficulty.
  • Media slot relatively large spacing If the density is small high K dielectric can play a role, then the process can be very reduced extent do improve device performance and reliability.
  • FIG. 1 A cross-sectional view of a conventional N-channel trench gate superjunction VDMOS device is shown in FIG. 1, with a semiconductor substrate 1 as a horizontal plane on which is a semiconductor drift region including alternating first semiconductor regions 2 (p-type semiconductors) And the second semiconductor region 3 (n-type semiconductor region), the p-type semiconductor region 2 and the n-type semiconductor region 3 are columnar, also referred to as p-column region and n-column region, p-type semiconductor region 2 and n-type semiconductor region 3 forming a super junction structure, the trench gate structure 13 is disposed directly above the n-type semiconductor region 3, the width of the n-type semiconductor region 3 is greater than the width of the trench gate structure 13, and the trench gate structure 13 includes the gate dielectric 6 and the gate dielectric 6 The conductive material 11 extracts the gate electrode G from the surface of the conductive material 11.
  • the total amount of impurities (i.e., the product of the lateral width and the doping concentration) of the p-type semiconductor region 2 and the n-type semiconductor region 3 are preferably.
  • the total amount of impurities should be equal, that is, the charge balance, and should be fully depleted in the blocking condition.
  • Two active regions are respectively disposed above the p-type semiconductor region 2 and the n-type semiconductor region 3 and are respectively in contact with the gate dielectric 6, and both include a p-type body region 5 and a p+ semiconductor body contact disposed on the p-type body region 5
  • the region 7 and the n+ semiconductor source region 9, the n+ semiconductor source region 9 is in contact with the gate dielectric 6
  • the source electrode S is disposed on the p+ semiconductor body contact region 7 and a portion of the n + semiconductor source region 9, the source electrode S and the gate electrode
  • the object of the present invention is to overcome the shortcomings of current semiconductor devices that cannot function as high-k dielectrics in the case of relatively large pitches and small densities of dielectric trenches, and to provide a trench gate semiconductor power device.
  • the present invention solves the technical problem thereof.
  • the technical solution adopted is a trench gate semiconductor power device, which comprises a semiconductor substrate, a trench gate structure, an active region and a semiconductor drift region, and is characterized in that it further comprises two high-K dielectric regions, which are high.
  • a K dielectric region is disposed over the semiconductor substrate
  • the semiconductor drift region includes a first semiconductor region and two second semiconductor regions
  • the first semiconductor region is disposed over the semiconductor substrate
  • the second semiconductor regions are disposed over the semiconductor substrate
  • Two sides of the first semiconductor region are respectively in contact with one side of the two second semiconductor regions, and a side of the two second semiconductor regions not in contact with the first semiconductor region is respectively in contact with a high K dielectric region
  • the width of the second semiconductor region 3 is not greater than the first semiconductor region 2
  • the doping concentration of the second semiconductor region is higher than that of the first semiconductor region
  • the trench gate structure is disposed above the first semiconductor region
  • the active region is disposed at a high K Above the dielectric region, and in contact with the upper surface of the high-k dielectric region, and in contact with the trench gate structure.
  • the first semiconductor region and the second semiconductor region have the same conductivity type, and the width of the trench gate structure is smaller than the sum of the widths of the first semiconductor region and the second semiconductor region.
  • first semiconductor region and the second semiconductor region have different conductivity types, and the width of the trench gate structure is greater than or equal to the width of the first semiconductor region and smaller than the width of the first semiconductor region and the second semiconductor region. Sum.
  • the semiconductor withstand voltage layer is disposed above the semiconductor substrate, below the first semiconductor region, the second semiconductor region, and the high-k dielectric layer, and the conductivity type of the semiconductor withstand voltage layer is The second semiconductor area is the same.
  • the lower surface of the trench gate structure is equal to or lower than the lower surface of the active region.
  • the relative dielectric constant of the high-k dielectric region is greater than the relative dielectric constant of the semiconductor drift region, and the critical breakdown electric field of the high-k dielectric is greater than 30 ⁇ / ⁇ .
  • the high germanium dielectric region is perpendicular to the semiconductor substrate and has a rectangular or trapezoidal or triangular cross-sectional shape centered on the first semiconductor region.
  • the trench gate semiconductor power device is a germanium channel or a germanium channel MOS device or a MOS controlled semiconductor device.
  • the beneficial effects of the present invention are that, by the above-mentioned trench gate semiconductor power device, the high germanium dielectric region increases the concentration of the semiconductor drift region and forms a second semiconductor region of a narrow strip width and a high concentration to form a low resistance current channel, thereby reducing the specific on-resistance; ⁇ Dielectric region adaptive depletion of semiconductor drift region to alleviate charge imbalance Problem, increase withstand voltage and process tolerance; high K dielectric region can modulate two-dimensional electric field distribution in the device to improve withstand voltage; second semiconductor region in contact with high ⁇ dielectric region in semiconductor drift region is narrow and doped concentration is high, semiconductor The variation of the width of the drift region does not have much influence on device performance, so the device design and manufacturing have great flexibility; and since the second semiconductor region is in contact with the first semiconductor region, the entire semiconductor drift region is not like US Patent US7. , 230, 310B2 is fragile.
  • FIG. 1 is a cross-sectional view of a conventional N-channel trench gate superjunction VDMOS device
  • FIG. 2 is a cross-sectional view of a trench gate VDMOS device having a low-resistance current channel of an N-channel according to the embodiment
  • FIG. 3 is a cross-sectional view of a deep trench gate VDMOS device having a low-resistance current channel of an N-channel according to the embodiment
  • FIG. 4 is a trench gate of an N-channel having a low-resistance current channel and a semi-media trench structure of the present embodiment.
  • FIG. 5 is a cross-sectional view of a N-channel VDMOS device having a trench gate super junction
  • FIG. 6 is a cross-sectional view of a trench gate VDMOS device having a low-resistance current channel in a P-channel according to the embodiment
  • FIG. FIG. 8 is a cross-sectional view of a trench gate IGBT device having a low resistance current path in the channel
  • FIG. 8 is a breakdown voltage of a conventional trench gate superjunction VDMOS device of FIG. 1 and its n-type semiconductor region and a breakdown voltage of the semiconductor device of the embodiment of the present invention Schematic diagram of the relationship between the concentration of the second semiconductor region and the concentration of N n ;
  • FIG. 9 is a schematic diagram showing the comparison of the forward conduction characteristics of the high-k dielectric region at different K values in the conventional trench gate super-junction VDMOS device device and the semiconductor device of the embodiment of the present invention.
  • 1 is a semiconductor substrate
  • 2 is a first semiconductor region
  • 3 is a second semiconductor region
  • 4 is a high-k dielectric region
  • 5 is a body region
  • 6 is a gate dielectric
  • 7 is a body contact region
  • 8 is a metal
  • 10 is an insulating layer
  • 11 is a conductive material
  • 12 is a semiconductor withstand voltage layer
  • 13 is a trench gate structure
  • G is a gate electrode
  • S is a source electrode
  • D is a drain electrode
  • n+ refers to a doping concentration greater than The concentration of n-type doping
  • n- refer to the doping concentration is less than the concentration of n-type doping
  • p+ means that the doping concentration is greater than the concentration of p-type doping
  • the p-referring doping concentration is less than the concentration of p-type doping.
  • the trench gate semiconductor power device of the present invention comprises a semiconductor substrate 1, a trench gate structure 13, an active region, a semiconductor drift region and two high K dielectric regions 4, and the high K dielectric region 4 is disposed above the semiconductor substrate 1.
  • the semiconductor drift region includes a first semiconductor region 2 and two second semiconductor regions 3, the first semiconductor region 2 is disposed above the semiconductor substrate 1, and the two second semiconductor regions 3 are disposed on the semiconductor liner Above the bottom 1, the two sides of the first semiconductor region 2 are respectively in contact with one side of the two second semiconductor regions 3, and the two second semiconductor regions 3 are not in contact with the first semiconductor region 2, respectively.
  • the K dielectric region 4 is in contact with each other, the width of the second semiconductor region 3 is not greater than the first semiconductor region 2, and the doping concentration of the second semiconductor region 3 is higher than that of the first semiconductor region 2, and the trench gate structure 13 is disposed at Above the semiconductor region 2, the active region is disposed above the high K dielectric region 4 and is in contact with the upper surface of the high K dielectric region 4 and is in contact with the trench gate structure 13.
  • a trench gate VDMOS device with an N-channel low-resistance current path is taken as an example, and its cross-sectional view is as shown in Fig. 2.
  • the semiconductor substrate is n+ doped (i.e., an n-type medium having a doping concentration greater than the n-type doping concentration).
  • the trench gate semiconductor power device of this example comprises an n+ type doped semiconductor substrate 1, a trench gate structure 13, an active region, a semiconductor drift region and two high K dielectric regions 4, and the semiconductor drift region comprises a first semiconductor region 2 And two second semiconductor regions 3, the first semiconductor region 2 is disposed above the semiconductor substrate 1, two second semiconductor regions 3 are disposed above the semiconductor substrate 1, and the high K dielectric region 4 is disposed above the semiconductor substrate 1, Two sides of the first semiconductor region 2 are respectively in contact with one side of the two second semiconductor regions 3, and a side of the two second semiconductor regions 3 not in contact with the first semiconductor region 2 is respectively associated with a high-K dielectric region 4 In contact with each other, the width of the second semiconductor region 3 is not greater than the first semiconductor region 2, the doping concentration of the second semiconductor region 3 is higher than that of the first semiconductor region 2, and the trench gate structure 13 is disposed in the first semiconductor region 2.
  • the active region is disposed above the high K dielectric region 4 and is in contact with the upper surface of the high K dielectric region 4 and is in contact with the
  • the first semiconductor region 2 is n-type doped (ie, an n-type medium having a doping concentration lower than the n-type doping concentration), the second semiconductor region 3 is n-type doped, and the first semiconductor region 2 is withstand voltage
  • the second semiconductor region 3 is a low-resistance current channel
  • the active region includes a p-type body region 5 and a p+ semiconductor body contact region 7 and an n + semiconductor source region 9 disposed on the p-type body region 5, and an n + semiconductor source
  • the region 9 is in contact with the gate dielectric 6, the source electrode S is disposed on the p+ semiconductor body contact region 7 and a portion of the n + semiconductor source region 9, the source electrode S is the metal layer 8, and between the source electrode S and the gate electrode G
  • An insulating layer 10 is disposed, and a drain electrode D is disposed under the semiconductor substrate 1.
  • the trench gate structure 13 includes a gate dielectric 6 and a conductive material 11 surrounded by the gate dielectric 6.
  • the gate electrode G is extracted from the surface of the conductive material 11, and the gate electrode G is a metal.
  • the layer 8, the conductive material 11 may be formed of polysilicon, the gate dielectric 6 is a high K dielectric or silicon dioxide, and the high K dielectric constituting the gate dielectric 6 may be the same as or different from the high K dielectric in the high K dielectric region.
  • the first semiconductor region 2 of the present example has the same conductivity type as the second semiconductor region 3, the second semiconductor region 3 is smaller than or equal to the width of the first semiconductor region 2, and the width of the trench gate structure 13 is smaller than the first The sum of the widths of the semiconductor region 2 and the second semiconductor region 3, where the first semiconductor region 2, the second semiconductor region 3, and the high-k dielectric region 4 are columnar, respectively perpendicular to the semiconductor substrate 1, and at this time, the high-k dielectric region
  • the cross-sectional shape perpendicular to the semiconductor substrate and centered on the first semiconductor region is rectangular, and the first semiconductor region 2, the second semiconductor region 3, and the high-k dielectric region 4 may have other shapes, such as a high-k dielectric high-k dielectric.
  • the cross-sectional shape perpendicular to the semiconductor substrate and passing through the first semiconductor region is trapezoidal or triangular, and the relative dielectric constant of the high-k dielectric region is greater than the relative dielectric constant of the semiconductor drift region.
  • the critical strike of the high-k dielectric The electric field is greater than 30 ⁇ / ⁇ ;
  • the bottom of the trench gate structure 13 of this example is parallel to the bottom of the active layer, but the process cannot accurately control the bottom of the trench gate structure 13 parallel to the bottom of the active region.
  • the bottom of the trench gate structure 13 is to be It is lower than the bottom of the active layer.
  • the deep trench gate makes the accumulation layer on the surface of the trench gate reduce the on-resistance when the gate is turned on.
  • the deep trench gate also reduces the length of the drift region and causes the withstand voltage to decrease.
  • the trench gate structure 13 extends downward beyond the active region, so that the trench gate structure 13 has a lower depth than the lower surface of the active region, and a cross-sectional view thereof is shown in FIG.
  • the depth of the medium groove cannot be made deep due to the process limitation, so a semi-dielectric groove structure can be used to increase the withstand voltage, that is, the semiconductor drift region and the high k dielectric region.
  • a semiconductor withstand voltage layer 12 having the same conductivity type as the second semiconductor region 3, which can reduce the depth of the groove and the process difficulty of the tilt injection, and withstand the partial withstand voltage by means of the layer This is more suitable for the application field with higher withstand voltage (withstand voltage higher than 400V). Therefore, the trench gate VDMOS structure of the semi-channel structure with N-channel low-resistance current channel is proposed as shown in Fig. 4, which is The embodiment of Fig.
  • the doping type of the low doped semiconductor layer 12 is the same as the doping type of the second semiconductor region 3, but the doping concentration is lower than the doping concentration of the semiconductor region 3.
  • the structure of the semiconductor device of the present invention has been described above by taking a trench gate VDMOS device having an N-channel low resistance current path as an example, and the structure of the present invention is equally applicable to an N-channel super junction structure VDMOS device.
  • the device in FIG. 5 corresponds to the structure of the device in FIG. 2, except that the doping of the first semiconductor region 2 of the device of FIG. 2 is changed from n-type low doping to p-type, and is super-exposed with the second semiconductor region. Knot The first semiconductor region and the second semiconductor region have different conductivity types. When the conductivity types of the first semiconductor region and the second semiconductor region are different, the width of the trench gate structure is greater than or equal to the first semiconductor. The width of the region is smaller than the sum of the widths of the first semiconductor region and the second semiconductor region.
  • the structure of the semiconductor device of the present invention has been described above by taking a trench gate VDMOS device having an N-channel low resistance current path as an example, and the structure of the present invention is also applicable to a P-channel VDMOS device.
  • the device in FIG. 6 corresponds to the structure of the device in FIG. 2, but the trench gate VDMOS device having the low-resistance current channel of the N-channel of FIG. 2 is changed into the P-channel trench-gate VDMOS device having the low-resistance current channel. Therefore, the conductivity type of each semiconductor region changes accordingly.
  • the VDMOS device is only one embodiment of the semiconductor device of the present invention
  • the trench gate semiconductor power device of the present invention may be an N-channel or P-channel MOS device or a MOS-controlled semiconductor device
  • the MOS device is like the VDMOS device described above.
  • MOS controlled semiconductor devices include IGBTs and the like.
  • a cross-sectional view of a trench IGBT device having an N-channel low-resistance current path is shown in FIG. 7.
  • the device in FIG. 7 is different from the device in FIG. 2 mainly in that the n + semiconductor lining in FIG. 2 is replaced by a p+ semiconductor substrate 1.
  • Bottom 1, the semi-super junction structure shown in Figure 4 is also applicable to IGBTs.
  • the structure of the present invention described above significantly improves the on-characteristics of the device, e.g., by about 30% lower than the on-resistance of a conventional superjunction VDMOS device, and increases the withstand voltage of the device and reduces the sensitivity of the withstand voltage to charge imbalance.
  • the parameters of the body region of the semiconductor device of the present invention can be equal to the body region parameters of the conventional trench gate super-junction VDMOS, so the channel resistances of the two devices can be considered equal.
  • the drift region resistance R D is mainly related to the concentration, width, length, and current spreading effects of the drift region. Since the structure proposed by the present invention employs a high-k dielectric and the second semiconductor region 3 is relatively narrow, the optimized concentration of the second semiconductor region 3 is not only much larger than the optimized concentration of the n-column region of the conventional trench-gate super-junction VDMOS, but also The slot-gate super-junction VDMOS embodiment is also larger than the n-column concentration required for the charge balance of the present invention (ie, the product of the n-column concentration and the lateral width is greater than the product of the p-column concentration and the lateral width), so The on-resistance of the structure is small.
  • the structure proposed by the present invention significantly reduces the forward on-resistance and reduces the power consumption of the device. 2) breakdown voltage
  • the structure of the present invention has a modulation effect on the electric field in the body, which increases the withstand voltage of the device by about 10%, and the doping variation of the withstand voltage to the second semiconductor region is not due to the introduction of the high-k dielectric. Very sensitive, reducing the difficulty of the process.
  • the present invention has a higher withstand voltage and a nearly 30% lower on-resistance than the conventional VDMOS structure. Further, the structure of the present invention has the characteristics of simple manufacturing process, large process tolerance, and good dynamic characteristics.
  • the structural model proposed by the patent of the present invention is established according to FIG. 2, and based on the model, the performance of the device is simulated by using the med 1C1 simulation software.
  • FIG. 8 is a schematic diagram showing the relationship between the breakdown voltage of a conventional trench gate super-junction VDMOS device and its n-type semiconductor region, and the breakdown voltage of the semiconductor device of the embodiment of the present invention and its second semiconductor region concentration N n .
  • the abscissa N n represents the doping concentration of the second semiconductor region 3
  • the ordinate represents the breakdown voltage.
  • the breakdown voltage of the conventional trench gate super-junction VDMOS (see FIG. 1) and the n-column region concentration are shown in the graph on the left side of FIG. 8, the breakdown voltage of the VDMOS device of the present invention and the concentration of the second semiconductor region 3. The relationship is shown in the curve on the right side of Figure 6.
  • Figure 8 shows that the optimized concentration of the n+ region of the semiconductor device of the present invention is larger than that of the conventional trench gate.
  • the VDMOS structure is one order of magnitude higher, and thus the on-resistance and conduction loss are reduced. Moreover, the sensitivity of the breakdown voltage to the n + region concentration N n change (charge non-equilibrium) is lowered, and thus the process tolerance is larger; The highest breakdown voltage of the semiconductor device of the present invention is about 20 V higher than that of the conventional super junction VDMOS.
  • the conventional trench gate super-junction VDMOS device has the maximum breakdown voltage during charge balance.
  • the withstand voltage of the device structure proposed by the present invention is affected by the concentration of the second semiconductor region 3, the higher the concentration of the second semiconductor region 3, the lower the withstand voltage, and the second semiconductor region 3 at the same withstand voltage
  • the doping concentration is much higher than the doping concentration of conventional superjunction VDMOS.
  • the breakdown voltage of the structure proposed by the present invention is insensitive to the concentration variation of the second semiconductor region as compared with the conventional trench gate superjunction VDMOS device.
  • FIG. 9 A comparison diagram of the forward conduction characteristics of the high-k dielectric region of the conventional trench gate super-junction VDMOS device device and the semiconductor device of the embodiment of the present invention is shown in FIG. 9 , wherein V drain represents The voltage of the drain, I fi , represents the current of the drain. Under a given drain current, the structure proposed by the present invention has a very low forward voltage drop, and the larger the value of ⁇ , the lower the on-resistance. This is mainly due to the effect of high K media.
  • the gate charge waveform of the structure proposed by the present invention is given under the conditions of given gate voltage, leakage current and drain voltage.
  • the conventional trench gate superjunction VDMOS is almost the same and does not change much with the K value.
  • the present invention differs from U.S. Patent No. 7,230,310B2 in that: 1) the semiconductor regions in the withstand voltage layer are different: the semiconductor drift region of the present invention has two semiconductor regions, a first semiconductor region 2 and a second semiconductor region 3, said high The K dielectric region is adjacent to the second semiconductor region 3; and the U.S. patent structure has only one semiconductor region (described in claim 1); 2) the semiconductor region functions differently: the second semiconductor region 3 of the present invention is A low-resistance channel whose concentration is more than an order of magnitude higher than that of the first semiconductor region 2, and its main function is a low-resistance current channel when the power device is conducting in the forward direction to reduce the specific on-resistance.
  • the first semiconductor region 2 of the present invention functions to modulate an electric field having a lower doping and thus a smaller electric field slope, which together with the high K dielectric region modulate the electric field distribution of the drift region, and the semiconductor region in the U.S. patent structure is off.
  • the high K dielectric region acts differently: the high K dielectric region 4 of the present invention mainly modulates the electric field distribution and the auxiliary depletion of the second semiconductor region 3.
  • the semiconductor device of the present invention Compared with the conventional trench gate super-junction VDMOS structure, the semiconductor device of the present invention has a drop in on-resistance of about 30% and a slight increase in withstand voltage. Meanwhile, the semiconductor device of the present invention has superior performance with large process tolerance, and overcomes Superjunction devices are the most common and difficult problem to solve, increasing the freedom of device design and manufacturing. At the same time, the first semiconductor region and the second semiconductor region of the present invention can be made narrow, so that the on-resistance and the device area are small.
  • the vertical MOSFET device of the present invention is most suitable for low power power devices, especially for low power power electronics with a withstand voltage of 100-300V.

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Abstract

A trench-gate semiconductor power device, which adds two high-K dielectric regions (4) at the left side and the right side of a semiconductor drift region, wherein the two sides of a first semiconductor region (2) in the semiconductor drift region are in contact with two second semiconductor regions (3), and the two high-K dielectric regions (4) are respectively in contact with the other sides of the two second semiconductor regions (3), thereby solving the problem that the existing semiconductor device cannot exert the high-K dielectric function in the case of relatively wide spacing and small density of dielectric trenches, and enabling the reduction of the specific on-resistance, the increase of the voltage resistance, and the application to an MOS device or an MOS controlled semiconductor device.

Description

槽栅半导体功率器件 所属技术领域  Trench gate semiconductor power device
本发明涉及半导体技术， 特别涉及具有介质槽和槽栅结构的低功耗半导 体功率器件。  This invention relates to semiconductor technology, and more particularly to low power semiconductor power devices having dielectric trench and trench gate structures.
背景技术 Background technique
功率 MOSFET ( metal oxide semiconductor Field-Effect Transistor)器件而 ί 高压需要漂移区较长且漂移区掺杂浓度低， 这使得比导通电阻 R。n, sp随器件 耐压 BV按 R。n, sp-BV2 ^2-6的关系增加， 导致功耗增大。 A power MOSFET (metal oxide semiconductor Field-Effect Transistor) device and ί high voltage requires a longer drift region and a lower drift region doping concentration, which makes the specific on-resistance R. n , sp with the device withstand voltage BV according to R. The relationship between n and sp -BV 2 ^ 2 - 6 increases, resulting in an increase in power consumption.
平面栅 VDMOS ( vertical double diffusion metal oxide semiconductor, 垂 直双扩散金属 -氧化物-半导体场效应晶体管） 的比导通电阻下降受 J ET (junction field-effect transistor ) 效应的限制已经达到极限。 由于 UMOS (U-type trench MOS, U型沟槽 MOS) 结构无 JFET效应且沟道密度高， 其 比导通电阻可以做的很小。 然而， 在高压大电流应用时， 由于漂移区的电阻 占器件总电阻的绝大部分，即使采用 UMOS结构仍然不能解决硅极限的问题。  The specific on-resistance drop of a vertical double diffusion metal oxide semiconductor (VDMOS) has been limited by the J ET (junction field-effect transistor) effect. Since the UMOS (U-type trench MOS) structure has no JFET effect and a high channel density, its specific on-resistance can be made small. However, in high-voltage and high-current applications, since the resistance of the drift region accounts for the majority of the total resistance of the device, even the UMOS structure cannot solve the silicon limit problem.
1993年电子科技大学的陈星弼教授提出， 在纵向功率器件 （尤其是纵向 MOSFET) 中采用交替的 P柱区和 N柱区结构作为漂移层的思想， 并称其为 "复合缓冲层" （composite buffer layer) 。 耐压层中 P柱区和 N柱区之间也相 互耗尽， 使得在较高的漏极电压下， 整个耐压层便完全耗尽， 类似于一个本 征耐压层， 从而使器件的耐压得以提高。 同时， 超结中的 N柱区可以采用较 高的浓度， 这样有利于降低导通电阻。  In 1993, Professor Chen Xingyu from the University of Electronic Science and Technology proposed the idea of using alternating P-column and N-column structures as drift layers in longitudinal power devices (especially vertical MOSFETs), and called them "composite buffers" (composite buffer). Layer). The P column region and the N column region in the withstand voltage layer are also depleted between each other, so that at a higher drain voltage, the entire withstand voltage layer is completely depleted, similar to an intrinsic withstand voltage layer, thereby making the device The withstand voltage is improved. At the same time, the N-column in the super junction can be used at a higher concentration, which helps to reduce the on-resistance.
1997年 Tatsuhiko等人在对上述概念的总结下提出了 "超结理论"。此后 "超 结" （superjunction, SJ) 这一概念被众多器件研究者所引用， 并且得到进一 歩的验证。  In 1997, Tatsuhiko et al. proposed the "super-junction theory" under the conclusion of the above concepts. Since then, the concept of "superjunction" (SJ) has been cited by many device researchers and has been further verified.
将超结引入功率 VDMOS, 在提高耐压的基础上降低导通电阻； 但为了 获得高性能的超结 VDMOS, 其工艺实现的难度较大。 首先， VDMOS 器件 耐压越高，所需纵向 P柱区和 N柱区越深，常规"超结"结构是采用多次注入、 多次外延以及退火形成， 因而， 超结 VDMOS耐压越高， 形成深 P柱区和 N 柱区外延和注入的次数就越多， 工艺难度就越大， 成本高； 而且， 采用多次 注入、 多次外延以及退火形成纵向的交替的 P型和 N型柱区， 难以形成高浓 度且窄条宽的 P型或 N型柱区； 其次， "超结 "器件的电学性能对电荷非平衡 很敏感， 工艺上须精确控制 P柱区和 N柱区的宽度和浓度， 否则导致器件电 学性能退化； 再次， 器件的体二级管反向恢复***等， 而且在大电流应用时 候击穿电压下降以及由于横向 PN结耗尽层扩大造成的导通电阻上升等问题。 The super junction is introduced into the power VDMOS, and the on-resistance is reduced on the basis of increasing the withstand voltage; however, in order to obtain a high-performance super-junction VDMOS, the process is difficult to implement. First, the higher the withstand voltage of the VDMOS device, the deeper the vertical P-column and N-column regions required. The conventional "super-junction" structure is formed by multiple injection, multiple epitaxy and annealing. Therefore, the higher the VDMOS withstand voltage The more the number of epitaxy and implantation in the deep P-column region and the N-column region is formed, the more difficult the process is, and the higher the cost; moreover, multiple injections, multiple epitaxy, and annealing are used to form longitudinal alternating P-type and N-type In the column region, it is difficult to form a P-type or N-type column region with a high concentration and a narrow strip width. Secondly, the electrical properties of the "superjunction" device are sensitive to charge non-equilibrium, and the process must accurately control the P column region and the N column region. Width and concentration, otherwise the device is electrically The performance degradation occurs; again, the device's body diode is reverse-recovered and hardened, and the breakdown voltage is lowered during high-current applications and the on-resistance is increased due to the expansion of the lateral PN junction depletion layer.
陈星弼院士在他的美国专利 US7 , 230 , 310B2 (发明名称： superjunction voltage sustaining layer with alternating semiconductor and high-K dielectric regions ) 中提出， 利用高 K ( Κ为相对介电系数） 介质来提高器件的电学性 能的思想。 这种结构能够避免常规的超结 Ρ柱和 Ν柱相互扩散的问题， 而且 在大电流时提高了器件的安全工作区， 降低了器件的导通电阻。 提高器件的 电学性能是指功率器件耐压与比导通电阻之间的矛盾关系 (R0„,sp^BV23~2.5 ) 的改善， 其思想是： 在耐压层中的硅与高 K介质槽紧密相间则其等效的介电 常数 εΜ将大于 ， 高 Κ材料的 f值越高 εΜ越大， 根据泊松方程可知电场斜 率 qND/sM随高 K材料的 K值增大而减小， 也就是具有高 K介质的功率器件 在更大的漂移区掺杂情况下才会到达相同的电场峰值， 这样上述矛盾关系得 到改善且高 K介质的对漂移区电场调制及辅助耗尽作用在介质槽小间距、 大 密度情况下效果明显。但是也因此有一些不足： 1、 介质槽小间距会使得介质 槽之间的硅柱变得很薄而易碎。 2、 高 K材料与硅之间的应力以及它们不同 的热膨胀系数引的起器件的缺陷、 形变甚至断裂也会随之变得严重， 影响器 件的性能和可靠性， 同时也增加了工艺难度。 所以在介质槽相对大间距、 小 密度情况下如果能发挥高 K介质的作用， 那么就能很程度上降低工艺难道提 高器件性能和可靠性。 In his U.S. Patent No. 7,230,310B2 (inductive name: superjunction voltage sustaining layer with alternating semiconductor and high-K dielectric regions), Chen Xingzhen proposed to use high K (Κ is a relative dielectric constant) medium to improve the electrical properties of the device. Performance thinking. This structure can avoid the problem of mutual diffusion of the conventional super-junction column and the column, and at the high current, the safe working area of the device is improved, and the on-resistance of the device is lowered. Improve the device performance is the electrical power and to improve the breakdown voltage than the contradictory relationship between on-resistance (R 0 ", sp ^ BV 23 ~ 2 5.) , The idea is: a silicon layer and a pressure-resistant closely spaced grooves of the high K dielectric permittivity ε Μ equivalent to greater than, f Κ material higher value of the high [mu] [epsilon] greater, the slope of the electric field seen qN D / s M with high-K material in accordance with the Poisson equation K The value increases and decreases, that is, the power device with high K dielectric reaches the same electric field peak in the case of larger drift region doping, so that the above contradiction relationship is improved and the high-K medium is applied to the drift region electric field modulation. And the auxiliary depletion effect is obvious in the case of small spacing and large density of the medium groove, but there are some disadvantages: 1. The small spacing of the medium grooves makes the silicon column between the dielectric grooves become thin and brittle. The stresses between high-k materials and silicon and their different thermal expansion coefficients lead to defects, deformations and even breaks in the device, which can affect the performance and reliability of the device and increase the process difficulty. Media slot relatively large spacing If the density is small high K dielectric can play a role, then the process can be very reduced extent do improve device performance and reliability.
常规的 N沟道的槽栅超结 VDMOS器件剖视图如图 1所示， 以半导体衬 底 1为水平面， 其上为半导体漂移区， 该半导体漂移区包括交替的第一半导 体区 2 (p型半导体区） 和第二半导体区 3 (n型半导体区）， p型半导体区 2 和 n型半导体区 3呈柱状， 也称作 p柱区和 n柱区， p型半导体区 2和 n型 半导体区 3形成超结结构， 槽栅结构 13设置在 n型半导体区 3正上方， n型 半导体区 3的宽度大于槽栅结构 13的宽度， 槽栅结构 13包括栅介质 6以及 栅介质 6所包围的导电材料 11，从导电材料 11表面引出栅电极 G，一般来说， 较好的情况下， p型半导体区 2的杂质总量 （即横向宽度和掺杂浓度的乘积） 与 n型半导体区 3杂质总量应该相等， 即电荷平衡， 且在阻断状况应全耗尽。 两个有源区分别设置在 p型半导体区 2和 n型半导体区 3上方并分别与栅介 质 6相接触， 都包括 p型体区 5以及设置在 p型体区 5上面的 p+半导体体接 触区 7和 n+半导体源区 9， n+半导体源区 9与栅介质 6相接触， 源极电极 S 设置在 p+半导体体接触区 7和部分 n +半导体源区 9上， 源极电极 S与栅电极 G之间具有绝缘层 10， 漏极电极 D设置在半导体衬底 1下方。 A cross-sectional view of a conventional N-channel trench gate superjunction VDMOS device is shown in FIG. 1, with a semiconductor substrate 1 as a horizontal plane on which is a semiconductor drift region including alternating first semiconductor regions 2 (p-type semiconductors) And the second semiconductor region 3 (n-type semiconductor region), the p-type semiconductor region 2 and the n-type semiconductor region 3 are columnar, also referred to as p-column region and n-column region, p-type semiconductor region 2 and n-type semiconductor region 3 forming a super junction structure, the trench gate structure 13 is disposed directly above the n-type semiconductor region 3, the width of the n-type semiconductor region 3 is greater than the width of the trench gate structure 13, and the trench gate structure 13 includes the gate dielectric 6 and the gate dielectric 6 The conductive material 11 extracts the gate electrode G from the surface of the conductive material 11. Generally, the total amount of impurities (i.e., the product of the lateral width and the doping concentration) of the p-type semiconductor region 2 and the n-type semiconductor region 3 are preferably. The total amount of impurities should be equal, that is, the charge balance, and should be fully depleted in the blocking condition. Two active regions are respectively disposed above the p-type semiconductor region 2 and the n-type semiconductor region 3 and are respectively in contact with the gate dielectric 6, and both include a p-type body region 5 and a p+ semiconductor body contact disposed on the p-type body region 5 The region 7 and the n+ semiconductor source region 9, the n+ semiconductor source region 9 is in contact with the gate dielectric 6, the source electrode S is disposed on the p+ semiconductor body contact region 7 and a portion of the n + semiconductor source region 9, the source electrode S and the gate electrode There is an insulating layer 10 between G, and a drain electrode D is disposed under the semiconductor substrate 1.
发明内容 Summary of the invention
本发明的目的是克服目前半导体器件在介质槽相对大间距、 小密度情况 下无法发挥高 K介质作用的缺点， 提供一种槽栅半导体功率器件。  SUMMARY OF THE INVENTION The object of the present invention is to overcome the shortcomings of current semiconductor devices that cannot function as high-k dielectrics in the case of relatively large pitches and small densities of dielectric trenches, and to provide a trench gate semiconductor power device.
本发明解决其技术问题， 采用的技术方案是， 槽栅半导体功率器件， 包 括半导体衬底、 槽栅结构、 有源区及半导体漂移区， 其特征在于， 还包括两 个高 K介质区， 高 K介质区设置在半导体衬底上方， 半导体漂移区包括第一 半导体区和两个第二半导体区， 第一半导体区设置在半导体衬底上方， 两个 第二半导体区设置在半导体衬底上方， 第一半导体区的两侧分别与两个第二 半导体区的一侧相接触， 两个第二半导体区未与第一半导体区相接触的一侧 分别与一个高 K介质区相接触， 所述第二半导体区 3的宽度不大于第一半导 体区 2， 第二半导体区的掺杂浓度高于第一半导体区， 所述槽栅结构设置在 第一半导体区上方， 有源区设置在高 K介质区上方， 并与高 K介质区的上表 面相接触， 且与槽栅结构相接触。  The present invention solves the technical problem thereof. The technical solution adopted is a trench gate semiconductor power device, which comprises a semiconductor substrate, a trench gate structure, an active region and a semiconductor drift region, and is characterized in that it further comprises two high-K dielectric regions, which are high. a K dielectric region is disposed over the semiconductor substrate, the semiconductor drift region includes a first semiconductor region and two second semiconductor regions, the first semiconductor region is disposed over the semiconductor substrate, and the second semiconductor regions are disposed over the semiconductor substrate Two sides of the first semiconductor region are respectively in contact with one side of the two second semiconductor regions, and a side of the two second semiconductor regions not in contact with the first semiconductor region is respectively in contact with a high K dielectric region, The width of the second semiconductor region 3 is not greater than the first semiconductor region 2, the doping concentration of the second semiconductor region is higher than that of the first semiconductor region, the trench gate structure is disposed above the first semiconductor region, and the active region is disposed at a high K Above the dielectric region, and in contact with the upper surface of the high-k dielectric region, and in contact with the trench gate structure.
具体的， 所述第一半导体区与第二半导体区的导电类型相同， 所述槽栅 结构的宽度小于第一半导体区和第二半导体区的宽度之和。  Specifically, the first semiconductor region and the second semiconductor region have the same conductivity type, and the width of the trench gate structure is smaller than the sum of the widths of the first semiconductor region and the second semiconductor region.
进一歩的， 所述第一半导体区与第二半导体区的导电类型不同， 所述槽 栅结构的宽度大于或等于第一半导体区的宽度， 且小于第一半导体区和第二 半导体区的宽度之和。  Further, the first semiconductor region and the second semiconductor region have different conductivity types, and the width of the trench gate structure is greater than or equal to the width of the first semiconductor region and smaller than the width of the first semiconductor region and the second semiconductor region. Sum.
具体的， 还包括半导体耐压层， 所述半导体耐压层设置在半导体衬底上 方， 第一半导体区、 第二半导体区及高 K介质层下方， 所述半导体耐压层的 导电类型与第二半导体区相同。  Specifically, the semiconductor withstand voltage layer is disposed above the semiconductor substrate, below the first semiconductor region, the second semiconductor region, and the high-k dielectric layer, and the conductivity type of the semiconductor withstand voltage layer is The second semiconductor area is the same.
再进一歩的， 所述槽栅结构的下表面等于或低于有源区的下表面。  Further, the lower surface of the trench gate structure is equal to or lower than the lower surface of the active region.
具体的， 所述高 K介质区的相对介电常数大于半导体漂移区的相对介电 常数， 所述高 K介质的临界击穿电场大于 30ν/μπι。  Specifically, the relative dielectric constant of the high-k dielectric region is greater than the relative dielectric constant of the semiconductor drift region, and the critical breakdown electric field of the high-k dielectric is greater than 30 ν/μπι.
再进一歩的， 所述高 Κ介质区垂直于半导体衬底且经过第一半导体区为 中心的剖面形状为矩形或梯形或三角形。  Further, the high germanium dielectric region is perpendicular to the semiconductor substrate and has a rectangular or trapezoidal or triangular cross-sectional shape centered on the first semiconductor region.
具体的，所述槽栅半导体功率器件为 Ν沟道或 Ρ沟道的 MOS器件或 MOS 控制的半导体器件。  Specifically, the trench gate semiconductor power device is a germanium channel or a germanium channel MOS device or a MOS controlled semiconductor device.
本发明的有益效果是， 通过上述槽栅半导体功率器件， 高 Κ介质区提高 半导体漂移区浓度且形成窄条宽的高浓度的第二半导体区形成低阻电流通 道， 降低比导通电阻； 高 Κ介质区自适应耗尽半导体漂移区缓解电荷非平衡 问题， 增加耐压和工艺容差； 高 K介质区可以调制器件内二维电场分布而提 高耐压;半导体漂移区中与高 κ介质区接触的第二半导体区窄且掺杂浓度高， 半导体漂移区宽度的变化对器件性能没有太大的影响， 所以器件设计和制造 具有很大的灵活性； 且由于第二半导体区与第一半导体区相接触， 整个半导 体漂移区也不像美国专利 US7 , 230, 310B2中易碎。 The beneficial effects of the present invention are that, by the above-mentioned trench gate semiconductor power device, the high germanium dielectric region increases the concentration of the semiconductor drift region and forms a second semiconductor region of a narrow strip width and a high concentration to form a low resistance current channel, thereby reducing the specific on-resistance;自适应Dielectric region adaptive depletion of semiconductor drift region to alleviate charge imbalance Problem, increase withstand voltage and process tolerance; high K dielectric region can modulate two-dimensional electric field distribution in the device to improve withstand voltage; second semiconductor region in contact with high κ dielectric region in semiconductor drift region is narrow and doped concentration is high, semiconductor The variation of the width of the drift region does not have much influence on device performance, so the device design and manufacturing have great flexibility; and since the second semiconductor region is in contact with the first semiconductor region, the entire semiconductor drift region is not like US Patent US7. , 230, 310B2 is fragile.
附图说明 DRAWINGS
图 1为常规的 N沟道的槽栅超结 VDMOS器件剖视图；  1 is a cross-sectional view of a conventional N-channel trench gate superjunction VDMOS device;
图 2为本实施例的 N沟道具有低阻电流通道的槽栅 VDMOS器件剖视图； 图 3为本实施例的 N沟道具有低阻电流通道的深槽栅 VDMOS器件剖视 图；  2 is a cross-sectional view of a trench gate VDMOS device having a low-resistance current channel of an N-channel according to the embodiment; FIG. 3 is a cross-sectional view of a deep trench gate VDMOS device having a low-resistance current channel of an N-channel according to the embodiment;
图 4为本实施例的 N沟道具有低阻电流通道的和 semi介质槽结构的槽栅 4 is a trench gate of an N-channel having a low-resistance current channel and a semi-media trench structure of the present embodiment.
VDMOS器件剖视图； VDMOS device cross-sectional view;
图 5为本实施例的 N沟道具有槽栅超结的 VDMOS器件剖视图； 图 6为本实施例的 P沟道具有低阻电流通道的槽栅 VDMOS器件剖视图； 图 7为本实施例的 N沟道具有低阻电流通道的槽栅 IGBT器件剖视图； 图 8为图 1中常规槽栅超结 VDMOS器件的击穿电压与其 n型半导体区 的关系及本发明实施例的半导体器件的击穿电压与其第二半导体区浓度 Nn 的关系示意图； 5 is a cross-sectional view of a N-channel VDMOS device having a trench gate super junction; FIG. 6 is a cross-sectional view of a trench gate VDMOS device having a low-resistance current channel in a P-channel according to the embodiment; FIG. FIG. 8 is a cross-sectional view of a trench gate IGBT device having a low resistance current path in the channel; FIG. 8 is a breakdown voltage of a conventional trench gate superjunction VDMOS device of FIG. 1 and its n-type semiconductor region and a breakdown voltage of the semiconductor device of the embodiment of the present invention Schematic diagram of the relationship between the concentration of the second semiconductor region and the concentration of N n ;
图 9为常规槽栅超结 VDMOS器件器件和本发明实施例的半导体器件中 高 K介质区在不同的 K值时正向导通特性的比较示意图 ·'  FIG. 9 is a schematic diagram showing the comparison of the forward conduction characteristics of the high-k dielectric region at different K values in the conventional trench gate super-junction VDMOS device device and the semiconductor device of the embodiment of the present invention.
其中， 1为半导体衬底， 2为第一半导体区， 3为第二半导体区， 4为高 K介质区， 5为体区， 6为栅介质， 7为体接触区， 8为金属， 9为源区， 10 为绝缘层， 11为导电材料， 12为半导体耐压层， 13为槽栅结构， G为栅电极， S为源极电极， D为漏极电极， n+指掺杂浓度大于 n型掺杂的浓度， n—指掺杂 浓度小于 n型掺杂的浓度， p+指掺杂浓度大于 p型掺杂的浓度， p—指掺杂浓度 小于 p型掺杂的浓度。  Wherein, 1 is a semiconductor substrate, 2 is a first semiconductor region, 3 is a second semiconductor region, 4 is a high-k dielectric region, 5 is a body region, 6 is a gate dielectric, 7 is a body contact region, and 8 is a metal, 9 For the source region, 10 is an insulating layer, 11 is a conductive material, 12 is a semiconductor withstand voltage layer, 13 is a trench gate structure, G is a gate electrode, S is a source electrode, D is a drain electrode, and n+ refers to a doping concentration greater than The concentration of n-type doping, n-refers to the doping concentration is less than the concentration of n-type doping, p+ means that the doping concentration is greater than the concentration of p-type doping, and the p-referring doping concentration is less than the concentration of p-type doping.
具体实施方式 detailed description
下面结合附图及实施例， 详细描述本发明的技术方案。  The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.
本发明所述的槽栅半导体功率器件， 包括半导体衬底 1、 槽栅结构 13、 有源区、 半导体漂移区及两个高 K介质区 4， 高 K介质区 4设置在半导体衬 底 1上方， 半导体漂移区包括第一半导体区 2和两个第二半导体区 3， 第一 半导体区 2设置在半导体衬底 1上方， 两个第二半导体区 3设置在半导体衬 底 1上方，第一半导体区 2的两侧分别与两个第二半导体区 3的一侧相接触， 两个第二半导体区 3未与第一半导体区 2相接触的一侧分别与一个高 K介质 区 4相接触， 所述第二半导体区 3的宽度不大于第一半导体区 2， 第二半导 体区 3的掺杂浓度高于第一半导体区 2， 所述槽栅结构 13设置在第一半导体 区 2上方， 有源区设置在高 K介质区 4上方， 并与高 K介质区 4的上表面相 接触， 且与槽栅结构 13相接触。 The trench gate semiconductor power device of the present invention comprises a semiconductor substrate 1, a trench gate structure 13, an active region, a semiconductor drift region and two high K dielectric regions 4, and the high K dielectric region 4 is disposed above the semiconductor substrate 1. The semiconductor drift region includes a first semiconductor region 2 and two second semiconductor regions 3, the first semiconductor region 2 is disposed above the semiconductor substrate 1, and the two second semiconductor regions 3 are disposed on the semiconductor liner Above the bottom 1, the two sides of the first semiconductor region 2 are respectively in contact with one side of the two second semiconductor regions 3, and the two second semiconductor regions 3 are not in contact with the first semiconductor region 2, respectively. The K dielectric region 4 is in contact with each other, the width of the second semiconductor region 3 is not greater than the first semiconductor region 2, and the doping concentration of the second semiconductor region 3 is higher than that of the first semiconductor region 2, and the trench gate structure 13 is disposed at Above the semiconductor region 2, the active region is disposed above the high K dielectric region 4 and is in contact with the upper surface of the high K dielectric region 4 and is in contact with the trench gate structure 13.
实施例  Example
本例以 N沟道具有低阻电流通道的槽栅 VDMOS器件为例， 其剖视图如 图 2。 在 N沟道 VDMOS器件的情况下半导体衬底为 n+型掺杂 （即掺杂浓度 大于 n型掺杂浓度的 n型介质）。  In this example, a trench gate VDMOS device with an N-channel low-resistance current path is taken as an example, and its cross-sectional view is as shown in Fig. 2. In the case of an N-channel VDMOS device, the semiconductor substrate is n+ doped (i.e., an n-type medium having a doping concentration greater than the n-type doping concentration).
本例的槽栅半导体功率器件， 包括 n+型掺杂的半导体衬底 1、 槽栅结构 13、 有源区、 半导体漂移区及两个高 K介质区 4， 半导体漂移区包括第一半 导体区 2和两个第二半导体区 3， 第一半导体区 2设置在半导体衬底 1上方， 两个第二半导体区 3设置在半导体衬底 1上方， 高 K介质区 4设置在半导体 衬底 1上方， 第一半导体区 2的两侧分别与两个第二半导体区 3的一侧相接 触， 两个第二半导体区 3未与第一半导体区 2相接触的一侧分别与一个高 K 介质区 4相接触， 所述第二半导体区 3的宽度不大于第一半导体区 2， 第二 半导体区 3的掺杂浓度高于第一半导体区 2， 所述槽栅结构 13设置在第一半 导体区 2上方， 有源区设置在高 K介质区 4上方， 并与高 K介质区 4的上表 面相接触， 且与槽栅结构 13相接触。  The trench gate semiconductor power device of this example comprises an n+ type doped semiconductor substrate 1, a trench gate structure 13, an active region, a semiconductor drift region and two high K dielectric regions 4, and the semiconductor drift region comprises a first semiconductor region 2 And two second semiconductor regions 3, the first semiconductor region 2 is disposed above the semiconductor substrate 1, two second semiconductor regions 3 are disposed above the semiconductor substrate 1, and the high K dielectric region 4 is disposed above the semiconductor substrate 1, Two sides of the first semiconductor region 2 are respectively in contact with one side of the two second semiconductor regions 3, and a side of the two second semiconductor regions 3 not in contact with the first semiconductor region 2 is respectively associated with a high-K dielectric region 4 In contact with each other, the width of the second semiconductor region 3 is not greater than the first semiconductor region 2, the doping concentration of the second semiconductor region 3 is higher than that of the first semiconductor region 2, and the trench gate structure 13 is disposed in the first semiconductor region 2. Above, the active region is disposed above the high K dielectric region 4 and is in contact with the upper surface of the high K dielectric region 4 and is in contact with the trench gate structure 13.
这里， 第一半导体区 2为 n—型掺杂 （即掺杂浓度低于 n型掺杂浓度的 n 型介质）， 第二半导体区 3为 n型掺杂， 第一半导体区 2为耐压区， 第二半导 体区 3为低阻电流通道， 有源区包括 p型体区 5以及设置在 p型体区 5上面 的 p+半导体体接触区 7和 n +半导体源区 9， n +半导体源区 9与栅介质 6相接 触， 源极电极 S设置在 p+半导体体接触区 7和部分 n +半导体源区 9上， 源极 电极 S为金属层 8， 源极电极 S与栅电极 G之间具有绝缘层 10， 漏极电极 D 设置在半导体衬底 1下方；槽栅结构 13包括栅介质 6及栅介质 6包围的导电 材料 11， 从导电材料 11表面引出栅电极 G, 栅电极 G为金属层 8， 导电材料 11可以由多晶硅形成， 栅介质 6为高 K介质或二氧化硅， 构成栅介质 6的高 K介质与高 K介质区中的高 K介质可以相同也可以不同。 Here, the first semiconductor region 2 is n-type doped (ie, an n-type medium having a doping concentration lower than the n-type doping concentration), the second semiconductor region 3 is n-type doped, and the first semiconductor region 2 is withstand voltage The second semiconductor region 3 is a low-resistance current channel, and the active region includes a p-type body region 5 and a p+ semiconductor body contact region 7 and an n + semiconductor source region 9 disposed on the p-type body region 5, and an n + semiconductor source The region 9 is in contact with the gate dielectric 6, the source electrode S is disposed on the p+ semiconductor body contact region 7 and a portion of the n + semiconductor source region 9, the source electrode S is the metal layer 8, and between the source electrode S and the gate electrode G An insulating layer 10 is disposed, and a drain electrode D is disposed under the semiconductor substrate 1. The trench gate structure 13 includes a gate dielectric 6 and a conductive material 11 surrounded by the gate dielectric 6. The gate electrode G is extracted from the surface of the conductive material 11, and the gate electrode G is a metal. The layer 8, the conductive material 11 may be formed of polysilicon, the gate dielectric 6 is a high K dielectric or silicon dioxide, and the high K dielectric constituting the gate dielectric 6 may be the same as or different from the high K dielectric in the high K dielectric region.
其中， 本例的第一半导体区 2与第二半导体区 3的导电类型相同， 第二 半导体区 3小于或等于第一半导体区 2的宽度，槽栅结构 13的宽度小于第一 半导体区 2和第二半导体区 3的宽度之和， 这里的第一半导体区 2、 第二半 导体区 3及高 K介质区 4为柱状， 分别垂直于半导体衬底 1， 此时高 K介质 区垂直于半导体衬底且经过第一半导体区为中心的剖面形状为矩形， 第一半 导体区 2、 第二半导体区 3及高 K介质区 4也可以为其他形状， 例如高 K介 质区高 K介质区垂直于半导体衬底且经过第一半导体区为中心的剖面形状为 梯形或三角形， 高 K介质区的相对介电常数大于半导体漂移区的相对介电常 数， 优选的， 高 K介质的临界击穿电场大于 30ν/μπι; 半导体漂移区可以是 半导体硅（Κ=11.9)、锗（Κ=16)、碳化硅 (Κ=9.7-10.3 )以及砷化镓（Κ=13.1 ) 等半导体材料。 Wherein, the first semiconductor region 2 of the present example has the same conductivity type as the second semiconductor region 3, the second semiconductor region 3 is smaller than or equal to the width of the first semiconductor region 2, and the width of the trench gate structure 13 is smaller than the first The sum of the widths of the semiconductor region 2 and the second semiconductor region 3, where the first semiconductor region 2, the second semiconductor region 3, and the high-k dielectric region 4 are columnar, respectively perpendicular to the semiconductor substrate 1, and at this time, the high-k dielectric region The cross-sectional shape perpendicular to the semiconductor substrate and centered on the first semiconductor region is rectangular, and the first semiconductor region 2, the second semiconductor region 3, and the high-k dielectric region 4 may have other shapes, such as a high-k dielectric high-k dielectric. The cross-sectional shape perpendicular to the semiconductor substrate and passing through the first semiconductor region is trapezoidal or triangular, and the relative dielectric constant of the high-k dielectric region is greater than the relative dielectric constant of the semiconductor drift region. Preferably, the critical strike of the high-k dielectric The electric field is greater than 30ν/μπι ; the semiconductor drift region may be semiconductor materials such as semiconductor silicon (Κ=11.9), germanium (Κ=16), silicon carbide (Κ=9.7-10.3), and gallium arsenide (Κ=13.1).
本例的槽栅结构 13的底部与有源层底部平行，但是工艺上无法准确的控 制槽栅结构 13底部与有源区底部平行， 为了保证功率器件能正常开启， 槽栅 结构 13底部要做的比有源层底部低，深槽栅使得在栅加开启电压的时候会在 槽栅的表面形成积累层可以减低导通电阻， 但是深槽栅同时也减小了漂移区 长度导致耐压降低， 可选的， 槽栅结构 13 向下超过有源区， 使槽栅结构 13 的深度低于有源区的下表面， 其剖面图如图 3。  The bottom of the trench gate structure 13 of this example is parallel to the bottom of the active layer, but the process cannot accurately control the bottom of the trench gate structure 13 parallel to the bottom of the active region. To ensure that the power device can be normally turned on, the bottom of the trench gate structure 13 is to be It is lower than the bottom of the active layer. The deep trench gate makes the accumulation layer on the surface of the trench gate reduce the on-resistance when the gate is turned on. However, the deep trench gate also reduces the length of the drift region and causes the withstand voltage to decrease. Optionally, the trench gate structure 13 extends downward beyond the active region, so that the trench gate structure 13 has a lower depth than the lower surface of the active region, and a cross-sectional view thereof is shown in FIG.
若器件运用于高耐压场所， 由于工艺上的限制介质槽的深度不能做得很 深， 所以可以做成半介质槽结构来提高耐压， 即半导体漂移区和高 k介质区 If the device is used in a high withstand voltage, the depth of the medium groove cannot be made deep due to the process limitation, so a semi-dielectric groove structure can be used to increase the withstand voltage, that is, the semiconductor drift region and the high k dielectric region.
4的底部与半导体衬底 1之间有半导体耐压层 12， 其导电类型与第二半导体 区 3相同， 该结构可以降低刻槽深度以及倾角注入的工艺难度， 并借助该层 承受部分耐压， 这更适合于耐压较高（耐压高于 400V) 的运用领域， 由此提 出了 N沟道具有低阻电流通道的 semi介质槽结构的槽栅 VDMOS结构如图 4 所示， 其与图 2的实施例的区别在于： 在 n型低掺杂的第一半导体区 2和 n 型掺杂的第二半导体区 3及高 K介质区 4下面且在半导体衬底 1上面具有一 层半导体耐压层 12， 由此形成半高 K介质结构。 由于低掺杂半导体耐压层 12的存在， n型低掺杂第一半导体区 2和 n型掺杂第二半导体区 3的高度可 以比图 2中的小， 这样进一歩简化了器件的制造工艺， 优选地低掺杂半导体 层 12的掺杂类型与第二半导体区 3的掺杂类型相同，但是掺杂浓度比半导体 区 3的掺杂浓度低。 Between the bottom of the 4 and the semiconductor substrate 1 is a semiconductor withstand voltage layer 12 having the same conductivity type as the second semiconductor region 3, which can reduce the depth of the groove and the process difficulty of the tilt injection, and withstand the partial withstand voltage by means of the layer This is more suitable for the application field with higher withstand voltage (withstand voltage higher than 400V). Therefore, the trench gate VDMOS structure of the semi-channel structure with N-channel low-resistance current channel is proposed as shown in Fig. 4, which is The embodiment of Fig. 2 differs in that: under the n-type low doped first semiconductor region 2 and the n-type doped second semiconductor region 3 and the high K dielectric region 4 and on the semiconductor substrate 1 there is a semiconductor The pressure resistant layer 12, thereby forming a half-height K dielectric structure. Due to the presence of the low doped semiconductor withstand voltage layer 12, the height of the n-type low doped first semiconductor region 2 and the n-type doped second semiconductor region 3 can be smaller than that of FIG. 2, which further simplifies device fabrication. The process, preferably the doping type of the low doped semiconductor layer 12 is the same as the doping type of the second semiconductor region 3, but the doping concentration is lower than the doping concentration of the semiconductor region 3.
上面以 N沟道具有低阻电流通道的槽栅 VDMOS器件为例说明了本发明 的半导体器件的结构， 本发明的结构同样适用于 N沟道超结结构 VDMOS器 件。 例如， 图 5中的器件与图 2中的器件的结构对应， 只是由图 2器件的第 一半导体区 2的掺杂由 n型低掺杂变为 p型， 且与第二半导体区构成超结结 构， 即是本申请中所述第一半导体区与第二半导体区的导电类型不同， 当第 一半导体区与第二半导体区的导电类型不同时， 槽栅结构的宽度大于或等于 第一半导体区的宽度， 且小于第一半导体区和第二半导体区的宽度之和。 The structure of the semiconductor device of the present invention has been described above by taking a trench gate VDMOS device having an N-channel low resistance current path as an example, and the structure of the present invention is equally applicable to an N-channel super junction structure VDMOS device. For example, the device in FIG. 5 corresponds to the structure of the device in FIG. 2, except that the doping of the first semiconductor region 2 of the device of FIG. 2 is changed from n-type low doping to p-type, and is super-exposed with the second semiconductor region. Knot The first semiconductor region and the second semiconductor region have different conductivity types. When the conductivity types of the first semiconductor region and the second semiconductor region are different, the width of the trench gate structure is greater than or equal to the first semiconductor. The width of the region is smaller than the sum of the widths of the first semiconductor region and the second semiconductor region.
上面以 N沟道具有低阻电流通道的槽栅 VDMOS器件为例说明了本发明 的半导体器件的结构， 本发明的结构同样适用于 P沟道的 VDMOS器件。 例 如， 图 6中的器件与图 2中的器件的结构对应， 只是由图 2的 N沟道具有低 阻电流通道的槽栅 VDMOS 器件变为 P 沟道具有低阻电流通道的槽栅 VDMOS器件， 所以每个半导体区域的导电类型相应改变。  The structure of the semiconductor device of the present invention has been described above by taking a trench gate VDMOS device having an N-channel low resistance current path as an example, and the structure of the present invention is also applicable to a P-channel VDMOS device. For example, the device in FIG. 6 corresponds to the structure of the device in FIG. 2, but the trench gate VDMOS device having the low-resistance current channel of the N-channel of FIG. 2 is changed into the P-channel trench-gate VDMOS device having the low-resistance current channel. Therefore, the conductivity type of each semiconductor region changes accordingly.
另外， VDMOS器件只是本发明的半导体器件的一个实施例， 本发明的 槽栅半导体功率器件可以为 N沟道或 P沟道的 MOS器件或 MOS控制的半导 体器件， MOS器件就如上述 VDMOS器件， MOS控制的半导体器件包括 IGBT 等。 N沟道具有低阻电流通道的槽栅 IGBT器件剖视图如图 7所示， 图 7中 的器件与图 2中的器件的不同主要在于用 p+半导体衬底 1代替图 2中的 n +半 导体衬底 1， 图 4所示的半超结结构也适用于 IGBT。 In addition, the VDMOS device is only one embodiment of the semiconductor device of the present invention, and the trench gate semiconductor power device of the present invention may be an N-channel or P-channel MOS device or a MOS-controlled semiconductor device, and the MOS device is like the VDMOS device described above. MOS controlled semiconductor devices include IGBTs and the like. A cross-sectional view of a trench IGBT device having an N-channel low-resistance current path is shown in FIG. 7. The device in FIG. 7 is different from the device in FIG. 2 mainly in that the n + semiconductor lining in FIG. 2 is replaced by a p+ semiconductor substrate 1. Bottom 1, the semi-super junction structure shown in Figure 4 is also applicable to IGBTs.
上述本发明的结构显著改善器件的导通特性， 例如相对于常规超结 VDMOS器件导通电阻降低约 30%, 并且提高了器件的耐压以及降低了耐压 对电荷不平衡的敏感性。  The structure of the present invention described above significantly improves the on-characteristics of the device, e.g., by about 30% lower than the on-resistance of a conventional superjunction VDMOS device, and increases the withstand voltage of the device and reduces the sensitivity of the withstand voltage to charge imbalance.
下面通过图 2中的本发明的半导体器件与图 1中的常规超结 VDMOS器 件进行比较进一歩说明本发明的优点：  The advantages of the present invention will now be described by comparing the semiconductor device of the present invention in FIG. 2 with the conventional superjunction VDMOS device of FIG.
1. 器件特性分析 1. Device characterization
1 ) 导通电阻 1) On-resistance
常规的高压槽栅 VDMOS结构的导通电阻 R。„， 主要由漂移区电阻 RD和 沟道电阻 Rch串联而成， 即 R。„ = RD +Rch。 The on-resistance R of a conventional high voltage trench gate VDMOS structure. „, mainly by the drift region resistance R D and the channel resistance R ch in series, that is, R. „ = R D + R ch .
本发明半导体器件的体区的参数可以与常规的槽栅超结 VDMOS的体区 参数相等， 所以两种器件的沟道电阻可认为相等。  The parameters of the body region of the semiconductor device of the present invention can be equal to the body region parameters of the conventional trench gate super-junction VDMOS, so the channel resistances of the two devices can be considered equal.
漂移区电阻 RD主要由漂移区的浓度、宽度、长度以及电流拓展效应有关。 由于本发明所提出的结构采用了高 K介质且第二半导体区 3相对较窄， 使第 二半导体区 3的优化浓度不仅远大于常规的槽栅超结 VDMOS的 n柱区优化 浓度， 而且当采用槽栅超结 VDMOS实施例时其还大于本发明电荷平衡所需 要的 n柱区浓度 （即 n柱区浓度与横向宽度的乘积大于 p柱区浓度与横向宽 度的乘积）， 所以最后导致提出的结构的导通电阻很小。 The drift region resistance R D is mainly related to the concentration, width, length, and current spreading effects of the drift region. Since the structure proposed by the present invention employs a high-k dielectric and the second semiconductor region 3 is relatively narrow, the optimized concentration of the second semiconductor region 3 is not only much larger than the optimized concentration of the n-column region of the conventional trench-gate super-junction VDMOS, but also The slot-gate super-junction VDMOS embodiment is also larger than the n-column concentration required for the charge balance of the present invention (ie, the product of the n-column concentration and the lateral width is greater than the product of the p-column concentration and the lateral width), so The on-resistance of the structure is small.
本发明提出的结构显著降低了正向的导通电阻， 降低器件功耗。 2) 击穿电压 The structure proposed by the present invention significantly reduces the forward on-resistance and reduces the power consumption of the device. 2) breakdown voltage
与常规槽栅超结 VDMOS相比，本发明的结构对体内电场具有调制作用， 使器件耐压提高约 10%， 且由于高 K介质的引入使得耐压对第二半导体区的 掺杂变化不是很敏感， 降低了工艺难度。  Compared with the conventional trench gate super-junction VDMOS, the structure of the present invention has a modulation effect on the electric field in the body, which increases the withstand voltage of the device by about 10%, and the doping variation of the withstand voltage to the second semiconductor region is not due to the introduction of the high-k dielectric. Very sensitive, reducing the difficulty of the process.
上述分析表明， 本发明与常规的 VDMOS结构相比， 耐压有所上升， 导 通电阻下降了近乎 30%。 另外， 本发明的结构还具有制造工艺简单， 工艺容 差大， 动态特性好等特性。  The above analysis shows that the present invention has a higher withstand voltage and a nearly 30% lower on-resistance than the conventional VDMOS structure. Further, the structure of the present invention has the characteristics of simple manufacturing process, large process tolerance, and good dynamic characteristics.
2. 性能评价 2. Performance evaluation
综合考虑各个参数对器件性能的影响以及基于对工艺难度的考虑， 根据 图 2建立本发明专利提出的结构模型， 基于该模型， 利用 med1C1仿真软件对 器件的性能进行仿真。 Considering the influence of various parameters on the performance of the device and based on the consideration of the process difficulty, the structural model proposed by the patent of the present invention is established according to FIG. 2, and based on the model, the performance of the device is simulated by using the med 1C1 simulation software.
1 ) 阻断特性 1) Blocking characteristics
图 1中常规槽栅超结 VDMOS器件的击穿电压与其 n型半导体区的关系 及本发明实施例的半导体器件的击穿电压与其第二半导体区浓度 Nn的关系 示意图如图 8所示， 其中， 横坐标 Nn表示第二半导体区 3的掺杂浓度， 纵坐 标表示击穿电压。 FIG. 8 is a schematic diagram showing the relationship between the breakdown voltage of a conventional trench gate super-junction VDMOS device and its n-type semiconductor region, and the breakdown voltage of the semiconductor device of the embodiment of the present invention and its second semiconductor region concentration N n . Here, the abscissa N n represents the doping concentration of the second semiconductor region 3, and the ordinate represents the breakdown voltage.
常规的槽栅超结 VDMOS (见图 1 )的击穿电压和 n柱区浓度的关系如图 8左侧的曲线所示， 本发明的 VDMOS器件的击穿电压和第二半导体区 3的 浓度的关系如图 6右侧的曲线所示。  The breakdown voltage of the conventional trench gate super-junction VDMOS (see FIG. 1) and the n-column region concentration are shown in the graph on the left side of FIG. 8, the breakdown voltage of the VDMOS device of the present invention and the concentration of the second semiconductor region 3. The relationship is shown in the curve on the right side of Figure 6.
图 8 显示， 本发明的半导体器件的 n+区优化浓度比常规的槽栅超结 Figure 8 shows that the optimized concentration of the n+ region of the semiconductor device of the present invention is larger than that of the conventional trench gate.
VDMOS结构高 1个数量级， 因而导通电阻和导通损耗降低； 而且， 击穿电 压对 n +区浓度 Nn变化（电荷非平衡） 的敏感性降低， 因而工艺容差更大； 再 者， 本发明的半导体器件的最高击穿电压较常规超结 VDMOS高约 20V。 The VDMOS structure is one order of magnitude higher, and thus the on-resistance and conduction loss are reduced. Moreover, the sensitivity of the breakdown voltage to the n + region concentration N n change (charge non-equilibrium) is lowered, and thus the process tolerance is larger; The highest breakdown voltage of the semiconductor device of the present invention is about 20 V higher than that of the conventional super junction VDMOS.
从图 8中可以看出： （1 ) 常规槽栅超结 VDMOS器件在电荷平衡时击穿 电压达到最大。 （2) 对于本发明提出的器件结构的耐压受第二半导体区 3的 浓度影响， 第二半导体区 3的浓度越高耐压越低， 且在相同耐压下其第二半 导体区 3的掺杂浓度远高于常规超结 VDMOS的掺杂浓度。 （3 ) 与常规槽栅 超结 VDMOS器件相比， 本发明提出的结构的击穿电压对第二半导体区的浓 度变化不敏感。  It can be seen from Figure 8 that: (1) The conventional trench gate super-junction VDMOS device has the maximum breakdown voltage during charge balance. (2) The withstand voltage of the device structure proposed by the present invention is affected by the concentration of the second semiconductor region 3, the higher the concentration of the second semiconductor region 3, the lower the withstand voltage, and the second semiconductor region 3 at the same withstand voltage The doping concentration is much higher than the doping concentration of conventional superjunction VDMOS. (3) The breakdown voltage of the structure proposed by the present invention is insensitive to the concentration variation of the second semiconductor region as compared with the conventional trench gate superjunction VDMOS device.
2) 正向导通特性 2) Forward conduction characteristics
常规槽栅超结 VDMOS器件器件和本发明实施例的半导体器件中高 K介 质区在不同的 K值时正向导通特性的比较示意图如图 9所示，其中， V漏表示 漏极的电压， I fi表示漏极的电流， 在给定的漏极电流下， 本发明提出的结构 具有很低的正向压降， 且 κ值越大， 导通电阻越低。 这主要是由于高 K介质 影响的结果。 A comparison diagram of the forward conduction characteristics of the high-k dielectric region of the conventional trench gate super-junction VDMOS device device and the semiconductor device of the embodiment of the present invention is shown in FIG. 9 , wherein V drain represents The voltage of the drain, I fi , represents the current of the drain. Under a given drain current, the structure proposed by the present invention has a very low forward voltage drop, and the larger the value of κ, the lower the on-resistance. This is mainly due to the effect of high K media.
3 ) 动态特性  3) Dynamic characteristics
在常规的槽栅超结 VDMOS和本发明提出的结构在不同的 K值时动态特 性比较中， 在给定的栅电压、 漏电流、 漏电压的条件下， 本发明提出结构的 栅电荷波形与常规的槽栅超结 VDMOS几乎一样， 且随着 K值变化不大。  In the comparison of the dynamic characteristics of the conventional trench gate super-junction VDMOS and the structure proposed by the present invention at different K values, the gate charge waveform of the structure proposed by the present invention is given under the conditions of given gate voltage, leakage current and drain voltage. The conventional trench gate superjunction VDMOS is almost the same and does not change much with the K value.
本发明与美国专利 US7 , 230， 310B2的区别在于： 1 ) 耐压层中半导体 区不同： 本发明的半导体漂移区具有两个半导体区第一半导体区 2和第二半 导体区 3， 所述高 K介质区与所述第二半导体区 3相邻； 而该美国专利结构 只有一个半导体区 （权利要求 1 中所述）； 2) 半导体区的作用不同： 本发明 的第二半导体区 3的是一个低阻通道， 其浓度比第一半导体区 2高一个数量 级以上， 其主要作用是功率器件正向导通的时候的低阻电流通道， 来降低比 导通电阻。 本发明的第一半导体区 2的作用是调制电场， 其掺杂较低因此电 场斜率小， 其和高 K介质区一起调制漂移区的电场分布， 而该美国专利结构 中的半导体区关态时耐压、 开态时作为整个半导体区作为电流通道； 3 )高 K 介质区起作用的区域不同： 本发明高 K介质区 4是主要是调制第二半导体区 3的电场分布和辅助耗尽第二半导体区 3， 因为第二半导体区 3是一个与高 K 介质区 4相邻的窄条， 高 K介质区 4对其辅助耗尽作用更明显， 可显著提高 第二半导体区 3的浓度， 从而降低导通电阻， 且高 K介质区 4对第二半导体 区 3的作用受介质槽间距变化影响很小， 而该美国专利结构中随着高 K介质 的间距的增大， 也就是半导体区的宽度增加， 高 K介质对半导体区的作用随 着高 K介质的间距的增大而被削弱， 导致其在在介质槽大间距、 小密度情况 下对改善功率器件耐压与比导通电阻之间的矛盾关系能力大为减弱。  The present invention differs from U.S. Patent No. 7,230,310B2 in that: 1) the semiconductor regions in the withstand voltage layer are different: the semiconductor drift region of the present invention has two semiconductor regions, a first semiconductor region 2 and a second semiconductor region 3, said high The K dielectric region is adjacent to the second semiconductor region 3; and the U.S. patent structure has only one semiconductor region (described in claim 1); 2) the semiconductor region functions differently: the second semiconductor region 3 of the present invention is A low-resistance channel whose concentration is more than an order of magnitude higher than that of the first semiconductor region 2, and its main function is a low-resistance current channel when the power device is conducting in the forward direction to reduce the specific on-resistance. The first semiconductor region 2 of the present invention functions to modulate an electric field having a lower doping and thus a smaller electric field slope, which together with the high K dielectric region modulate the electric field distribution of the drift region, and the semiconductor region in the U.S. patent structure is off. When the voltage is high, the whole semiconductor region acts as a current channel; 3) the high K dielectric region acts differently: the high K dielectric region 4 of the present invention mainly modulates the electric field distribution and the auxiliary depletion of the second semiconductor region 3. The second semiconductor region 3, because the second semiconductor region 3 is a narrow strip adjacent to the high K dielectric region 4, the high K dielectric region 4 is more effective in assisting depletion, and the concentration of the second semiconductor region 3 can be significantly increased. Thereby reducing the on-resistance, and the effect of the high-k dielectric region 4 on the second semiconductor region 3 is less affected by the variation of the dielectric trench spacing, and the US patent structure increases with the spacing of the high-k dielectric, that is, the semiconductor region. The width increases, and the effect of the high-k dielectric on the semiconductor region is weakened as the pitch of the high-k dielectric increases, causing it to improve the work at a large pitch and a small density in the dielectric trench. Capability contradictory relationship between the breakdown voltage and specific on-resistance greatly diminished.
本发明的半导体器件与常规的槽栅超结 VDMOS结构相比， 导通电阻下 降了约 30%， 耐压略有上升； 同时， 本发明的半导体器件具有工艺容差大的 优越性能， 克服了超结器件最常见也是较难解决的问题， 增加了器件设计和 制造的自由度。 同时本发明第一半导体区与第二半导体区可以做的很窄， 使 得导通电阻和器件面积较小。本发明的纵向 MOSFET器件最适合做低功耗的 功率器件， 特别是用于耐压为 100-300V的低功耗功率电子领域。  Compared with the conventional trench gate super-junction VDMOS structure, the semiconductor device of the present invention has a drop in on-resistance of about 30% and a slight increase in withstand voltage. Meanwhile, the semiconductor device of the present invention has superior performance with large process tolerance, and overcomes Superjunction devices are the most common and difficult problem to solve, increasing the freedom of device design and manufacturing. At the same time, the first semiconductor region and the second semiconductor region of the present invention can be made narrow, so that the on-resistance and the device area are small. The vertical MOSFET device of the present invention is most suitable for low power power devices, especially for low power power electronics with a withstand voltage of 100-300V.

Claims

权利要求书 claims
1、 槽栅半导体功率器件， 包括半导体衬底、 槽栅结构、 半导体漂移区及 有源区， 其特征在于， 还包括两个高 κ介质区， 所述两个高 K介质区设置在 半导体衬底上方， 半导体漂移区包括第一半导体区和两个第二半导体区， 第 一半导体区设置在半导体衬底上方， 两个第二半导体区设置在半导体衬底上 方， 第一半导体区的两侧分别与两个第二半导体区的一侧相接触， 两个第二 半导体区未与第一半导体区相接触的一侧分别与一个高 κ介质区相接触， 所 述第一半导体区的宽度不小于第二半导体区， 第二半导体区的掺杂浓度高于 第一半导体区， 所述槽栅结构设置在第一半导体区上方， 有源区设置在高 κ 介质区上方， 并与高 κ介质区的上表面相接触， 且与槽栅结构相接触。 1. A trench gate semiconductor power device, including a semiconductor substrate, a trench gate structure, a semiconductor drift region and an active region. It is characterized in that it also includes two high K dielectric regions, and the two high K dielectric regions are arranged on the semiconductor substrate. Above the bottom, the semiconductor drift region includes a first semiconductor region and two second semiconductor regions. The first semiconductor region is provided above the semiconductor substrate. The two second semiconductor regions are provided above the semiconductor substrate. Both sides of the first semiconductor region They are respectively in contact with one side of the two second semiconductor regions, and the side of the two second semiconductor regions that is not in contact with the first semiconductor region is in contact with a high κ dielectric region respectively. The width of the first semiconductor region is not is smaller than the second semiconductor region, the doping concentration of the second semiconductor region is higher than that of the first semiconductor region, the trench gate structure is disposed above the first semiconductor region, the active region is disposed above the high κ dielectric region, and is connected to the high κ dielectric region The upper surface of the region is in contact with the trench gate structure.
2、 根据权利要求 1所述槽栅半导体功率器件， 其特征在于， 所述第一半 导体区与第二半导体区的导电类型相同， 所述槽栅结构的宽度小于第一半导 体区和第二半导体区的宽度之和。 2. The trench gate semiconductor power device according to claim 1, wherein the first semiconductor region and the second semiconductor region have the same conductivity type, and the width of the trench gate structure is smaller than that of the first semiconductor region and the second semiconductor region. The sum of the widths of the zones.
3、 根据权利要求 1所述槽栅半导体功率器件， 其特征在于， 所述第一半 导体区与第二半导体区的导电类型不同， 所述槽栅结构的宽度大于或等于第 一半导体区的宽度， 且小于第一半导体区和第二半导体区的宽度之和。 3. The trench gate semiconductor power device according to claim 1, wherein the first semiconductor region and the second semiconductor region have different conductivity types, and the width of the trench gate structure is greater than or equal to the width of the first semiconductor region. , and is less than the sum of the widths of the first semiconductor region and the second semiconductor region.
4、 根据权利要求 1所述槽栅半导体功率器件， 其特征在于， 还包括半导 体耐压层， 所述半导体耐压层设置在半导体衬底上方， 第一半导体区、 第二 半导体区及高 K介质层下方， 所述半导体耐压层的导电类型与第二半导体区 相同。 4. The trench gate semiconductor power device according to claim 1, further comprising a semiconductor voltage-resistant layer, the semiconductor voltage-resistant layer is disposed above the semiconductor substrate, the first semiconductor region, the second semiconductor region and the high-K Below the dielectric layer, the conductivity type of the semiconductor voltage-resistant layer is the same as that of the second semiconductor region.
5、 根据权利要求 1所述槽栅半导体功率器件， 其特征在于， 所述槽栅结 构的下表面等于或低于有源区的下表面。 5. The trench gate semiconductor power device according to claim 1, wherein the lower surface of the trench gate structure is equal to or lower than the lower surface of the active region.
6、 根据权利要求 1 所述槽栅半导体功率器件， 其特征在于， 所述高 K 介质区的相对介电常数大于半导体漂移区的相对介电常数， 所述高 K介质的 临界击穿电场大于 30ν/μπι。 6. The trench gate semiconductor power device according to claim 1, wherein the relative dielectric constant of the high-K dielectric region is greater than the relative dielectric constant of the semiconductor drift region, and the critical breakdown electric field of the high-K dielectric is greater than 30ν/μπι.
7、 根据权利要求 1 所述槽栅半导体功率器件， 其特征在于， 所述高 Κ 介质区垂直于半导体衬底且经过第一半导体区为中心的剖面形状为矩形或梯 形或三角形。 7. The trench gate semiconductor power device according to claim 1, wherein the cross-sectional shape of the high-K dielectric region perpendicular to the semiconductor substrate and centered through the first semiconductor region is rectangular, trapezoidal, or triangular.
8、根据权利要求 1或 2或 3或 4或 5或 6或 7所述槽栅半导体功率器件， 其特征在于，所述槽栅半导体功率器件为 Ν沟道或 Ρ沟道的 MOS器件或 MOS 控制的半导体器件。 8. The trench gate semiconductor power device according to claim 1 or 2 or 3 or 4 or 5 or 6 or 7, characterized in that the trench gate semiconductor power device is an N-channel or P-channel MOS device or MOS controlled semiconductor devices.
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