CN105206666B - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
- Publication number
- CN105206666B CN105206666B CN201410232012.7A CN201410232012A CN105206666B CN 105206666 B CN105206666 B CN 105206666B CN 201410232012 A CN201410232012 A CN 201410232012A CN 105206666 B CN105206666 B CN 105206666B
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- impurity
- region
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of semiconductor devices, including：Substrate, the device region positioned at the epitaxial layer of substrate surface and in epitaxial layer, wherein：Oxide layer buried layer is provided in fixed area in substrate, which contacts with epitaxial layer, and is right against the drift region in device region；In epitaxial layer, except being provided with the first diffusion region in addition to the region of oxide layer buried layer face, which is in contact with substrate；Impurity conduction type in first diffusion region is identical as the conduction type of the impurity in substrate.The embodiment of the present invention efficiently solves manufacture such as rf-ldmos semiconductor field effect transistor in the prior art, it expands in dense doped substrate on impurity when carrying out sinking floor height temperature and driving in leads to effective epitaxy layer thickness reduction under drift region, and then the technical issues of so that device electric breakdown strength is declined.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor devices.
Background technology
Currently, in radio frequency-cross bimoment (Radio Frequency-
Lateral Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor, RF-
LDMOS it is used in structure) and is typically characterised by back of the body source technology, is i.e. source electrode is drawn from the device back side.The corresponding tradition of the technology
Method is that source electrode is guided to the back side using sinking layer by way of sinking layer injection (being usually p-type ion boron) and driving in.This
Kind of method, which needs prolonged high temperature to drive in, to be driven into p-type high concentration substrate the injection ion in sinking layer, allow sinking
Layer and substrate connect, to draw source electrode using substrate as the back side.
Fig. 1 carries on the back the substrate and epitaxial layer portion structure that source technology is formed to be utilized in existing RF-LDMOS, including：Dense doping
Substrate 1, epitaxial layer 2, sinking floor 3, the areas Xia Kuo 4 of sinking floor 3, dense doped substrate 1 the areas Shang Kuo 5.Wherein, dense doped substrate 1
It is identical with the doping type in sinking layer 3；The areas Xia Kuo 4 of sinking floor 3 and the areas Shang Kuo 5 of dense doped substrate 1 are respectively that device exists
The Doped ions that drive in rear corresponding sinking layer 3 and dense doped substrate 1 of high temperature for carrying out back of the body source technology are diffused into epitaxial layer 2
It is formed by structure.
For N-shaped RF-LDMOS, substrate and epitaxial layer are all the p-type boron ions adulterated, and sinking layer injects ion
It is the boron ion of p-type.The dense substrate of p-type is that (boron ion source protonatomic mass is small, is easy in the semiconductors under high temperature for boron due to doping
Diffusion), so in high Warming processes, inevitably quickly diffuse up, has tied up the space of p-type epitaxial layer so that
Effective epitaxy layer thickness (effective epitaxy layer thickness refers to the epitaxial thickness below the drift region of device) is greatly reduced, and then drops
The low breakdown voltage of RF-LDMOS.Therefore prior art, often according to the needs of device electric breakdown strength, increases when designing device
The thickness of epitaxial layer.But blocked up epitaxy layer thickness, and the difficulty that sinking layer is connected with substrate can be increased, while also will increase
The conducting resistance of device, makes device performance decline.
Invention content
The present invention provides a kind of semiconductor devices, manufactures RF-LDMOS to solve the prior art, is carrying out sinking layer
The technical issues of effectively epitaxy layer thickness reduces caused by expanding in dense doped substrate when high temperature drives in, and device electric breakdown strength declines.
The embodiment of the present invention provides a kind of semiconductor devices, including：Substrate, the epitaxial layer positioned at the substrate surface and position
Device region in the epitaxial layer；Wherein：
Oxide layer buried layer is provided in fixed area in the substrate, the oxide layer buried layer connects with the epitaxial layer
It touches, and the drift region being right against in the device region；
It is described except being provided with the first diffusion region in addition to the region of the oxide layer buried layer face in the epitaxial layer
First diffusion region is in contact with the substrate；Impurity conduction type in first diffusion region and the impurity in the substrate
Conduction type is identical, and its impurity concentration is higher than the impurity concentration in the epitaxial layer.
Semiconductor devices provided by the invention, the interior setting oxide layer buried layer of fixed area in the substrate, makes the oxide layer
Buried layer is contacted with epitaxial layer, and is right against the drift region being arranged in device region in the epitaxial layer.The program makes semiconductor devices
When carrying out high temperature injection process, avoid caused by drift region of the impurity in substrate into semiconductor devices be diffused
The reduction of effective epitaxy layer thickness under drift region, to avoid semiconductor devices breakdown voltage decline, improve device
Performance.
Description of the drawings
Fig. 1 is the substrate formed using back of the body source technology in existing RF-LDMOS and epitaxial layer diagrammatic cross-section；
Fig. 2 is the diagrammatic cross-section of semiconductor devices provided in an embodiment of the present invention；
Fig. 3 is the diagrammatic cross-section of another semiconductor devices provided in an embodiment of the present invention；
Fig. 4 a are the forming method of pad oxide and silicon nitride layer during preparing oxide layer buried layer in the embodiment of the present invention
Schematic diagram；
Fig. 4 b are the silicon nitride layer structural schematic diagram that photoetching is completed during preparing oxide layer buried layer in the embodiment of the present invention；
Fig. 4 c are the structural representation formed after pad oxide oxidation during preparing oxide layer buried layer in the embodiment of the present invention
Figure；
Fig. 4 d are that silicon nitride layer and pad oxide carry out wet method corruption during preparing oxide layer buried layer in the embodiment of the present invention
The structural schematic diagram formed after erosion；
After Fig. 4 e carry out chemical mechanical grinding for oxide layer buried layer during preparation oxide layer buried layer in the embodiment of the present invention
The structural schematic diagram of formation.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described.For convenience of explanation, amplification or
The size of different layer and region is reduced, so size as shown in the figure and ratio might not represent actual size, is not also reflected
The proportionate relationship of size.
Fig. 2 is the diagrammatic cross-section of semiconductor devices provided in an embodiment of the present invention.As shown in Fig. 2, the device architecture has
Body includes：Substrate 201, the epitaxial layer 202 positioned at 201 surface of substrate and the device region in the epitaxial layer, wherein：
Oxide layer buried layer 206 is provided in fixed area in substrate 201, which contacts with epitaxial layer, and
It is right against the drift region in device region；
In epitaxial layer 202, except with the first diffusion region 204 is provided in addition to the region of 206 face of oxide layer buried layer, this
One diffusion region 204 is in contact with substrate 201；Impurity conduction type in first diffusion region 204 and the impurity in substrate 201
Conduction type is identical, and its impurity concentration is higher than the impurity concentration in epitaxial layer.
Above-mentioned substrate 201 is specifically as follows the semi-conducting material with dense doping, such as silicon, germanium, gallium nitride, GaAs material
Material, incorporation impurity can be the impurity that conduction type is p-type, such as boron.Can also be conduction type be N-type impurity, as phosphorus,
Arsenic, antimony.
When preparing the RF-LDMOS such as N-type substrate due to prior art, the foreign ion of N-type is relative to p type impurity ion
Its atomic weight is larger, even if carrying out high-temperature process to device in device fabrication process, heat will not make N-type in substrate layer
Ion is largely diffused into epitaxial layer, influences effective epitaxy layer thickness below the position of drift region in epitaxial layer.Therefore originally
It is dense doping and the RF- that incorporation impurity is p type impurity that the structure type of semiconductor devices shown in embodiment, which is more suitable for substrate,
The structure type of LDMOS device.
In above-described embodiment, epitaxial layer 202 is specifically as follows incorporation impurity such as boron, phosphorus, arsenic, the silicon of antimony etc., germanium, nitridation
The materials such as gallium, GaAs.
In above-described embodiment, it is located at the specially prepared semiconductor devices of device region in epitaxial layer 202 in epitaxial layer
Corresponding device area in 202.It will be appreciated by those skilled in the art that be the device area be realize certain semiconductor device
Device architecture part essential to function, such as including source region, drain region, grid, well region and raceway groove structural region.The present invention is above-mentioned
The drift region between the grid and drain region of semiconductor devices prepared in the device region is important to notice that in embodiment
Position relationship between spatial position and substrate 201, and for the concrete type and structure of the semiconductor devices in the device region
And it is not limited.In other words, the semiconductor devices in the present embodiment is applicable to any kind of existing semiconductor devices.
In above-described embodiment, in substrate 201 and it is right against the oxide layer being arranged on the position of the drift region of device region and buries
Layer 206 can be used for preventing entire semiconductor devices under high temperature environment, in the region corresponding with oxide layer buried layer 206 of substrate 201
Foreign ion epitaxial layers 202 in spread, so as to avoid 202 subregion of drift region lower epi layer because miscellaneous in substrate 201
Epitaxy layer thickness caused by the influence of the diffusion of matter ion becomes smaller.
In order to more obviously protrude oxide layer buried layer 206 at high temperature to the blocking effect expanded on substrate impurity, opened up in Fig. 2
The actual scene that substrate 201 expands on substrate impurity in the case of a high temperature is shown.As shown in Fig. 2, region 204 is in substrate 201
The structure for the formation expanded on impurity；In comparison, above oxide layer buried layer 206 corresponding epitaxial layer 202 subregion
It is interior, due to the blocking of oxide layer buried layer 206, cause the corresponding substrate impurity in the subregion not on diffuse into epitaxial layer.
In general, corresponding epitaxy layer thickness directly affects entire device breakdown electricity under its drift region of semiconductor devices
(the portion of epi layer thickness is bigger, and breakdown voltage is bigger for the size of pressure；Otherwise breakdown voltage is smaller), therefore, above-described embodiment
Shown in semiconductor devices can effectively avoid or eliminate the breakdown voltage of device caused by substrate impurity is spread under high temperature and become smaller.
Further, it will be appreciated by those skilled in the art that：If by taking the RF-LDMOS in existing semiconductor devices as an example,
In addition to all device architectures for including in above-described embodiment 2, should also include in embodiment as shown in Figure 3：
In epitaxial layer 202, sinking layer is provided in the fixed area on 202 surface of epitaxial layer far from substrate 201
203, the impurity conduction type in the sinking layer 203 is identical as the conduction type of the impurity in substrate 201；
In epitaxial layer 202,203 periphery of sinking layer is provided with the second diffusion region 205, second diffusion region 205
Respectively with the source region contact of the first diffusion region 204 and semiconductor devices；Impurity conduction type in second diffusion region 205 with
The conduction type of impurity in sinking layer 203 is identical, and its impurity concentration is higher than the impurity concentration in epitaxial layer 202.
In above-described embodiment, the second diffusion region 205 is that its internal foreign ion is diffused into sinking layer 203 under high temperature environment
The structural region formed after in epitaxial layer 202.In actual process engineering, the second diffusion can be made by controlling temperature and duration
Area 205 is in contact with the source area of device region and above-mentioned first diffusion region 204 respectively, to make source area be realized with substrate 201
Short circuit, and then realize above-mentioned back of the body source technology, draw source electrode from substrate side.
Further, the impurity conduction type of substrate 201 is p-type in semiconductor devices shown in the present embodiment.Specifically
It can be realized by mixing boron impurity ion into substrate 201.
Further, oxide layer buried layer 206 shown in the present embodiment be the thickness that generates of the method for using thermal oxide for
0.5~1 micron of oxide layer.
Specifically, preparing the process of oxide layer buried layer 206 can be：
1, pad oxide and silicon nitride layer are sequentially generated on substrate；
Fig. 4 a are that the forming method of pad oxide and silicon nitride layer is shown during preparing oxide layer buried layer in the present embodiment
It is intended to.As shown in fig. 4 a, the method for generating pad oxide is that above-mentioned underlayer temperature is carried out high temperature oxygen between 850~950 degree
Change, is existed with generating thicknessBetween oxide layer as pad oxide.With low-pressure chemical vapor deposition process upper
It states pad oxide surface and deposits one layer of silicon nitride layer, thickness isBetween.
2, lithography and etching processing is carried out successively to silicon nitride layer, to remove the silicon nitride layer in fixed area；
Fig. 4 b are the silicon nitride layer structural schematic diagram that etching is completed during preparing oxide layer buried layer in the present embodiment.Such as figure
Shown in 4b, by existing lithography and etching technique, lithography and etching is carried out to silicon nitride layer successively, to get rid of on silicon nitride layer
Silicon nitride in fixed area makes corresponding pad oxide in the fixed area be exposed.
3, the pad oxide surface of exposure after the silicon nitride layer in removal fixed area is aoxidized, to generate oxide layer
Buried layer；
Fig. 4 c are the structural schematic diagram formed after pad oxide oxidation during preparing oxide layer buried layer in the present embodiment.Such as
Shown in Fig. 4 c, specifically, the process that thermal oxide can be used in the process is into trip temperature to the pad oxide of above-mentioned exposure
1000~1200 degree of high temperature oxidation process, makes the part pad oxide mushroom out thickening, is to generate thicknessOxide layer as oxide layer buried layer.
4, wet etching is carried out to silicon nitride layer and pad oxide, to remove silicon nitride layer and pad oxide, retains oxidation
Layer buried layer；
After Fig. 4 d is silicon nitride layers during preparation oxide layer buried layer in the present embodiment and pad oxide progress wet etching
The structural schematic diagram of formation.As shown in figure 4d, during being somebody's turn to do, hot phosphoric acid can be used in removal silicon nitride layer, and this method will not be to oxygen
Changing layer buried layer has corrosiveness；Hydrofluoric acid can be used in removal pad oxide, which can be to oxide layer in concrete technology practice
Buried layer is lossy, but pad oxide wants thin too many compared to oxide layer buried layer its thickness, so this loss can be ignored not
Meter.
5, chemical mechanical grinding is carried out to the oxide layer buried layer of reservation, so that the oxide layer buried layer surface after grinding and substrate
Surface is in the same plane；Fig. 4 e are that oxide layer buried layer progress chemical machinery is ground during preparing oxide layer buried layer in the present embodiment
The structural schematic diagram formed after mill passes through chemical mechanical grinding (Chemical Mechanical as shown in fig 4e
Polishing, CMP) technique, grinds off the oxide layer for being higher by substrate surface so that entire substrate surface restores smooth.So far complete
At the generating process of oxide layer buried layer.
Semiconductor devices provided by the invention makes the oxygen by the way that oxide layer buried layer is arranged in fixed area in the substrate
Change layer buried layer to contact with epitaxial layer, and be right against the drift region in device region, prevents substrate under high temperature environment, it is internal miscellaneous
Epitaxial layer of the matter below the drift region into semiconductor devices is expanded, and then is avoided and floated caused by substrate impurity is spread
The breakdown voltage of device caused by the effective epitaxy layer thickness moved below area becomes smaller declines, and improves the performance of device.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to
So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into
Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (8)
1. a kind of semiconductor devices, which is characterized in that including：Substrate, positioned at the epitaxial layer of the substrate surface and positioned at described
Device region in epitaxial layer, wherein：
Oxide layer buried layer is provided in fixed area in the substrate, the oxide layer buried layer is contacted with the epitaxial layer, and
It is right against the drift region in the device region；
In the epitaxial layer, except be provided with the first diffusion region in addition to the region of the oxide layer buried layer face, described first
Diffusion region is in contact with the substrate；The conduction of impurity conduction type and the impurity in the substrate in first diffusion region
Type is identical；
Further include：
In the epitaxial layer, the sinking layer being arranged in the fixed area of the epi-layer surface far from substrate, the sinking layer
In impurity conduction type it is identical as the conduction type of the impurity in the substrate；
In the epitaxial layer, around the sinking layer periphery setting the second diffusion region, second diffusion region respectively with
First diffusion region and source region contact, the source area are set to the device region, the impurity in second diffusion region
Concentration is higher than the impurity concentration in the epitaxial layer, and second diffusion region is that impurity is diffused at high temperature in the sinking layer
It is formed in the epitaxial layer.
2. semiconductor devices according to claim 1, first diffusion region is that impurity expands at high temperature in the substrate
It is scattered in the epitaxial layer and is formed.
3. semiconductor devices according to claim 1 or 2, which is characterized in that the conduction type of the impurity in the substrate
For p-type.
4. semiconductor devices according to claim 1 or 2, which is characterized in that the thickness of first diffusion region is described
The half of the thickness of epitaxial layer.
5. semiconductor devices according to claim 1 or 2, which is characterized in that the thickness of the oxide layer buried layer be 0.5~
1 micron.
6. semiconductor devices according to claim 1 or 2, which is characterized in that the oxide layer buried layer is using thermal oxide
Method generate oxide layer.
7. semiconductor devices according to claim 1, which is characterized in that the substrate is any in silicon, germanium, gallium nitride
Material.
8. semiconductor devices according to claim 1, which is characterized in that the impurity in the substrate is boron ion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410232012.7A CN105206666B (en) | 2014-05-28 | 2014-05-28 | Semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410232012.7A CN105206666B (en) | 2014-05-28 | 2014-05-28 | Semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105206666A CN105206666A (en) | 2015-12-30 |
| CN105206666B true CN105206666B (en) | 2018-09-25 |
Family
ID=54954230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410232012.7A Active CN105206666B (en) | 2014-05-28 | 2014-05-28 | Semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105206666B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298475B (en) * | 2015-06-03 | 2020-07-14 | 北大方正集团有限公司 | Method for reducing expansion on semiconductor substrate |
| CN106997898B (en) * | 2016-01-26 | 2019-10-15 | 北大方正集团有限公司 | Semiconductor structure and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103545346A (en) * | 2012-07-09 | 2014-01-29 | 上海华虹Nec电子有限公司 | Isolated N-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof |
| CN103606562A (en) * | 2013-09-03 | 2014-02-26 | 北京大学深圳研究院 | Buried N-type layer partial silicon-on-insulator LDMOS transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101572476B1 (en) * | 2008-12-12 | 2015-11-27 | 주식회사 동부하이텍 | semiconductor and method of manufacturing the same |
-
2014
- 2014-05-28 CN CN201410232012.7A patent/CN105206666B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103545346A (en) * | 2012-07-09 | 2014-01-29 | 上海华虹Nec电子有限公司 | Isolated N-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof |
| CN103606562A (en) * | 2013-09-03 | 2014-02-26 | 北京大学深圳研究院 | Buried N-type layer partial silicon-on-insulator LDMOS transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105206666A (en) | 2015-12-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106876485A (en) | Double trench MOSFET devices of a kind of SiC of integrated schottky diode and preparation method thereof | |
| CN105097914B (en) | Transverse diffusion metal oxide semiconductor device and its manufacture method | |
| JP2012038810A (en) | Semiconductor device and manufacturing method thereof | |
| US20240222498A1 (en) | Semiconductor device including trench gate structure and buried shielding region and method of manufacturing | |
| WO2016058277A1 (en) | Shallow-trench semi-super-junction vdmos device and manufacturing method therefor | |
| CN109065627A (en) | A kind of LDMOS device with polysilicon island | |
| CN107768428A (en) | lateral double-diffused metal oxide semiconductor (L DMOS) device and manufacturing method thereof | |
| CN102983171A (en) | Structure and manufacturing method of vertical junctionless gate-all-round MOSFET device | |
| CN104637821A (en) | Manufacturing method of super junction device | |
| CN106158957B (en) | Transverse diffusion metal oxide semiconductor field effect pipe and its manufacturing method | |
| CN108346696A (en) | LDMOS device and its manufacturing method | |
| EP2897159B1 (en) | High-voltage super-junction igbt manufacturing method | |
| CN103178087A (en) | Ultra-high voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure and production method thereof | |
| CN105206666B (en) | Semiconductor devices | |
| CN117153888B (en) | Semiconductor device and method for manufacturing the same | |
| CN206574721U (en) | A kind of double trench MOSFET devices of SiC of integrated schottky diode | |
| CN103531592B (en) | Three gate control type nodeless mesh body pipes of high mobility low source and drain resistance | |
| CN104425258A (en) | Manufacturing method for reverse conducting FS IGBT (field stop insulated gate bipolar transistor) | |
| CN103187254B (en) | A kind of manufacture method of dual poly gate | |
| CN102931081B (en) | Manufacturing method for semiconductor device with field barrier layer | |
| CN105990254A (en) | Manufacturing method of BiCMOS integrated circuit | |
| CN105826195A (en) | Super junction power device and manufacturing method thereof | |
| CN106257630B (en) | The manufacturing method of radio frequency LDMOS device | |
| CN103022087A (en) | Semiconductor chip and production method thereof | |
| CN103377941A (en) | PMOS transistor and forming method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220718 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |