CN105206666A - Semiconductor device - Google Patents
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- CN105206666A CN105206666A CN201410232012.7A CN201410232012A CN105206666A CN 105206666 A CN105206666 A CN 105206666A CN 201410232012 A CN201410232012 A CN 201410232012A CN 105206666 A CN105206666 A CN 105206666A
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Abstract
The invention provides a semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer arranged on the surface of the substrate and a device region arranged in the epitaxial layer, wherein the an oxide buried layer is arranged in a fixed area of the substrate, and the oxide buried layer is in contact with the epitaxial layer and directly faces a drift region in the device region; the epitaxial layer is provided with a first diffusion region except the region directly facing the oxide buried layer, and the first diffusion region is in contact with the substrate; and the conductive type of impurities in the first diffusion region is identical with the conductive type of impurities in the substrate. The semiconductor device effectively solves the problems in the prior art that in the manufacturing process of an existing semiconductor device such as a radio frequency-lateral dual-diffusion metal oxide semiconductor field effect transistor, impurities in a strongly-doped substrate diffuses upwards when a sinking layer is driven in at a high temperature, the effective thickness of the epitaxial layer is reduced, and the breakdown voltage of the device further decreases.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of semiconductor device.
Background technology
At present, at radio frequency-cross bimoment (RadioFrequency-LateralDouble-DiffusedMetal-Oxide-Semicon ductorField-EffectTransistor, RF-LDMOS) characteristic feature adopted in structure is back of the body source technology, and namely source electrode is drawn from the device back side.Conventional method corresponding to this technology is the mode injected (being generally P type ion boron) by sinking layer and driven in, and utilizes sinking layer that source electrode is guided to the back side.This method needs long high temperature to drive in could be driven into the injection ion in sinking layer P type high concentration substrate, allows sinking layer and substrate couple together, thus draws source electrode using substrate as the back side.
Fig. 1 is the substrate and epitaxial layer portion structure that utilize back of the body source technology to be formed in existing RF-LDMOS, comprising: the Xia Kuo district 4 of dense doped substrate 1, epitaxial loayer 2, sinking floor 3, sinking floor 3, the Shang Kuo district 5 of dense doped substrate 1.Wherein, dense doped substrate 1 is identical with the doping type in sinking layer 3; The Xia Kuo district 4 of sinking floor 3 and the Shang Kuo district 5 of dense doped substrate 1 be respectively device carry out carrying on the back the high temperature of source technology drive in after Doped ions in corresponding sinking floor 3 and dense doped substrate 1 be diffused into the structure formed in epitaxial loayer 2.
For N-shaped RF-LDMOS, substrate and epitaxial loayer are all the P type boron ions of doping, and sinking layer injects the boron ion that ion is also P type.The dense substrate of P type is that (boron ion source protonatomic mass is little for boron due to doping, diffusion is easy in the semiconductors) under high temperature, so in high-temperature hot process, inevitably upwards spread fast, tie up the space of P type epitaxial loayer, effective epitaxy layer thickness (effective epitaxy layer thickness refers to the epitaxial thickness below the drift region of device) is significantly reduced, and then reduces the puncture voltage of RF-LDMOS.Therefore existing technique is when designing device, often according to the needs of device electric breakdown strength, increases the thickness of epitaxial loayer.But blocked up epitaxy layer thickness, can increase again the difficulty that sinking layer is connected with substrate, simultaneously also can the conducting resistance of increased device, device performance is declined.
Summary of the invention
The invention provides a kind of semiconductor device, manufacture RF-LDMOS in order to solve prior art, it when carrying out sinking floor height temperature and driving in, dense doped substrate expands the effective epitaxy layer thickness caused and reduces, the technical problem that device electric breakdown strength declines.
The embodiment of the present invention provides a kind of semiconductor device, comprising: substrate, be arranged in the epitaxial loayer of described substrate surface and be positioned at the device region of described epitaxial loayer; Wherein:
Be provided with oxide layer buried regions in fixed area in described substrate, described oxide layer buried regions contacts with described epitaxial loayer, and is right against the drift region in described device region;
Be arranged in described epitaxial loayer, except the region just right with described oxide layer buried regions is outside equipped with the first diffusion region, described first diffusion region contacts with described substrate; Impurity conduction type in described first diffusion region is identical with the conduction type of the impurity in described substrate, and its impurity concentration is higher than the impurity concentration in described epitaxial loayer.
Semiconductor device provided by the invention, arranges oxide layer buried regions in fixed area in the substrate, this oxide layer buried regions is contacted with epitaxial loayer, and is right against the drift region be arranged in epitaxial loayer in device region.The program makes semiconductor device when carrying out high temperature injection process, the reduction of effective epitaxy layer thickness under the drift region that the impurity avoided in substrate carries out spreading to the drift region in semiconductor device and causes, thus avoid the decline of the puncture voltage of semiconductor device, improve the performance of device.
Accompanying drawing explanation
Fig. 1 is the substrate and epitaxial loayer generalized section that utilize back of the body source technology to be formed in existing RF-LDMOS;
The generalized section of the semiconductor device that Fig. 2 provides for the embodiment of the present invention;
The generalized section of another semiconductor device that Fig. 3 provides for the embodiment of the present invention;
Fig. 4 a is the schematic diagram of the formation method preparing pad oxide and silicon nitride layer in oxide layer buried regions process in the embodiment of the present invention;
Fig. 4 b prepares the silicon nitride layer structural representation completing photoetching in oxide layer buried regions process in the embodiment of the present invention;
Fig. 4 c prepares the structural representation formed after pad oxide oxidation in oxide layer buried regions process in the embodiment of the present invention;
Fig. 4 d prepares the structural representation formed after silicon nitride layer and pad oxide carry out wet etching in oxide layer buried regions process in the embodiment of the present invention;
Fig. 4 e prepares the structural representation formed after oxide layer buried regions carries out cmp in oxide layer buried regions process in the embodiment of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.For convenience of description, zoomed in or out the size of different layers and region, so size shown in figure and ratio might not represent actual size, also do not reflect the proportionate relationship of size.
The generalized section of the semiconductor device that Fig. 2 provides for the embodiment of the present invention.As shown in Figure 2, this device architecture specifically comprises: substrate 201, be arranged in the epitaxial loayer 202 on substrate 201 surface and be positioned at the device region of described epitaxial loayer, wherein:
Be provided with oxide layer buried regions 206 in fixed area in substrate 201, this oxide layer buried regions contacts with epitaxial loayer, and is right against the drift region in device region;
Be arranged in epitaxial loayer 202, except the region just right with oxide layer buried regions 206 is outside equipped with the first diffusion region 204, this first diffusion region 204 contacts with substrate 201; Impurity conduction type in this first diffusion region 204 is identical with the conduction type of the impurity in substrate 201, and its impurity concentration is higher than the impurity concentration in epitaxial loayer.
Above-mentioned substrate 201 is specifically as follows the semi-conducting material with dense doping, and as materials such as silicon, germanium, gallium nitride, GaAs, mixing impurity can be the impurity of P type for conduction type, as boron.The impurity of N-type that also can be conduction type be, as phosphorus, arsenic, antimony.
During due to the RF-LDMOS of existing technique preparation as N-type substrate, the foreign ion of N-type is larger relative to its atomic weight of p type impurity ion, even if carry out high-temperature process to device in device fabrication process, its heat also can not make N-type ion in substrate layer be diffused in a large number in epitaxial loayer, affects the effective epitaxy layer thickness in epitaxial loayer below position, drift region.The structure type of the semiconductor device therefore shown in the present embodiment is more suitable for substrate and is dense doping and mixes the structure type that impurity is the RF-LDMOS device of p type impurity.
In above-described embodiment, epitaxial loayer 202 is specifically as follows and mixes impurity as boron, phosphorus, arsenic, the material such as silicon, germanium, gallium nitride, GaAs of antimony etc.
In above-described embodiment, the device region being arranged in epitaxial loayer 202 is specially the device area of prepared semiconductor device corresponding to epitaxial loayer 202.It will be appreciated by those skilled in the art that as this device area is for realizing the essential device architecture part of certain semiconductor device function, as comprised the structural regions such as source region, drain region, grid, well region and raceway groove.What pay close attention in the above embodiment of the present invention is position relationship between the locus of drift region between the grid of semiconductor device prepared in this device region and drain region and substrate 201, and is not limited for the particular type of the semiconductor device in this device region and structure.In other words, the semiconductor device in the present embodiment is applicable to the existing semiconductor device of any kind.
In above-described embodiment, be right against the oxide layer buried regions 206 that the position of the drift region of device region is arranged and can be used for stoping whole semiconductor device in high temperature environments in substrate 201, spread in foreign ion epitaxial layers 202 in the region that substrate 201 is corresponding with oxide layer buried regions 206, thus avoid the epitaxy layer thickness that drift region lower epi layer 202 subregion causes because of the impact of the diffusion of foreign ion in substrate 201 and diminish.
In order to more obvious outstanding oxide layer buried regions 206 is at high temperature to the blocking effect that substrate impurity expands, in Fig. 2, illustrate the actual scene that substrate 201 in the case of a high temperature substrate impurity expands.As shown in Figure 2, region 204 is the structure of the formation of in substrate 201, impurity expanding; Comparatively speaking, in the subregion of epitaxial loayer 202 corresponding above oxide layer buried regions 206, due to the stop of oxide layer buried regions 206, cause substrate impurity corresponding to this subregion not on diffuse in epitaxial loayer.
Usually, corresponding under its drift region of semiconductor device epitaxy layer thickness directly affects the size of whole device electric breakdown strength, and (this portion of epi layer thickness is larger, and puncture voltage is larger; Otherwise puncture voltage is less), therefore, the semiconductor device shown in above-described embodiment can effectively be avoided or eliminate the puncture voltage spreading because of substrate impurity the device caused under high temperature and diminish.
Further, it will be appreciated by those skilled in the art that: if for the RF-LDMOS in existing semiconductor device, except all device architectures comprised in above-described embodiment 2, also should comprise in embodiment as shown in Figure 3:
Be arranged in epitaxial loayer 202, be provided with sinking layer 203 in the fixed area away from epitaxial loayer 202 surface of substrate 201, the impurity conduction type in this sinking layer 203 is identical with the conduction type of the impurity in substrate 201;
Be arranged in epitaxial loayer 202, sinking layer 203 periphery be provided with the second diffusion region 205, this second diffusion region 205 respectively with the source region contact of the first diffusion region 204 and semiconductor device; Impurity conduction type in this second diffusion region 205 is identical with the conduction type of the impurity in sinking layer 203, and its impurity concentration is higher than the impurity concentration in epitaxial loayer 202.
In above-described embodiment, the structural region that the second diffusion region 205 is formed after its inner foreign ion is diffused in epitaxial loayer 202 in high temperature environments for sinking layer 203.In actual process engineering, by control temperature and duration, the second diffusion region 205 is contacted respectively with the source area of device region and above-mentioned first diffusion region 204, thus make source area and substrate 201 realize short circuit, and then realize above-mentioned back of the body source technology, draw source electrode from substrate side.
Further, in the semiconductor device shown in the present embodiment, the impurity conduction type of substrate 201 is P type.Concrete realizes by mixing boron impurity ion in substrate 201.
Further, the oxide layer buried regions 206 shown in the present embodiment is the thickness adopting the method for thermal oxidation to generate is the oxide layer of 0.5 ~ 1 micron.
Concrete, the process of preparation oxide layer buried regions 206 can be:
1, substrate generates pad oxide and silicon nitride layer successively;
Fig. 4 a is the schematic diagram of the formation method preparing pad oxide and silicon nitride layer in oxide layer buried regions process in the present embodiment.As shown in fig. 4 a, the method generating pad oxide, for above-mentioned underlayer temperature is carried out high-temperature oxydation between 850 ~ 950 degree, exists to generate thickness
between oxide layer as pad oxide.With low-pressure chemical vapor deposition process at above-mentioned pad oxide surface deposition one deck silicon nitride layer, its thickness is
between.
2, successively photoetching and etching processing are carried out to silicon nitride layer, to remove the silicon nitride layer in fixed area;
Fig. 4 b prepares the silicon nitride layer structural representation completing etching in oxide layer buried regions process in the present embodiment.As shown in Figure 4 b, by existing photoetching and etching technics, successively photoetching and etching are carried out to silicon nitride layer, to get rid of the silicon nitride on silicon nitride layer in fixed area, pad oxide corresponding in this fixed area is come out.
3, the pad oxide surface exposed after the silicon nitride layer removed in fixed area is oxidized, to generate oxide layer buried regions;
Fig. 4 c prepares the structural representation formed after pad oxide oxidation in oxide layer buried regions process in the present embodiment.As illustrated in fig. 4 c, concrete, this process can adopt the process of thermal oxidation to carry out to the pad oxide of above-mentioned exposure the high temperature oxidation process that temperature is 1000 ~ 1200 degree, this part pad oxide ramp is thickeied, to generate thickness is
oxide layer as oxide layer buried regions.
4, wet etching is carried out to silicon nitride layer and pad oxide, to remove silicon nitride layer and pad oxide, retains oxide layer buried regions;
Fig. 4 d prepares the structural representation formed after silicon nitride layer and pad oxide carry out wet etching in oxide layer buried regions process in the present embodiment.As shown in figure 4d, in this process, remove silicon nitride layer and can adopt hot phosphoric acid, the method can not have corrosiveness to oxide layer buried regions; Removal pad oxide layer can adopt hydrofluoric acid, and this process can be lossy to oxide layer buried regions in concrete technology practice, but pad oxide wants too much thin compared to its thickness of oxide layer buried regions, so this loss is negligible.
5, cmp is carried out to the oxide layer buried regions retained, to make the surface of the oxide layer buried regions after grinding and substrate surface at grade; Fig. 4 e prepares the structural representation formed after oxide layer buried regions carries out cmp in oxide layer buried regions process in the present embodiment, as shown in fig 4e, by cmp (ChemicalMechanicalPolishing, CMP) technique, the oxide layer exceeding substrate surface is ground off, makes whole substrate surface recover smooth.So far the generative process of oxide layer buried regions is completed.
Semiconductor device provided by the invention, by arranging oxide layer buried regions in fixed area in the substrate, this oxide layer buried regions is contacted with epitaxial loayer, and the drift region be right against in device region, prevent substrate in high temperature environments, its inner impurity expands to the epitaxial loayer below the drift region in semiconductor device, and then the diminish puncture voltage of the device caused of the effective epitaxy layer thickness avoided because substrate impurity diffusion below the drift region that causes declines, and improves the performance of device.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (9)
1. a semiconductor device, is characterized in that, comprising: substrate, be arranged in the epitaxial loayer of described substrate surface and be positioned at the device region of described epitaxial loayer, wherein:
Be provided with oxide layer buried regions in fixed area in described substrate, described oxide layer buried regions contacts with described epitaxial loayer, and is right against the drift region in described device region;
Be arranged in described epitaxial loayer, except the region just right with described oxide layer buried regions is outside equipped with the first diffusion region, described first diffusion region contacts with described substrate; Impurity conduction type in described first diffusion region is identical with the conduction type of the impurity in described substrate.
2. semiconductor device according to claim 1, described first diffusion region is that in described substrate, impurity is at high temperature diffused in described epitaxial loayer and is formed.
3. semiconductor device according to claim 1, described second diffusion region is that in described sinking layer, impurity is at high temperature diffused in described epitaxial loayer and is formed.
4. the semiconductor device according to any one of claims 1 to 3, is characterized in that, the conduction type of the impurity in described substrate is P type.
5. the semiconductor device according to any one of claims 1 to 3, is characterized in that, the thickness of described first diffusion region is the half of the thickness of described epitaxial loayer.
6. the semiconductor device according to any one of claims 1 to 3, is characterized in that, the thickness of described oxide layer buried regions is 0.5 ~ 1 micron.
7. the semiconductor device according to any one of claims 1 to 3, is characterized in that, described oxide layer buried regions is the oxide layer adopting the method for thermal oxidation to generate.
8. semiconductor device according to claim 1, is characterized in that, described substrate is any one material in silicon, germanium, gallium nitride.
9. semiconductor device according to claim 3, is characterized in that, the impurity in described substrate is boron ion.
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| CN201410232012.7A CN105206666B (en) | 2014-05-28 | 2014-05-28 | Semiconductor devices |
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| CN201410232012.7A CN105206666B (en) | 2014-05-28 | 2014-05-28 | Semiconductor devices |
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| CN105206666B CN105206666B (en) | 2018-09-25 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298475A (en) * | 2015-06-03 | 2017-01-04 | 北大方正集团有限公司 | Reduce the method expanded in Semiconductor substrate |
| CN106997898A (en) * | 2016-01-26 | 2017-08-01 | 北大方正集团有限公司 | Semiconductor structure and preparation method thereof |
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| US20100148254A1 (en) * | 2008-12-12 | 2010-06-17 | Cho Eung Park | Power semiconductor device and method of manufacturing the same |
| CN103545346A (en) * | 2012-07-09 | 2014-01-29 | 上海华虹Nec电子有限公司 | Isolated N-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof |
| CN103606562A (en) * | 2013-09-03 | 2014-02-26 | 北京大学深圳研究院 | Buried N-type layer partial silicon-on-insulator LDMOS transistor |
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2014
- 2014-05-28 CN CN201410232012.7A patent/CN105206666B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100148254A1 (en) * | 2008-12-12 | 2010-06-17 | Cho Eung Park | Power semiconductor device and method of manufacturing the same |
| CN103545346A (en) * | 2012-07-09 | 2014-01-29 | 上海华虹Nec电子有限公司 | Isolated N-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof |
| CN103606562A (en) * | 2013-09-03 | 2014-02-26 | 北京大学深圳研究院 | Buried N-type layer partial silicon-on-insulator LDMOS transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298475A (en) * | 2015-06-03 | 2017-01-04 | 北大方正集团有限公司 | Reduce the method expanded in Semiconductor substrate |
| CN106298475B (en) * | 2015-06-03 | 2020-07-14 | 北大方正集团有限公司 | Method for reducing expansion on semiconductor substrate |
| CN106997898A (en) * | 2016-01-26 | 2017-08-01 | 北大方正集团有限公司 | Semiconductor structure and preparation method thereof |
| CN106997898B (en) * | 2016-01-26 | 2019-10-15 | 北大方正集团有限公司 | Semiconductor structure and preparation method thereof |
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| CN105206666B (en) | 2018-09-25 |
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Effective date of registration: 20220718 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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