CN103579188A - 嵌入式集成电路封装及其制造方法 - Google Patents
嵌入式集成电路封装及其制造方法 Download PDFInfo
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- CN103579188A CN103579188A CN201310303410.9A CN201310303410A CN103579188A CN 103579188 A CN103579188 A CN 103579188A CN 201310303410 A CN201310303410 A CN 201310303410A CN 103579188 A CN103579188 A CN 103579188A
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- encapsulating material
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Abstract
本发明提供了嵌入式集成电路封装及其制造方法,其中所述嵌入式集成电路封装包括:布置在芯片载体之上的至少一个芯片,所述至少一个芯片包括多个芯片接触焊盘;封装材料,在所述芯片载体之上形成并至少部分围绕所述至少一个芯片;贯穿封装材料形成的多个电互连,其中各个电互连电连接到芯片接触焊盘;以及在所述嵌入式集成电路封装的电互连之间形成的结构,其中所述结构增加所述电互连之间的抗爬电性(creepage resistance)。
Description
技术领域
各种实施方式总体涉及嵌入式集成电路封装及嵌入式集成电路封装的制造方法。
背景技术
各种挑战与在晶圆级制造高压外壳相关并存在于半导体功率模块的生产中。通常,有机聚合物材料可用于组件封装,例如,集成电路芯片(IC)的封装。这些有机聚合物材料可呈现有限的介电强度和抗爬电性。这些电气参数可显著损害或降低,特别是在与湿气相结合时。其结果是,例如高电压应用的芯片外壳可具有受限或有限的可用性。
图1A和图1B示出了芯片封装110、120,它们可包括诸如DPAK和D2Pak的晶体管轮廓(TO)外壳封装。可在模制材料104中制造凹槽102以增加抗爬电性。
发明内容
各种实施方式提供了嵌入式集成电路封装,该嵌入式集成电路封装包括:布置在芯片载体之上的至少一个芯片,所述至少一个芯片包括多个芯片接触焊盘;封装材料,在芯片载体之上并至少部分围绕至少一个芯片来形成;多个电互连,贯穿封装材料形成,其中各个电互连电连接到芯片接触焊盘;以及结构,在嵌入式集成电路封装的电互连之间形成,其中结构增加电互连之间的抗爬电性。
附图说明
在附图中,遍及不同视图的相同的参考标号一般指相同的部分。附图不一定按比例绘制,而是重点一般放在示出本发明的原理。在以下描述中,参考以下附图来描述本发明的各种实施方式,其中:
图1A和图1B示出了芯片封装;
图2示出了根据实施方式的用于制造嵌入式集成电路封装的方法;
图3A至图3E示出了根据实施方式的用于制造嵌入式集成电路封装的方法;
图4A到图4C示出了根据实施方式的用于制造嵌入式集成电路封装的方法;
图5A至图5C示出了根据实施方式的用于制造嵌入式集成电路封装的方法;
图6A和图6B示出了根据实施方式的用于制造嵌入式集成电路封装的方法;
图7示出了根据实施方式的嵌入式集成电路封装。
具体实施方式
以下详细描述是指通过图示的方式示出本发明可实行的具体细节和实施方式的附图。
在本文中使用的词语“示例性”的意思是“用作示例、实例或图示”。在本文中描述为“示例性”的任何实施方式或设计不必被解释为比其它实施方式或设计优选或有利。
本文中用于描述在侧面或表面“之上”形成特征(例如层)的词“之上”可用于表示特征(例如层)可以“直接在所指的侧和表面上”形成(例如与其直接接触)的意思。本文中用于描述在侧或表面“之上”形成特征(例如层)的词“之上”可用于表示特征(例如层)可以“间接在所指的侧和表面上”形成(其中在所指的侧或表面和所形成的层之间布置了的一个或多个附加层)的意思。
各种实施方式提供了用于在晶圆级制造高压应用的芯片(例如能够负载大于300V的电压的芯片)外壳的方法。
各种实施方式提供了用于制造高压芯片的封装的方法,其中可在晶圆级实现完整的组件制备。
各种实施方式提供了晶圆级封装和/或芯片封装(例如无引线封装),其中凹槽和/或结构可以在芯片互连之间的封装体中形成。
各种实施方式提供了晶圆级封装和/或芯片封装(例如无引线封装),其中诸如玻璃和/或陶瓷元件的爬电强度材料可以形成以用于增加芯片互连之间的介电强度和/或抗爬电性,例如,芯片互联可形成在凹槽中。
各种实施方式提供了晶圆级封装和/或芯片封装(例如无引线封装),其中例如包括爬电强度材料的一个或多个突起可在芯片互连之间的封装体中形成,其中例如芯片互连之间的组件的抗爬电性可显著增加。
图2示出了用于制造根据实施方式的芯片封装的方法200。
方法200可包括:
将至少一个芯片布置在芯片载体之上,该芯片包括多个芯片接触焊盘(210);
在芯片载体之上并至少部分围绕至少一个芯片来形成封装材料(220);
贯穿封装材料形成多个电互连,从而将各个电互连电连接到芯片接触焊盘(230);以及
在嵌入式集成电路封装的电互连之间形成结构,其中结构增加电互连之间的抗爬电性(240)。
图3A至图3E示出了用于制造根据各种实施方式的嵌入式集成电路封装的方法300。
嵌入式集成电路封装可包括例如晶圆级封装的芯片封装。
如图3A中所示,方法300可包括将至少一个芯片306布置在芯片载体308之上,其中至少一个芯片306可包括多个芯片接触焊盘312。
芯片306可包括例如裸片的半导体芯片,该半导体芯片可包括在晶圆衬底之上形成的一个或多个电子组件。例如晶圆的芯片306可包括例如半导体材料的各种材料。晶圆衬底可包括来自以下材料组的至少一个,该材料组由以下材料组成:硅、锗、III族至V族材料、聚合物、掺杂或未掺杂的硅、半导体化合物材料(例如砷化镓(GaAs)、磷化铟(InP))、四元半导体化合物材料(例如铟镓砷化物(InGaAs))、绝缘体上硅(SOI)。
芯片306可包括功率半导体芯片。例如,芯片306可能够负载300V至高达约10000V之间的电压。
芯片306可包括多个芯片接触焊盘312,例如前侧接触焊盘312F1、312F2和至少一个后侧接触焊盘312B。前侧接触焊盘312F1、312F2可形成在第一芯片侧314(例如顶侧,例如上侧)之上。至少一个后侧接触焊盘312B可形成在第二芯片侧316(例如后侧,例如底侧)之上。多个芯片接触焊盘312可包括导电焊盘,导电焊盘可包括来自以下材料组的至少一种材料、元素或合金,该组由以下材料组成:铜、铝、银、锡、金、钯、锌、镍、铁。
芯片前侧也可被称为“第一芯片侧”、“芯片顶侧”或“芯片上侧”,这些在下文可互换使用。芯片后侧也可被称为“第二芯片侧”、“芯片底侧”或“芯片下侧”,这些在下文可互换使用。
芯片306可被布置在芯片载体308之上,例如芯片306可经由第二芯片侧316(例如芯片后侧)粘附、或结合、或固定到芯片载体308。芯片306可包括在第二芯片后侧316上形成的芯片后侧接触焊盘312B,即芯片后侧金属化;且芯片后侧接触焊盘312B可例如经由导电粘合剂、焊接或烧结来粘附、或结合、或固定到芯片载体308。
芯片载体308可包括导电引线框。因此,可在后侧接触焊盘312B和芯片载体308之间形成电连接。
应理解,为了简洁起见,仅对于单个芯片306描述各种实施方式。然而应理解,各种实施方式可应用于制造包括多个芯片的嵌入式集成电路封装,例如批量处理多于一个的芯片(例如306、306A、306B)。换言之,根据方法300集成电路封装(例如芯片封装)的制造可应用于批量处理晶圆级芯片封装,在该晶圆级芯片封装中多个芯片根据方法300被封装在例如公共连续芯片载体308之上,并在处理的最后阶段被个别化。
封装材料304可形成在芯片载体308之上并至少部分围绕芯片306。封装材料304一般可被沉积以封装和/或电绝缘芯片306。封装材料304可在芯片载体308上形成,例如在芯片载体顶表面313上和芯片306的一个或多个侧壁318上形成。
在图3A的310中,封装材料304可基本上(例如基本上完全)覆盖第一芯片侧314。随后,多个电互连326可贯穿封装材料304形成。各个电互连326可电连接到芯片接触焊盘312。
封装材料304可以是电绝缘的,并可将多个电互连326彼此电绝缘。根据某些实施方式,封装材料304可包括可例如使用模制方法来沉积的模制化合物。根据其它实施方式,封装材料304可通过层压沉积。因此,封装材料304可包括电绝缘层压材料,例如一个或多个层压板。封装材料304可包括电绝缘层压材料,该电绝缘层压材料包括来自以下材料组的至少一个,所述材料组由以下材料组成:填充或未填充的环氧树脂、预浸渍的复合纤维、增强纤维、层压材料、模制材料、热固性材料、热塑性材料、填料颗粒、纤维增强层压材料、纤维增强聚合物层压材料、具有填料颗粒的纤维增强聚合物层压材料。
多个电互连326可通过至少部分地填充也被称为通孔的多个孔328(例如328F1、328F2、328B)来形成。多个孔328(例如328F1、328F2、328B)可在封装材料304中形成,从而各个孔328使电连接到芯片接触焊盘312的电接触露出。例如,孔328B可露出芯片载体308的一部分(例如,芯片载体308的顶表面322)。孔328F1和328F2可使芯片接触焊盘312F1和312F2从封装材料露出(例如外露)。
多个电互连326可形成(例如电镀)在孔328中。例如在孔328F1中的第一电互连326F1可电连接到形成在第一芯片侧上的第一芯片接触焊盘312F1;例如在孔328F2中的第二电互连326F2可电连接到形成在第一芯片侧314上的第二芯片接触焊盘312F2;并且例如在孔328B中的第三电互连326B可经由芯片载体308电连接到形成在第二芯片侧316上的第三芯片接触焊盘312B,其中第二芯片侧316可形成在芯片载体308上。
多个电互连326可形成在芯片306和芯片载体308中的至少一个之上。例如,第一电互连326F1可形成在芯片接触焊盘312F1之上,例如直接在芯片接触焊盘312F1之上;而第二电互连326F2可形成在芯片接触焊盘312F2之上,例如直接在芯片接触焊盘312F2之上。因此,第一电互连326F1和第二电互连326F2可形成在芯片306之上。第三电互连326B可形成在芯片载体308的顶侧322之上,并直接连接到芯片载体308。
多个电互连326可例如通过用导电材料填充(诸如电镀,例如伽伐尼电镀(galvanic electroplating))孔328来形成。多个电互连326可包括来自以下材料组的至少一种材料、元件或合金,该组由以下材料组成:铜、铝、银、锡、金、钯、锌、镍、铁。应理解,最终的嵌入式集成电路封装和/或芯片封装可因此包括封装中不存在配线接合的无引线封装。然而应理解,多个电互连326沉积可不限于例如伽伐尼电镀的电镀,并且可包括例如溅射、蒸发、无电镀的沉积方法。
在图3B的320中,结构332可形成在嵌入式集成电路封装的电互连326之间,其中结构332可增加电互连326之间的抗爬电性。
如图3B中所示,结构332可包括形成在封装材料304中的腔室334。结构332(例如结构332的腔室334)可增加沿着封装材料304的表面测量的电互连326之间的爬电距离。腔室334可形成在封装材料304中(例如在层压片中的凸块中),和/或例如通过封装材料304的激光结构化或光蚀刻来形成。
图3B示出根据实施方式的嵌入式集成电路封装360。嵌入式集成电路封装360可包括:布置在芯片载体308之上的至少一个芯片306,该至少一个芯片306包括多个芯片接触焊盘312;形成在芯片载体308之上并至少部分围绕至少一个芯片306的封装材料304;贯穿封装材料304形成的多个电互连326,其中各个电互连326可电连接到芯片接触焊盘312;以及形成在嵌入式集成电路封装360的电互连326之间的结构332,其中结构332可增加电互连326之间的抗爬电性。结构332可形成在芯片306和芯片载体308中的至少一个之上。
应理解,爬电距离可被定义为在绝缘材料(例如封装材料304)的表面上的两个导电元件之间(例如328F1和328F2之间;或328F1和328B之间)的最短距离。应理解,在328F1和328B之间施加的电压比在328F1和328F2之间施加的电压高很多,其结果是,重要的可以是在328F1和328B之间的爬电距离足够大以防止和/或避免漏电起痕(tracking)。
图3C至图3E示出了根据各种实施方式的在具有或不具有结构332的情况下沿着封装材料304的表面测量的电互连326之间的爬电距离。如图3C中所示,沿着封装材料304的表面测量的爬电距离(不具有结构332)可以是Dc。
图3D示出了结构332(例如腔室334)在封装材料304的表面338的形成。测量沿着封装材料304的表面测量的爬电距离可增至Dc2。Dc2可比Dc(具有结构332)大近似两倍的从封装材料表面338起的腔室深度t。
如图3E中所示,结构332不仅可包括形成在电互连326之间的唯一腔室334,而且可包括形成在电互连之间的多个腔室332,例如多于一个的腔室334。可实现更大的爬电距离Dc3。
图4示出了根据实施方式的嵌入式集成电路封装460。嵌入式集成电路封装460可根据方法400来制造,其中除了关于方法300来描述的一个或多个或全部的处理之外,方法400可进一步包括在芯片306和芯片载体308中的至少一个之上形成另外的材料436,另外的材料436具有比封装材料304更高的介电强度和/或更高的相对漏电起痕指数(CTI)。可根据基于IEC60112标准的测试方法,通过用于确定固体绝缘材料的检验(proof)和相对漏电起痕指数的方法来测量相对漏电起痕指数。CTI可测量绝缘材料的表面上的电击穿的趋势。具有较大CTI的绝缘材料较不可能经历跨材料表面的传导电荷的泄漏。另外的材料436例如可呈现大于300℃的高温稳定性、高的介电强度、大的抗爬电性、稳定的介电强度和爬电强度、独立于外部条件(例如湿度,例如温度)。因此,更高的元件可靠性可被实现且可适用于大范围的电子组件。
另外的材料436可包括电绝缘材料。另外的材料436可包括来自以下材料组的至少一种材料,该材料组由玻璃、陶瓷组成。另外的材料436可包括比封装材料304更高的温度稳定性。另外的材料436可包括比封装材料304更高的介电强度。另外的材料436可包括比封装材料304更大的抗爬电性。
另外的材料436可形成在电互连312之间。另外的材料436可至少部分地填充腔室334,例如腔室334。例如,另外的材料436可基本填满腔室334(如嵌入式集成电路封装460中所示)。因此,嵌入式集成电路封装460可在电互连326之间包括一个或一个陶瓷和/或玻璃填充的凹槽。如图4B的嵌入式集成电路封装470中所示,根据另一实施方式,另外的材料436可形成另外的材料436从封装材料304的突起439。
如图4C中所示,突起439可具有从封装材料顶表面338延伸约500nm至约1000μm的高度p。此外,突起439可将在电互连326之间沿着电绝缘材料的表面测量的爬电距离增加至Dc4。应理解,电互连326之间的电绝缘材料可包括封装材料304和另外的材料436中的至少一部分。因此,Dc4可比Dc(不具有结构332)大近似突起部分高度p的两倍。此外,在腔室334中的另外的材料436的使用(例如电互连326之间的玻璃或陶瓷填充的凹槽或腔室334)可进一步提高电互连326之间的整体抗爬电性,其中另外的材料436可具有比封装材料304更高的介电强度和/或更高的相对漏电起痕指数。
图5A至图5C示出了用于制造根据一个实施方式的嵌入式集成电路封装的方法500。方法500可包括已经关于方法300和400来描述的一个或多个特征。
如图5A中所示,方法500可包括在芯片载体308之上布置至少一个芯片306,其中至少一个芯片306可包括多个芯片接触焊盘312。这可根据方法300所描述的来实现(图3A)。
如关于方法300来描述的,封装材料304可形成在芯片载体308之上并且至少部分围绕芯片306。封装材料304可包括电绝缘层压材料并可通过如根据方法300所描述的层压来沉积,例如,可在金属芯片载体304上实现集成电路芯片306的单侧层压。然而,对于方法500,封装材料304可基本上沉积在芯片306的一个或多个侧壁318上,并且可选地不在第一芯片侧314上。随后,芯片306可由封闭的结构化隔离材料覆盖,即在封装体(encapsulation mass)304之上的另外的材料536。
在准备形成电互连326时,可在封装材料304中形成多个孔328(例如328B),各个孔328从而露出电连接到芯片接触焊盘312的电接触。例如,孔328B可露出芯片载体308的一部分,例如芯片载体308的顶表面322。
随后,在520中,另外的材料536(类似于另外的材料436)可在封装材料304之上形成,另外的材料536包括玻璃和/或陶瓷和/或高CTI电绝缘材料。
此外,包括结构化玻璃和/或陶瓷区域的另外的材料536可被进一步结构化,其中可在另外的材料536中形成一个或多个孔528。例如,可在孔328B之上形成孔528B。此外,孔528F1和528F2可将芯片接触焊盘312F1和312F2从封装材料露出(例如外露)。
应理解,处理510和520可根据处理要求来合并。例如,在封装材料304和另外的材料536沉积之后,例如在另外的材料536和封装材料304中的孔528可如以上根据各种实施方式描述的在分开的处理中形成,或可在单个处理中形成。
随后,在530中,多个电互连326可以贯穿封装材料304和另外的材料536形成。各个电互连326可电连接到芯片接触焊盘312。多个电互连326可如根据方法300所描述的形成(例如电镀)并且可如根据320中的方法300所描述的电连接到芯片306和/或芯片载体308。例如,孔328、528可被填充(例如使用单步骤电镀或双步骤电镀处理来电镀)。例如,在形成另外的材料536(此后在孔528中电镀)之前,可首先在孔328中进行电镀(双步骤电镀);或在另外的材料536中形成孔528之后,可在单步骤中在孔328、528中进行电镀(单步骤电镀)。
应理解,如图5C中所示,另外的材料536可形成在电互连326之间。图5B示出了根据实施方式的嵌入式集成电路封装560。嵌入式集成电路封装560可包括:布置在芯片载体308之上的至少一个芯片306,该至少一个芯片306包括多个芯片接触焊盘312;封装材料304,在芯片载体308之上形成并至少部分围绕至少一个芯片306;贯穿封装材料304形成的多个电互连326,其中各个电互连326可电连接到芯片接触焊盘312;以及在嵌入式集成电路封装360的电互连之间形成的结构332,其中结构332可增加电互连326之间的抗爬电性。结构332可形成在芯片306和芯片载体308中的至少一个之上。
如图5C中所示,结构332可包括在芯片306之上(例如在第一芯片侧314和封装材料304之上)形成的另外的材料536。包括另外的材料536的结构332可在电互连326之间形成。另外的材料536比封装材料304更高的CTI可增加电互连326之间的抗爬电性。
图6A示出根据实施方式的嵌入式集成电路封装660。嵌入式集成电路封装660可包括已经根据嵌入式集成电路封装560描述的一个或多个或全部特征。然而,除此之外结构332可进一步包括在另外的材料536中形成的腔室334。
如图6B中所示,结构332的腔室334可将沿着另外的材料536的表面测量的电互连328之间的爬电距离增加至Dc5。此外,具有比封装材料30更高的介电强度和/或更高的相对漏电起痕指数(CTI)的另外的材料536可增加在电互连328之间的整体抗爬电性。
图7示出了根据实施方式的嵌入式集成电路封装760。嵌入式集成电路封装760可包括:布置在芯片载体308之上的至少一个芯片306,该至少一个芯片306包括多个芯片接触焊盘312;封装材料304,在芯片载体308之上形成并至少部分围绕至少一个芯片306;贯穿封装材料304形成的多个电互连,其中各个电互连326可电连接到芯片接触焊盘312;以及在嵌入式集成电路封装360的电互连之间形成的结构332,其中结构332可增加电互连326之间的抗爬电性。
各种实施方式提供了一种嵌入式集成电路封装,该嵌入式集成电路封装包括:布置在芯片载体之上的至少一个芯片,该至少一个芯片包括多个芯片接触焊盘;封装材料,形成在芯片载体之上并至少部分围绕至少一个芯片;贯穿封装材料形成的多个电互连,其中各个电互连电连接到芯片接触焊盘;以及形成在嵌入式集成电路封装的电互连之间的结构,其中结构增加电互连之间的抗爬电性。
根据实施方式,至少一个芯片包括功率半导体芯片。
根据实施方式,芯片载体包括导电引线框。
根据实施方式,多个芯片接触焊盘包括导电焊盘。
根据实施方式,封装材料包括电绝缘材料。
根据实施方式,封装材料使多个电互连彼此电绝缘。
根据实施方式,封装材料形成在芯片之上以及至少一个芯片的一个或多个侧壁上。
根据实施方式,多个电互连形成在至少一个芯片和芯片载体中的至少一个之上。
根据实施方式,封装材料包括电绝缘层压材料。
根据实施方式,封装材料包括电绝缘层压材料,该电绝缘层压材料包括来自以下材料组中的至少一种,该组由以下材料组成:填充或未填充的环氧树脂、预浸渍的复合纤维、增强纤维、层压材料、模制材料、热固性材料、热塑性材料、填料颗粒、纤维增强层压材料、纤维增强聚合物层压材料、具有填料颗粒的纤维增强聚合物层压材料。
根据实施方式,结构增加沿着所述封装材料的表面测量的电互连之间的爬电距离。
根据实施方式,结构包括在封装材料中形成的腔室。
根据实施方式,结构包括形成在芯片和芯片载体中的至少一个之上的另外的材料,该另外的材料具有比封装材料高的介电强度。
根据实施方式,结构包括在电互连之间的封装材料中形成的腔室,并且其中另外的材料至少部分地填充腔室,该另外的材料具有比封装材料高的介电强度。
根据实施方式,结构包括在电互连之间的封装材料中形成的腔室,并且其中另外的材料至少部分地填充腔室,该另外的材料包括来自以下材料组的至少一种材料,该材料组由玻璃、陶瓷组成。
根据实施方式,结构包括在电互连之间的封装材料中形成的腔室,并且其中另外的材料至少部分地填充腔室,从而形成另外的材料从封装材料的突起。
根据实施方式,结构形成在芯片和芯片载体中的至少一个之上。
根据实施方式,多个电互连沉积在形成在封装材料中的一个或多个孔中,各个孔露出电连接到芯片接触焊盘的电接触。
根据实施方式,多个电互连沉积在形成在封装材料中的一个或多个孔中,各个孔从封装材料露出接触焊盘。
根据实施方式,第一电互连电连接到在第一芯片侧上形成的第一芯片接触焊盘;而第二电互连电连接到在第一芯片侧或第二芯片侧上形成的第二芯片接触焊盘,其中第二芯片侧在芯片载体上形成。
根据实施方式,嵌入式集成电路封装还包括:电连接到在第一芯片侧上形成的第一芯片接触焊盘的第一电互连;电连接到在第一芯片侧上形成的第二芯片接触焊盘的第二电互连;以及经由芯片载体电连接到在第二芯片侧上形成的第三芯片接触焊盘的第三电互连,其中第二芯片侧在芯片载体上形成。
根据实施方式,嵌入式集成电路封装还包括晶圆级封装。
各种实施方式提供了一种用于制造嵌入式集成电路封装的方法,该方法包括:将芯片布置在芯片载体之上,芯片包括多个芯片接触焊盘;在芯片载体之上并至少部分围绕芯片来形成封装材料;贯穿封装材料形成多个电互连,从而使各个电互连电连接到芯片接触焊盘;以及在嵌入式集成电路封装的电互连之间形成结构,其中结构增加电互连之间的抗爬电性。
根据实施方式,将芯片布置在芯片载体之上包括将芯片焊接在芯片载体上。
在所述芯片载体之上并至少部分围绕所述芯片来形成封装材料包括使所述封装材料层压在所述芯片和至少一部分所述芯片载体之上。
根据实施方式,贯穿封装材料形成多个电互连包括通过伽伐尼电镀来沉积电互连。
虽然本发明已经参照特定实施方式来具体示出和描述,但是本领域中的技术人员应理解,在不脱离如由所附权利要求定义的本发明的实质和范围的情况下,可在形式和细节上进行各种改变。因此,本发明的范围由所附权利要求表示,且因此旨在涵盖包含在权利要求的等同物的含义和范围内的所有变化。
Claims (25)
1.一种嵌入式封装,包括:
至少一个芯片,布置在芯片载体之上,所述至少一个芯片包括多个芯片接触焊盘;
封装材料,在所述芯片载体之上并至少部分围绕所述至少一个芯片来形成;
多个电互连,贯穿所述封装材料形成,其中各个电互连电连接到芯片接触焊盘;以及
结构,在所述嵌入式集成电路封装的电互连之间形成,其中所述结构增加所述电互连之间的抗爬电性。
2.根据权利要求1所述的嵌入式集成电路封装,
其中,所述至少一个芯片包括功率半导体芯片。
3.根据权利要求1所述的嵌入式集成电路封装,
其中,所述芯片载体包括导电引线框。
4.根据权利要求1所述的嵌入式集成电路封装,
其中,所述多个芯片接触焊盘包括导电焊盘。
5.根据权利要求1所述的嵌入式集成电路封装,
其中,所述封装材料包括电绝缘材料。
6.根据权利要求1所述的嵌入式集成电路封装,
其中,所述封装材料使所述多个电互连彼此电绝缘。
7.根据权利要求1所述的嵌入式集成电路封装,
其中,所述封装材料在所述芯片之上以及所述至少一个芯片的一个或多个侧壁上形成。
8.根据权利要求1所述的嵌入式集成电路封装,
其中,所述多个电互连在所述至少一个芯片和所述芯片载体中的至少一个之上形成。
9.根据权利要求1所述的嵌入式集成电路封装,
其中,所述封装材料包括电绝缘层压材料。
10.根据权利要求1所述的嵌入式集成电路封装,
其中,所述封装材料包括电绝缘层压材料,所述电绝缘层压材料包括来自以下材料组中的至少一种,所述组由以下材料组成:填充或未填充的环氧树脂、预浸渍的复合纤维、增强纤维、层压材料、模制材料、热固性材料、热塑性材料、填料颗粒、纤维增强层压材料、纤维增强聚合物层压材料、具有填料颗粒的纤维增强聚合物层压材料。
11.根据权利要求1所述的嵌入式集成电路封装,
其中,所述结构增加沿着所述封装材料的表面测量的所述电互连之间的爬电距离。
12.根据权利要求1所述的嵌入式集成电路封装,
其中,所述结构包括在所述封装材料中形成的腔室。
13.根据权利要求1所述的嵌入式集成电路封装,
其中,所述结构包括
另外的材料,在所述芯片和所述芯片载体中的至少一个之上形成,所述另外的材料具有比所述封装材料高的介电强度。
14.根据权利要求1所述的嵌入式集成电路封装,
其中,所述结构包括
腔室,在所述电互连之间的所述封装材料中形成,并且
其中,另外的材料至少部分地填充所述腔室,所述另外的材料具有比所述封装材料高的介电强度。
15.根据权利要求1所述的嵌入式集成电路封装,
其中,所述结构包括
腔室,在所述电互连之间的所述封装材料中形成,并且
其中,另外的材料至少部分地填充所述腔室,所述另外的材料包括来自以下材料组的至少一种材料,所述材料组由以下材料组成:玻璃、陶瓷。
16.根据权利要求1所述的嵌入式集成电路封装,
其中,所述结构包括
腔室,在所述电互连之间的所述封装材料中形成,并且
其中,另外的材料至少部分地填充所述腔室,从而形成所述另外的材料从所述封装材料的突起。
17.根据权利要求1所述的嵌入式集成电路封装,
其中,所述结构在所述芯片和所述芯片载体中的至少一个之上形成。
18.根据权利要求1所述的嵌入式集成电路封装,
其中,所述多个电互连沉积在形成在所述封装材料中的一个或多个孔中,各个孔使电连接到芯片接触焊盘的电接触露出。
19.根据权利要求1所述的嵌入式集成电路封装,
其中,第一电互连电连接到在第一芯片侧上形成的第一芯片接触焊盘;并且
其中,第二电互连电连接到在所述第一芯片侧或第二芯片侧上形成的第二芯片接触焊盘,其中所述第二芯片侧在所述芯片载体上形成。
20.根据权利要求1所述的嵌入式集成电路封装,还包括
第一电互连,电连接到在第一芯片侧上形成的第一芯片接触焊盘;
第二电互连,电连接到在所述第一芯片侧上形成的第二芯片接触焊盘;以及
第三电互连,经由所述芯片载体电连接到在第二芯片侧上形成的第三芯片接触焊盘,其中所述第二芯片侧在所述芯片载体上形成。
21.根据权利要求1所述的嵌入式集成电路封装,
其中,所述嵌入式集成电路封装包括晶圆级封装。
22.一种用于制造嵌入式集成电路封装的方法,所述方法包括:
将芯片布置在芯片载体之上,所述芯片包括多个芯片接触焊盘;
在所述芯片载体之上并至少部分围绕所述芯片来形成封装材料;
贯穿所述封装材料形成多个电互连,从而将各个电互连电连接到芯片接触焊盘;以及
在所述嵌入式集成电路封装的电互连之间形成结构,其中所述结构增加所述电互连之间的抗爬电性。
23.根据权利要求22所述的方法,其中,
将芯片布置在芯片载体之上包括将芯片焊接在芯片载体上。
24.根据权利要求22所述的方法,其中,
在所述芯片载体之上并至少部分围绕所述芯片来形成封装材料包括使所述封装材料层压在所述芯片和至少一部分的所述芯片载体之上。
25.根据权利要求21所述的方法,其中,
贯穿所述封装材料形成多个电互连包括通过伽伐尼电镀来沉积所述电互连。
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CN109326571A (zh) * | 2018-09-26 | 2019-02-12 | 矽力杰半导体技术(杭州)有限公司 | 芯片封装组件及其制造方法 |
CN112216666A (zh) * | 2019-07-11 | 2021-01-12 | 珠海格力电器股份有限公司 | 元器件电性连接方法及芯片封装 |
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US8648456B1 (en) * | 2012-07-18 | 2014-02-11 | Infineon Technologies Ag | Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package |
US9960099B2 (en) * | 2013-11-11 | 2018-05-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thermally conductive molding compound structure for heat dissipation in semiconductor packages |
US10510707B2 (en) * | 2013-11-11 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thermally conductive molding compound structure for heat dissipation in semiconductor packages |
JP6125984B2 (ja) * | 2013-12-11 | 2017-05-10 | トヨタ自動車株式会社 | 半導体装置 |
US10685904B2 (en) | 2014-11-21 | 2020-06-16 | Delta Electronics, Inc. | Packaging device and manufacturing method thereof |
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US11621204B2 (en) | 2021-02-17 | 2023-04-04 | Infineon Technologies Ag | Molded semiconductor module having a mold step for increasing creepage distance |
EP4187586A1 (en) * | 2021-11-24 | 2023-05-31 | Hitachi Energy Switzerland AG | Assembly for a power module, power module and method for producing an assembly for a power module |
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CN103579188B (zh) | 2016-12-28 |
US20140151862A1 (en) | 2014-06-05 |
US9082767B2 (en) | 2015-07-14 |
DE102013107593A1 (de) | 2014-01-23 |
US8648456B1 (en) | 2014-02-11 |
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