CN107958844A - 封装结构及其制作方法 - Google Patents

封装结构及其制作方法 Download PDF

Info

Publication number
CN107958844A
CN107958844A CN201610969569.8A CN201610969569A CN107958844A CN 107958844 A CN107958844 A CN 107958844A CN 201610969569 A CN201610969569 A CN 201610969569A CN 107958844 A CN107958844 A CN 107958844A
Authority
CN
China
Prior art keywords
dielectric material
convex block
circuit element
conductive
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610969569.8A
Other languages
English (en)
Other versions
CN107958844B (zh
Inventor
许诗滨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Phoenix Pioneer Technology Co Ltd
Original Assignee
Phoenix and Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix and Corp filed Critical Phoenix and Corp
Publication of CN107958844A publication Critical patent/CN107958844A/zh
Application granted granted Critical
Publication of CN107958844B publication Critical patent/CN107958844B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32237—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明揭示一种封装结构及其制作方法。该封装结构包括：一导电图案层，包含一凸块区及一线路区，其中该凸块区包含复数个导电凸块及一围绕该复数个导电凸块的第一介电材料，该线路区包含复数个第一导电线路及一围绕并覆盖该复数个第一导电线路的第二介电材料；一电路元件，具有复数个连接端并设置于该凸块区上，其中该复数个连接端与该复数个导电凸块彼此对应；一绝缘阻隔胶，其形成于该第二介电材料上并围绕该电路元件的侧边下缘；以及一第三介电材料，包覆该电路元件及该线路区。

Description

封装结构及其制作方法
技术领域
本发明涉及一种适用于大面积矩形面板形式制造的封装结构以及其制作方法。
背景技术
新一代电子产品不仅追求轻薄短小的高密度，更有朝向高功率发展的趋势；因此，积体电路(Integrated Circuit，简称IC)技术及其后端的晶片封装技术也随之进展，以符合此新一代电子产品的效能规格。
目前晶圆尺寸为基底的封装方式可参考图1来说明，先在晶圆承载板(Wafercarrier)11上形成粘接层18，如图1A所示；接着将半导体晶片13或电子元件15的接脚16朝下并凭借该粘接层18而粘贴于该晶圆承载板11，再以铸模技术使铸模化合物12包覆及封装该半导体晶片13或电子元件15，如图1B所示；在去除该晶圆承载板11及该粘接层18之后，将该半导体晶片13、该电子元件15、及该铸模化合物12的组合结构20上下翻转，使得重布线层(ReDistribution Layer，简称RDL)17可制作于该组合结构20的上表面21的上，如图1C所示。
倘若欲以一般现有的微影蚀刻技术制作细线路间距(fine pitch)的重布线层17于该组合结构20的上表面21上，则该上表面21必须能提供很高的平坦度。然而，为了达成上述对该上表面21平坦度的要求，该晶圆承载板11及该粘接层18必须采用较为昂贵者，且该半导体晶片13及该电子元件15必须以精准而慢速的方式粘贴于该粘接层18；这不利于大面积矩形面板(Panel)形式的制造，并将会提高封装元件的制造成本。因此，有必要发展新的封装基板元件技术，以对治及改善上述的问题。
发明内容
为改善上述问题及达成超细线路间距和超细凸块间距的目的，本发明提供一种封装结构。
以上说明对本发明而言只是说明性的，而非限制性的，本领域普通技术人员理解，在不脱离本申请所限定的精神和范围的情况下，可作出许多修改、变化或等效，但都将落入本发明的保护范围之内。
一种封装结构，其包含：一导电图案层，包含一凸块区及一线路区，其中该凸块区包含复数个导电凸块及一围绕该复数个导电凸块的第一介电材料，该线路区包含复数个导电线路及一围绕并覆盖该复数个导电线路的第二介电材料；一电路元件，具有复数个连接端并设置于该凸块区上，其中该复数个连接端与该复数个导电凸块彼此对应；一绝缘阻隔胶，其形成于该第二介电材料上并围绕该电路元件的侧边下缘；以及一第三介电材料，包覆该电路元件及该线路区。
在一实施例中，该导电图案层还包含一阻隔框，其设置于该凸块区与该线路区之间，且该阻隔框具有一线宽，使得该电路元件的边缘位于该阻隔框的线宽范围内。
在一实施例中，该阻隔框的组成材质为金属或有机绝缘材料。
在一实施例中，还包含复数个第一导电柱状物，其形成于该复数个第一导电线路上并被该第三介电材料所包覆。
在一实施例中，该电路元件为半导体晶片或电子元件。
在一实施例中，还包含：
一导柱层，包含复数个第二金属柱状物及一围绕该复数个第二金属柱状物的第四介电材料，该导柱层形成于该导电图案层下方；以及
一重布线层，包含复数个第二导电线路以及一围绕该复数个第二导电线路的第五介电材料，该重布线层形成于该导柱层下方。
根据本发明另一实施例提供一种封装结构的制作方法，其步骤包含：形成一导电图案层于一承载板上，其中该导电图案层包含一凸块区及一线路区，该凸块区包含复数个导电凸块，且该线路区包含复数个导电线路；形成一第一第二介电材料，其包覆该复数个导电线路；设置一具有复数个连接端的电路元件于该凸块区上，使得该复数个连接端与该复数个导电凸块彼此对应；形成一绝缘阻隔胶于该第一第二介电材料上并围绕该电路元件的侧边下缘；形成一第二第三介电材料于该承载板上，使其包覆该电路元件及该线路区；移除该承载板，并形成一第四介电材料于该导电图案层及该电路元件上，使其围绕该复数个导电凸块及该电路元件的该复数个连接端；以及形成复数个金属柱状物于该第四介电材料中，使其连接该复数个导电凸块及该复数个导电线路。
在一实施例中，在步骤(D)之前还包含：(C1)在该复数个导电线路上形成复 数个导电柱状物。
在一实施例中，该电路元件为半导体晶片或电子元件。
根据本发明另一实施例提供一种封装结构的制作方法，其步骤包含：形成一导电图案层于一承载板上，其中该导电图案层包含一凸块区、一围绕该凸块区的金属阻隔框、及一围绕该导电阻隔框的线路区，该凸块区包含复数个导电凸块，该线路区包含复数个导电线路，且该金属阻隔框具有一线宽；形成一第二介电材料，其包覆该金属阻隔框及该复数个导电线路；设置一具有复数个连接端的电路元件于该凸块区及该金属阻隔框上，使得该复数个连接端与该复数个导电凸块彼此对应，且该电路元件的边缘位于该金属阻隔框的线宽范围内；形成一绝缘阻隔胶于该第二介电材料上并围绕该电路元件的侧边下缘；形成一第三介电材料于该承载板上，使其包覆该电路元件及该线路区；移除该承载板，并形成一第四介电材料于该导电图案层及该电路元件上，使其围绕该复数个导电凸块及该电路元件的该复数个连接端；以及形成复数个金属柱状物于该第四介电材料中，使其连接该复数个导电凸块及该复数个导电线路。
在一实施例中，在步骤(D)之前还包含：(C1)在该复数个导电线路上形成复数个导电柱状物。
在一实施例中，该电路元件为半导体晶片或电子元件。
与现有技术相比较，本发明具有的有益效果是：可达成超细线路间距和超细凸块间距的目的。
附图说明
图1A～图1C为现有晶圆级封装结构的制程步骤的对应剖面图。
图2A为根据本发明第一实施例的封装结构的剖面示意图。
图2B为根据本发明第三实施例的封装结构的剖面示意图。
图3A为第一实施例导电图案层在X-Y平面的剖面图。
图3B为第三实施例导电图案层在X-Y平面的剖面图。
图4A为根据本发明第二实施例的封装结构的剖面示意图。
图4B为根据本发明第四实施例的封装结构的剖面示意图。
图5A～图5B为本发明封装结构制程步骤的一的封装基板剖面图。
图6A～图6D为本发明封装结构制程步骤的一的封装基板剖面图。
图7A～图7B为本发明封装结构制程步骤的一的封装基板剖面图。
图8A～图8B为本发明封装结构制程步骤的一的封装基板剖面图。
图9为根据本发明第五实施例的封装结构的剖面示意图。
附图标记说明：100、200、300、400、500封装结构；110承载板；120导电图案层；121～126、520导电线路；130阻隔框；135～137导电凸块；230凸块区；330线路区；140绝缘阻隔胶；150、500电路元件；151～153、551～552连接端；127、138、160、178、188介电材料；170导柱层；171～177金属柱状物；180重布线层；181～187导电线路；191～194金属导柱。
具体实施方式
为使对本发明的特征、目的及功能有更还的认知与了解，兹配合图式详细说明本发明的实施例如后。在所有的说明书及图示中，将采用相同的元件编号以指定相同或类似的元件。
在各个实施例的说明中，当一元素被描述是在另一元素的「上方/上」或「下方/下」，系指直接地或间接地在该另一元素的上或的下的情况，其可能包含设置于其间的其他元素；所谓的「直接地」系指其间并未设置其他中介元素。「上方/上」或「下方/下」等的描述系以图式为基准进行说明，但也包含其他可能的方向转变。所谓的「第一」、「第二」、及「第三」系用以描述不同的元素，这些元素并不因为此类谓辞而受到限制。为了说明上的便利和明确，图式中各元素的厚度或尺寸，系以夸张或省略或概略的方式表示，且各元素的尺寸并未完全为其实际的尺寸。
图2A为根据本发明第一实施例的封装结构100的剖面示意图。该封装结构100包含：一重布线层180、一导柱层170、一导电图案层120、一电路元件150、一绝缘阻隔胶140以及一介电材料160；其中，该导电图案层120的平面图可参考图3A，而区分成凸块区230及线路区330等二个部分，其中该线路区330为围绕该凸块区230的外环区域。也就是说，图2A代表本实施例封装结构100在X-Z平面的剖面图，Z方向朝上，因此该重布线层180位于该封装结构100的最下层，而该导柱层170、该导电图案层120、该电路元件150及该介电材料160则依序向上堆叠成层状结构。此外，图3A代表本实施例的该导电图案层120在X-Y平面的剖面图，该凸块区230基本上是方框或矩形框，其框外为线路区330。该绝缘阻隔胶140形成于该线路区330上并围绕该电路元件150的侧边下缘。本发明对该凸块区230的外框形状不加以限制，端视后续将要放置的电路元件150的外形而定，使得该电路元件150的边缘能落在该线路区330的范围内，则该电路元件150与该线路区330能将该凸块区230包覆起来。在此，该绝缘阻隔胶140的组成材质可以是树脂材料，而以点胶(Dispensing)或薄膜型材料真空贴合技术形成于该电路元件150的侧边下缘周边。
以图2A为例，该凸块区230包含导电凸块135～137及围绕该复数个导电凸块135～137的介电材料138，该线路区330则包含导电线路121～126及围绕并覆盖该复数个导电线路121～126的介电材料127。该复数个导电凸块135～137的位置安排会与将要放置其上的电路元件150的连接端151～153彼此对应，例如，排列成行列型式的矩阵。该复数个导电凸块135～137的相邻者之间之间隔距离可小到10μm。该复数个导电线路121～126组成该封装结构100的上层电路布局。该重布线层180又称为增线层，是该封装结构100的上层电路布局，而形成于该导电图案层120下方。此外，该导柱层170包含金属柱状物171～177以及围绕该复数个金属柱状物171～177的介电材料178，该重布线层180包含导电线路181～187以及围绕该复数个导电线路181～187的介电材料188。如图2A所示，通过该复数个金属柱状物171～177，该复数个导电凸块135～137及该复数个导电线路121～126可连接到作为该封装结构100下层电路布局的该重布线层180，使得该复数个导电凸块135～137可重新连接到其他合适的位置，且该复数个导电线路121～126可与该复数个导电线路181、182、186、187组合成更高密度的电路。
该电路元件150可以是主动元件或半导体晶片，其系以积体电路制程技术施加于半导体晶圆(wafer)，并加以切割成晶粒(die)及接上作为连接端151～153的外接脚垫(或称为接脚(pin)或垫片(pad))，例如，特殊应用积体电路(Application-SpecificIntegrated Circuit，简称ASIC)或应用处理器(Application Processor，简称AP)。该介电材料160用以包覆该电路元件150及该线路区330，可凭借封装胶体的铸模技术来制作，例如，压缩铸模法(Compression molding)，其组成材质可以是酚醛基树脂(Novolac-basedresin)、环氧基树脂(Epoxy-based resin)、或硅基树脂(Silicone-based resin)等绝缘材料；但本发明对此不加以限制，也可以使用液态树脂充填技术或膜状介电材料真空压膜技术。在本实施例中，该复数个介电材料127、138、160、178、188可以是相同或不同的组成材质，该介电材料127可以局部或完全覆盖，该复数个导电线路121～126，或平齐于该复数个导电线路121～126的端面，本发明对此也不加以限制。
当该电路元件150设置于该导电图案层120上的时候，其连接端151～153会分别对准该凸块区230的导电凸块135～137。此时，该电路元件150的侧边下缘与该介电材料127之间仍可能存有空隙，为了使得该凸块区230在该介电材料138尚未填入前能形成一个只包含该复数个导电凸块135～137的密闭空间，本实施例在该电路元件150的侧边下缘施加该绝缘阻隔胶140于该线路区330的该介电材料127上，如图2A所示。如此，在进行该介电材料160的铸模成形时，该介电材料160受到该电路元件150、该介电材料127及该绝缘阻隔胶140的阻隔而不致进入上述的凸块区密闭空间；如此的目的是防止倘若该介电材料160填入该凸块区230所将造成的充填不良，而形成气泡或空洞(void)，这将非常不利于细间距线路或细间距凸块的制作。该介电材料138的填入是施作于一相对空旷的空间，因此可克服气泡或空洞的问题，且不需要求施作表面严格的平整度。该绝缘阻隔胶140的组成材质可以是流体状或薄膜状的树脂材料。
图4A为根据本发明第二实施例的封装结构200的剖面示意图。该封装结构200基本上相同于图2A的封装结构100，其差异处在于：该封装结构200在该介电材料160内还形成复数个金属导柱191～194，使得该封装结构100的电路布局及设计具有更大的弹性空间，可还制作堆叠封装结构(例如，本说明书后面将会描述的第五实施例)。
图2B为根据本发明第三实施例的封装结构300的剖面示意图。该封装结构300基本上相同于图2A的封装结构100，其差异处在于：该封装结构300在该导电图案层120内还包含一阻隔框130，其设置于该凸块区230与该线路区330之间，且该阻隔框130具有一线宽W，使得该电路元件150的边缘位于其线宽范围内，如图3B所示。换言之，该导电图案层120的平面图可区分成三个部分：凸块区230、阻隔框130及线路区330，其中该金属阻隔框130围绕该凸块区230，该线路区330围绕该阻隔框130。此外，图3B代表本实施例的该导电图案层120在X-Y平面的剖面图，该阻隔框130基本上是方框或矩形框，具有四个宽度为W的框边，其框内为凸块区230，框外则为线路区330。本发明对该阻隔框130的形状不加以限制，端视后续将要放置的电路元件150的外型而定，使得该电路元件150的边缘位于其框边的宽度W范围内，则该电路元件150与该阻隔框130能将该凸块区230包覆起来。
该介电材料127形成于该导电图案层120及该阻隔框130上。当该电路元件150设置于该导电图案层120上的时候，其连接端151～153会分别对准该凸 块区230的导电凸块135～137。此时，该电路元件150的底部会略高于该阻隔框130且略低于该介电材料127，使该电路元件150的侧边下缘与该介电材料127之间有些许的间距，再施加以绝缘阻隔胶140，如图2B所示，使得该凸块区230在该介电材料138尚未填入前能形成一个只包含该复数个导电凸块135～137的空间，从而在进行该介电材料160的铸模成形时，该介电材料160受到该电路元件150、该介电材料127及该阻隔框130的阻隔而不致进入上述的凸块区密闭空间。该阻隔框130在制程上与该复数个导电线路121～126及该复数个导电凸块135～137一起形成于该导电图案层120内的同一层。此外，由于金属材质的该阻隔框130包围该复数个导电凸块135～137以及该电路元件150的连接端151～153，因此该阻隔框130也对该凸块区230具有电磁屏蔽(electromagnetic shield)的功效。
图4B为根据本发明第四实施例的封装结构400的剖面示意图。该封装结构400基本上相同于图2B的封装结构300，其差异处在于：该封装结构400在该介电材料160内还形成复数个金属导柱191～194，使得该封装结构400的电路布局及设计具有更大的弹性空间，可还制作堆叠封装结构。
以下说明本发明第一及第二实施例的封装结构的制程。请参照图5A、图6A、图7、图8及图2A(以第一实施例的封装结构100为例)，其分别对应上述第一实施例封装结构100各个制程步骤的封装结构的剖面图。
首先，提供一承载板110，其为一导电材质的基板，例如，金属基板或是表面镀有金属层的介电材质基板，用以承载或支持该封装结构100的后续制程，例如，制作该封装结构100的导电线路。上述基板的金属成分包含铁(Fe)、铜(Cu)、镍(Ni)、锡(Sn)、铝(Al)、镍/金(Ni/Au)及其组合或合金，但本发明不以此为限。
接着，可凭借光微影(Photolithography)及电镀(Electrolytic Plating)技术，形成一图案化的细线路间距的金属层于该承载板110上，以形成包含凸块区230及线路区330的导电图案层120，如图3A所示；也就是说，该线路区330为围绕该凸块区230的外环区域，该凸块区230的框边可以是方框或矩形框，其框外为线路区330。该凸块区230包含导电凸块135～137，该线路区330则包含导电线路121～126。接着，形成一层介电材料127于该承载板110上，使其包覆该导电图案层120，再以光微影技术的显影方式，或电浆蚀刻法，或喷砂技术选择性移除该凸块区230内的介电材料127，使得该介电材料127只包覆该复数个导电线路121～126，而不包覆该复数个导电凸块135～137，如图5A所示。
接着，将该电路元件150设置于该导电图案层120上。该电路元件150具有复数个连接端151～153，且当该电路元件150设置于该导电图案层120上的时候，其外缘会坐落于其框边的宽度W范围内，且该复数个连接端151～153会分别对准该复数个导电凸块135～137。此时，该电路元件150的侧边下缘会与该介电材料127些微接触，二者之间仍可能存有空隙。由于本制程后续将会以类似铸模方式形成介电材料160于该承载板110上，使其包覆该电路元件150及该线路区330，为了使得该凸块区230在介电材料138尚未填入前能形成一个只包含该复数个导电凸块135～137的密闭空间，以确保该介电材料160在此铸模步骤进行过程中不会渗入上述的密闭空间，本实施例凭借类似点胶或薄膜型材料真空贴合技术，施加树脂材料于该线路区330上并围绕该电路元件150的侧边下缘周边，而形成如图6A所示的绝缘阻隔胶140。如此，该电路元件150、该介电材料127及该绝缘阻隔胶140可形成一凸块区密闭空间。
接着，如图7A所示，凭借封装胶体的铸模技术，例如，压缩铸模法、液态树脂充填技术或介电材料真空压膜技术，于该承载板110上形成包覆该电路元件150及该线路区330的介电材料160，其组成材质可以是酚醛基树脂、环氧基树脂、或硅基树脂等绝缘材料。该介电材料160硬化后将与该电路元件150形成稳固的封装结构。接着，移除该承载板110。如上所述，由于该电路元件150、该该线路区330的该介电材料127、以及该绝缘阻隔胶140的阻隔作用，该介电材料160在其铸模过程中不会渗入该电路元件150的下方。此时该电路元件150下方只有排列成矩阵型式且彼此隔离的金属孤岛(例如，导电凸块135与连接端151的组合结构为第一孤岛，导电凸块136与连接端152的组合结构为第二孤岛，导电凸块137与连接端153的组合结构为第三孤岛)。在另一实施例中，该复数个导电凸块135～137之间可以彼此连接，或是另以导电线路连接至该线路区330的导电线路121～126，本发明对此不加以限制。
在该承载板110移除之后，可将由该导电图案层120、该电路元件150及该介电材料160所组成的剩余部分形成如图7A所示的主体结构。将图7A的主体结构上下翻转，并形成一层介电材料178于该主体结构上，使其包覆该电路元件150、该导电图案层120及该凸块区230。由于该电路元件150上方的金属孤岛彼此隔离，介电材料178可轻易地以类似点胶方式(或是使用液态树脂充填方式、铸模化合物模压方式、或介电材料真空压膜方式)而有效地充填于该电路元件150上方及围绕该复数个金属孤岛而覆盖该凸块区230，而有效减小空穴(void) 形成其中的可能性。接着，可再以光微影及金属电镀技术、雷射开口技术、或电浆蚀刻技术形成开口，再施以金属电镀于上述开口，来制作以形成金属柱状物171～177，如图8A所示。如此方法，该介电材料178不需选用成本较高的底部填充剂(Underfill)，只需一般性介电材料即可达到在电路元件150的各连接端151～153之间的充填效果，可降低封装基板元件的制作成本。
接着，可利用增层技术来制作重布线层180，如图2A所示。该重布线层180包含导电线路181～187以及围绕该复数个导电线路181～187的介电材料188。如图2A所示，通过该复数个金属柱状物171～177，该复数个导电凸块135～137及该复数个导电线路121～126可连接到作为该封装结构100下层电路布局的该重布线层180，使得该复数个导电凸块135～137可重新连接到其他合适的位置，且该复数个导电线路121～126可与该复数个导电线路181、182、186、187组合成更高密度的电路。
在第二实施例中，为使该封装结构100的电路布局具有更大的弹性空间，复数个金属导柱191、192、193、194可形成于该复数个导电线路121、123、124、126上，如图6B、图7B、图8B所示，此步骤可凭借例如光微影及电镀技术来实现。该复数个金属导柱191～194可形成于该电路元件150的设置之前，或是先设置该电路元件150再制作该复数个金属导柱191～194，本发明对此不加以限制。在本实施例中，该介电材料160及该复数个金属导柱191～194必须以研磨或电浆蚀刻技术移除其上半部，如图7B所示。
以下说明本发明第三及第四实施例的封装结构的制程，其基本上相同于第一实施例的封装结构100的制程，主要差异处请参照图5B，当形成于该承载板110上的金属层被施以图案化时，该导电图案层120会包含如图3B所示的凸块区230、阻隔框130及线路区330，其中，该金属阻隔框130围绕该凸块区230，该线路区330围绕该阻隔框130。该阻隔框130基本上是方框或矩形框，具有四个宽度为W的框边，其框内为凸块区230，框外则为线路区330；但本发明对此不加以限制，该阻隔框130也可以是不规则形状框，端视该电路元件150的形状而定。此外，当该电路元件150设置于该导电图案层120上的时候，其外缘会坐落于该阻隔框130框边的宽度W范围内，使得该电路元件150的底面、位于该阻隔框130上的该介电材料127、以及该承载板110的顶面可形成一个含有该复数个导电凸块135～137的空间，如图6C所示。如此，也能在该绝缘阻隔胶140施加于该电路元件150的侧边下缘之后，该电路元件150、该阻隔框130上的该介电材料127、以及该绝缘阻隔胶140将可提供良好的阻隔作用，使得后续该介电材料160的铸模过程不会渗入该电路元件150下方空间的效果。其余与第一实施例封装结构100相同的制程，请参阅前文所述，在此不再赘述。此外，该介电材料127只包覆该复数个导电线路121～126及部份或全部的该阻隔框130，而不包覆该复数个导电凸块135～137，如图5B所示。
在第四实施例中，为使该封装结构400的电路布局具有更大的弹性空间，复数个金属导柱191、192、193、194可形成于该复数个导电线路121、123、124、126上，如图6D所示，此步骤可凭借例如光微影及电镀技术来实现。该复数个金属导柱191～194可形成于该电路元件150的设置之前，或是先设置该电路元件150再制作该复数个金属导柱191～194，本发明对此不加以限制。在本实施例中，该介电材料160及该复数个金属导柱191～194必须以研磨或电浆蚀刻技术移除其上半部，如图7B所示。
图9为根据本发明第五实施例的封装结构500的剖面示意图。该封装结构500基本上系建构于图4A封装结构200的基础上，还于该介电材料160内设置另一电路元件550，其连接端551、552朝上连接该介电材料160上的另一层导电线路520。如此，本实施例的封装结构可实现电路元件的多层堆叠结构，使封装结构的电路布局及设计具有更大的弹性空间。
以上说明对本实用新型而言只是说明性的，而非限制性的，本领域普通技术人员理解，在不脱离本申请所限定的精神和范围的情况下，可作出许多修改、变化或等效，但都将落入本实用新型的保护范围之内。

Claims (12)

1.一种封装结构，其特征在于，包含：
一导电图案层，包含一凸块区及一线路区，其中该凸块区包含复数个导电凸块及一围绕该复数个导电凸块的第一介电材料，该线路区包含复数个第一导电线路及一围绕并覆盖该复数个第一导电线路的第二介电材料；
一电路元件，具有复数个连接端并设置于该凸块区上，其中该复数个连接端与该复数个导电凸块彼此对应；
一绝缘阻隔胶，其形成于该第二介电材料上并围绕该电路元件的侧边下缘；以及
一第三介电材料，包覆该电路元件及该线路区。
2.根据权利要求1所述的封装结构，其特征在于，该导电图案层还包含一阻隔框，其设置于该凸块区与该线路区之间，且该阻隔框具有一线宽，使得该电路元件的边缘位于该阻隔框的线宽范围内。
3.根据权利要求2所述的封装结构，其特征在于，该阻隔框的组成材质为金属或有机绝缘材料。
4.根据权利要求1所述的封装结构，其特征在于，还包含复数个第一导电柱状物，其形成于该复数个第一导电线路上并被该第三介电材料所包覆。
5.根据权利要求1所述的封装结构，其特征在于，该电路元件为半导体晶片或电子元件。
6.根据权利要求1所述的封装结构，其特征在于，还包含：
一导柱层，包含复数个第二金属柱状物及一围绕该复数个第二金属柱状物的第四介电材料，该导柱层形成于该导电图案层下方；以及
一重布线层，包含复数个第二导电线路以及一围绕该复数个第二导电线路的第五介电材料，该重布线层形成于该导柱层下方。
7.一种封装结构的制作方法，其特征在于，其步骤包含：
(A)在一承载板上形成一导电图案层，其中该导电图案层包含一凸块区及一线路区，该凸块区包含复数个导电凸块，且该线路区包含复数个导电线路；
(B)形成一第二介电材料，其包覆该复数个导电线路；
(C)在该凸块区上设置一具有复数个连接端的电路元件，使得该复数个连接端与该复数个导电凸块彼此对应；
(D)在该第二介电材料上形成一绝缘阻隔胶，并且该绝缘阻隔胶围绕该电路元件的侧边下缘；
(E)在该承载板上形成一第三介电材料，使其包覆该电路元件及该线路区；
(F)移除该承载板，并在该导电图案层及该电路元件上形成一第四介电材料，使该第四介电材料围绕该复数个导电凸块及该电路元件的该复数个连接端；以及
(G)在该第四介电材料中形成复数个金属柱状物，使该复数个金属柱状物连接该复数个导电凸块及该复数个导电线路。
8.根据权利要求7所述的制作方法，其特征在于，在步骤(D)之前还包含：(C1)在该复数个导电线路上形成复数个导电柱状物。
9.根据权利要求7所述的封装结构的制作方法，其特征在于，该电路元件为半导体晶片或电子元件。
10.一种封装结构的制作方法，其特征在于，其步骤包含：
(A)在一承载板上形成一导电图案层，其中该导电图案层包含一凸块区、一围绕该凸块区的金属阻隔框、及一围绕该金属阻隔框的线路区，该凸块区包含复数个导电凸块，该线路区包含复数个导电线路，且该金属阻隔框具有一线宽；
(B)形成一第二介电材料，其包覆该金属阻隔框及该复数个导电线路；
(C)在该凸块区及该金属阻隔框上设置一具有复数个连接端的电路元件，使得该复数个连接端与该复数个导电凸块彼此对应，且该电路元件的边缘位于该金属阻隔框的线宽范围内；
(D)在该第二介电材料上形成一绝缘阻隔胶，并且该绝缘阻隔胶围绕该电路元件的侧边下缘；
(E)在该承载板上形成一第三介电材料，使其包覆该电路元件及该线路区；
(F)移除该承载板，并在该导电图案层及该电路元件上形成一第四介电材料，使该第四介电材料围绕该复数个导电凸块及该电路元件的该复数个连接端；以及
(G)在该第四介电材料中形成复数个金属柱状物，使该复数个金属柱状物连接该复数个导电凸块及该复数个导电线路。
11.根据权利要求10所述的封装结构的制作方法，其特征在于，在步骤(D)之前还包含：(C1)在该复数个导电线路上形成复数个导电柱状物。
12.根据权利要求11所述的封装结构的制作方法，其特征在于，该电路元件为半导体晶片或电子元件。
CN201610969569.8A 2016-10-14 2016-10-28 封装结构及其制作方法 Active CN107958844B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW105133328A TWI602275B (zh) 2016-10-14 2016-10-14 封裝結構及其製作方法
TW105133328 2016-10-14

Publications (2)

Publication Number Publication Date
CN107958844A true CN107958844A (zh) 2018-04-24
CN107958844B CN107958844B (zh) 2021-03-26

Family

ID=61011202

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610969569.8A Active CN107958844B (zh) 2016-10-14 2016-10-28 封装结构及其制作方法

Country Status (3)

Country Link
US (1) US10361160B2 (zh)
CN (1) CN107958844B (zh)
TW (1) TWI602275B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI675441B (zh) * 2018-05-14 2019-10-21 欣興電子股份有限公司 封裝載板結構及其製造方法
JP2020053655A (ja) * 2018-09-28 2020-04-02 キオクシア株式会社 半導体装置及び半導体装置の製造方法
JP7385483B2 (ja) * 2020-01-27 2023-11-22 キオクシア株式会社 半導体装置およびその製造方法
CN113571494A (zh) * 2020-04-28 2021-10-29 群创光电股份有限公司 电子装置及其制作方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313527B1 (en) * 1998-12-10 2001-11-06 United Microelectronics Corp. Dual-dies packaging structure and packaging method
CN101030565A (zh) * 2006-03-01 2007-09-05 南茂科技股份有限公司 高频集成电路封装构造及其制造方法
TW200816439A (en) * 2006-07-26 2008-04-01 Texas Instruments Inc Array-processed stacked semiconductor packages
US20100013076A1 (en) * 2008-07-21 2010-01-21 Samsung Electronics., Co., Ltd. Semiconductor device package and method of fabricating the same
CN104952828A (zh) * 2014-03-25 2015-09-30 恒劲科技股份有限公司 覆晶堆叠封装结构及其制作方法
TW201611204A (zh) * 2014-09-05 2016-03-16 台灣積體電路製造股份有限公司 具有凹陷邊緣的半導體裝置以及製造方法
CN105990270A (zh) * 2015-02-13 2016-10-05 矽品精密工业股份有限公司 电子封装件及其制法
CN106158673A (zh) * 2015-02-06 2016-11-23 矽品精密工业股份有限公司 封装结构及其制法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007069606A1 (ja) * 2005-12-14 2007-06-21 Shinko Electric Industries Co., Ltd. チップ内蔵基板およびチップ内蔵基板の製造方法
JP5162226B2 (ja) * 2007-12-12 2013-03-13 新光電気工業株式会社 配線基板及び半導体装置
KR101481577B1 (ko) * 2008-09-29 2015-01-13 삼성전자주식회사 잉크 젯 방식의 댐을 구비하는 반도체 패키지 및 그 제조방법
JP5587123B2 (ja) * 2010-09-30 2014-09-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5837339B2 (ja) * 2011-06-20 2015-12-24 新光電気工業株式会社 半導体装置の製造方法及び半導体装置
US20170017898A1 (en) * 2015-07-14 2017-01-19 Bradley Hertz Method of Determining Working Memory Retrieval Through Finite Automata and Co-Prime Numbers
KR101912278B1 (ko) * 2015-12-21 2018-10-29 삼성전기 주식회사 전자 부품 패키지 및 그 제조방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313527B1 (en) * 1998-12-10 2001-11-06 United Microelectronics Corp. Dual-dies packaging structure and packaging method
CN101030565A (zh) * 2006-03-01 2007-09-05 南茂科技股份有限公司 高频集成电路封装构造及其制造方法
TW200816439A (en) * 2006-07-26 2008-04-01 Texas Instruments Inc Array-processed stacked semiconductor packages
US20100013076A1 (en) * 2008-07-21 2010-01-21 Samsung Electronics., Co., Ltd. Semiconductor device package and method of fabricating the same
CN104952828A (zh) * 2014-03-25 2015-09-30 恒劲科技股份有限公司 覆晶堆叠封装结构及其制作方法
TW201611204A (zh) * 2014-09-05 2016-03-16 台灣積體電路製造股份有限公司 具有凹陷邊緣的半導體裝置以及製造方法
CN106158673A (zh) * 2015-02-06 2016-11-23 矽品精密工业股份有限公司 封装结构及其制法
CN105990270A (zh) * 2015-02-13 2016-10-05 矽品精密工业股份有限公司 电子封装件及其制法

Also Published As

Publication number Publication date
US10361160B2 (en) 2019-07-23
TWI602275B (zh) 2017-10-11
CN107958844B (zh) 2021-03-26
US20180108615A1 (en) 2018-04-19
TW201814864A (zh) 2018-04-16

Similar Documents

Publication Publication Date Title
CN104051334B (zh) 半导体封装和封装半导体装置的方法
CN107275294B (zh) 薄型芯片堆叠封装构造及其制造方法
CN105575913B (zh) 埋入硅基板扇出型3d封装结构
CN103187394B (zh) 具有无源器件的封装件及其形成方法
US8053275B2 (en) Semiconductor device having double side electrode structure and method of producing the same
CN101499445B (zh) 半导体器件及其制造方法
TWI255538B (en) Semiconductor package having conductive bumps on chip and method for fabricating the same
TWI392066B (zh) 封裝結構及其製法
CN109494202B (zh) 一种半导体芯片封装方法及封装结构
CN104051394B (zh) 半导体封装和封装半导体装置的方法
CN103779235A (zh) 扇出晶圆级封装结构
CN104952828A (zh) 覆晶堆叠封装结构及其制作方法
CN107346766A (zh) 整合扇出型封装及其制造方法
CN107958844A (zh) 封装结构及其制作方法
TW201705386A (zh) 以封膠體取代基板核心之多晶片封裝構造
CN105489565A (zh) 嵌埋元件的封装结构及其制法
US20150332937A1 (en) Semiconductor device, semiconductor stacked module structure, stacked module structure and method of manufacturing same
CN109427700A (zh) 集成电路封装及其制作方法
CN110246812A (zh) 一种半导体封装结构及其制作方法
CN105206595B (zh) 封装基板、包含该封装基板的覆晶封装电路及其制作方法
CN107301954A (zh) 封装基板的制作方法
CN108022846A (zh) 封装基板及其制作方法
JP6290987B2 (ja) 半導体パッケージ基板及びその製造方法
KR102170383B1 (ko) 플립칩 자기 센서 패키지 및 그 제조 방법
CN106941101A (zh) 封装基板及其制作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20200708

Address after: Hsinchu County, Taiwan, China

Applicant after: PHOENIX PIONEER TECHNOLOGY Co.,Ltd.

Address before: The Cayman Islands KY1-1205 Grand Cayman West Bay Road No. 802 Furong Road Hongge mailbox No. 31119

Applicant before: PHOENIX & Corp.

GR01 Patent grant
GR01 Patent grant