CN103579170B - 电介质层中粘附结构的产生以及结合粘附结构的器件 - Google Patents

电介质层中粘附结构的产生以及结合粘附结构的器件 Download PDF

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CN103579170B
CN103579170B CN201310313031.8A CN201310313031A CN103579170B CN 103579170 B CN103579170 B CN 103579170B CN 201310313031 A CN201310313031 A CN 201310313031A CN 103579170 B CN103579170 B CN 103579170B
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geometry
conductive layer
layer
dielectric layer
semiconductor device
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CN103579170A (zh
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T.格利勒
U.黑德尼希
R.穆特
J.普拉格曼
H.舍恩赫尔
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Infineon Technologies AG
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Abstract

本发明公开了电介质层中粘附结构的产生以及结合粘附结构的器件。在本公开的各种方面中，一种半导体器件包括：至少一个半导体管芯；邻接所述半导体管芯的电介质层；在所述电介质层中形成的几何结构；以及在所述电介质层上沉积的导电层，其中所述导电层至少部分地位于所述几何结构上。

Description

电介质层中粘附结构的产生以及结合粘附结构的器件
技术领域
本公开的各种方面总体上涉及用于改进电介质层中的粘附的方法。
背景技术
现今，集成电路器件的制造通常包括在器件的表面形成金属键合垫（bond pad）。有时存在金属键合垫到底层电介质表面的粘附的问题。改进金属键合垫到这样的表面的粘附会是有用的。
发明内容
根据本公开的一个方面，提供一种半导体器件结构。所述半导体器件结构包括：至少一个半导体器件；邻接所述半导体器件的电介质层；在所述电介质层中形成的几何结构；以及在所述电介质层上沉积的导电层，其中所述导电层至少部分地位于所述几何结构上。
根据本公开的另一方面，提供一种在半导体器件上沉积导电层的方法。所述方法包括：提供至少一个半导体器件；在所述半导体器件上形成至少一个电介质层；在所述电介质层中形成多个几何结构；以及在第一电介质层上沉积第一导电层，第一导电层至少部分地位于所述多个几何结构上。
附图说明
在附图中，类似的附图标记通常指代遍及不同视图的相同部分。附图不一定是按比例的，而是通常将重点放在说明本发明的原理上。在下列描述中，参考下列附图来描述本发明的公开的各种方面，在附图中：
图1示出半导体器件剖面；
图2示出根据本公开的方面的工艺；
图3A-E示出根据本公开的方面的蚀刻工艺；以及
图4A-4E示出根据本公开的方面的蚀刻工艺。
具体实施方式
在本公开的各种方面中，可以提供可以包括覆盖结构化（textured）衬底的一个或多个键合垫的器件。结构化表面可以通过在表面中形成几何结构来形成。几何结构图案可以通过光刻工艺来形成。键合垫可以由金属材料形成。结构化表面可以包括硅材料。含硅材料可以包括硼磷硅玻璃（BPSG）。图案尺寸可以进行改变以增加到表面的粘附水平。粘附也可以取决于被用来形成几何结构的工艺而进行改变。
下列详细描述参考了附图，所述附图通过图示的方式示出其中可以实践示例性实施例的本公开的特定细节和方面。在不偏离本公开的范围的情况下，可以利用本公开的其他方面并且可以做出结构、逻辑和电的改变。本公开的各种方面不一定是互斥的，因为本公开的一些方面可以与本公开的一个或多个其他方面进行组合以形成本公开的新方面。因此，下列详细描述不应在限制性意义上来理解，并且本实例的范围由所附权利要求来限定。
针对器件来提供本公开的各种方面，并且针对方法来提供本公开的各种方面。将理解的是，器件的基本特性也适用于方法并且反之亦然。因此，为了简洁起见，可能省略对这样的特性的重复描述。
如在本文中使用的术语“耦合”或“连接”可以被理解成分别包括直接“耦合”或直接“连接”以及间接“耦合”或间接“连接”。
如在本文中使用的术语“设置在…上”、“位于…上”或“布置在…上”意图包括其中第一元件或层可以被直接地设置、定位或布置在第二元件或层上（中间没有另外的元件或层）的布置，以及其中第一元件或层可以被设置、定位或布置在第二元件或层上（一个或多个附加元件或层在第一元件或层与第二元件或层之间）的布置。
如在本文中使用的术语“键合垫”可以被理解成包括例如形成管芯或芯片的表面连接点的垫。在应用球附着工艺的情况下，还可以使用术语“球垫”。
如在本文中使用的术语“再分布迹线”可以被理解成包括例如设置在半导体器件的或晶片的有源表面上并且被用来重定位半导体器件或晶片的键合垫的导线或迹线。换言之，键合垫在半导体器件或晶片上的原位置可以借助于再分布迹线而被移位到新位置，所述再分布迹线可以用作在半导体器件或晶片上的新位置处的（再定位的）键合垫与原位置处的电接触（或垫）之间的电连接。
如在本文中使用的术语“再分布层（RDL）”可以被理解成指代包括被用来再定位（“再分布”）管芯或晶片的多个键合垫的至少一个或一组再分布迹线的层。
在半导体器件的制造中，需要提供在器件表面中的用于将器件连接到外部封装或较大的电子器件（例如电路板）的点。这通常通过经由键合垫将金属引线或连接附着到半导体器件来完成。举例来说，键合垫形成器件互连（例如扇出设计封装中的再分布层）的端点。举例来说，键合垫提供相对较大的连接表面，通过本领域中已知的键合工艺（例如通过焊球）将金属引线或连接附着到所述连接表面。
在使用期间，电子器件和半导体器件通常将经历由于例如热循环和归因于例如碰撞的震动而引起的各种应力。这些应力将又被传送到器件内的各种电连接，包括键合垫与外部封装或PCB之间的电连接。如果应力足够剧烈，则连接会被破坏，从而潜在地导致器件的故障。在连接内的许多地方中会发生破坏，但是在本实例中特别感兴趣的是由于键合垫粘附的丧失而引起的连接故障。在本实例中，键合垫和电连接保持电连接。然而，键合垫升离半导体器件的表面，因此与底层互连至少部分地断开。因此，感兴趣的是改进键合垫到底层衬底的粘附。
图1示出示例性半导体器件100的简化截面。衬底101包括许多组合层，它们形成器件的有源层（未示出）。键合垫105被附着到源自衬底101内的互连（未示出）。键合垫105可以由任何合适的材料形成，包括例如铝（Al）、铜（Cu）、钛（Ti）或金（Au）。就本公开来说，用来形成键合垫105的材料不是限制性的。
到外部器件的电连接可以被直接形成到键合垫105，或者如更频繁地实践的那样，键合垫105形成到再分布层150的连接。再分布层150被形成在衬底101上。再分布层150由第一电介质层115、再分布迹线110和第二电介质层125形成。在一个实施例中，第一电介质层115由硼磷硅玻璃（BPSG）形成。然而，对本公开来说所使用的电介质的类型不是关键的，并且因而可以使用其他常用的半导体电介质，例如二氧化硅（SiO2）、氮化硅（SiN）或其他已知的电介质材料。
第二电介质层125中的开口120形成第二键合垫120。在本公开的一个方面中，第二键合垫120（以及因此再分布迹线110）由钛（Ti）形成。然而，在本文中指定的材料不是关键的，并且因此所公开的键合垫粘附方法与在半导体器件中常用的其他金属（例如铜（Cu）、镍（Ni）、金（Au）、铝（Al））或由这些材料的组合形成的合金或层相容。正是与再分布层150相关联的第二键合垫120将是下列示例性实施例的目的。
图2示出根据本公开的一个方面的工艺步骤的序列，其中进一步参考图1中所示的结构。图2是示例性序列，并且因此可能没有示出在典型制造序列中使用的所有层或步骤。因而并且如将变得明显的那样，关于用于改进键合垫粘附的所公开的方法，特定器件制造步骤或层的存在或不存在不应该被视为是限制性的。
该讨论假设，在步骤201处，已经通过通常被称为工艺的“前端”的内容在半导体衬底中创建了许多半导体器件，如本领域中很好地理解的那样，在工艺的“前端”中已经沉积了管芯层。此外，已经在器件的表面上形成键合垫。例如，通过图1上的特征101和105示出单个器件和键合垫。
在205处，在器件上沉积第一电介质层。对本公开来说电介质的类型不是重要的，并且因此不是限制性的。对本实施例来说，电介质包括BPSG。该层类似于例如图1中的层115。
在210处，执行本公开的一个方面中的图案化工艺。在该步骤中，在第一电介质层的表面中形成几何结构的图案，正如将在下面更详细地公开的那样。例如通过光刻工艺来形成图案化。
在215处，在图案化的第一电介质层上沉积再分布层。该层类似于图1中的层110。该层是导电层，并且因此可以由许多不同材料来形成。用于该步骤的有用导电材料的实例包括Ni、Cu、Al、Ti或Au、或其混合物或合金。
在216处，图案化所述导电层。这可以使用可用于金属图案化的任何工艺来完成，例如干蚀刻或湿化学蚀刻。对本公开来说，用于图案化所述导电层的蚀刻工艺的本质不是限制性的。
在220处，可以在再分布层之上形成第二电介质层。该层类似于图1中的层125。对本公开来说，所使用的电介质的本质不是限制性的。
在225处，可以执行光刻工艺以形成第二键合垫。该键合垫类似于图1中的结构120。在完成该步骤时，半导体器件继续进行另外的处理。因为在本文中公开的键合垫粘附方法不依赖于这些处理步骤，所以将不进一步讨论它们。
图3A-3D示出在本公开的一个方面中的用于产生具有增加的粘附的键合垫的一种方法。为了易于参考，用来标识各种层的附图标记与用来标识图1中的层的附图标记相一致。
图3A示出半导体器件，其包括管芯301、第一键合垫305和第一电介质层315。这对应于图2的步骤205。在该示例性实施例中，第一电介质层315包括硼磷硅玻璃（BPSG）。
如图3B中所示，沉积光致抗蚀剂层330。光致抗蚀剂层330是通常在半导体器件光刻工艺中使用的类型。在该示例性实施例中，光致抗蚀剂是通常用于干蚀刻工艺的类型。
在图3C中，使用适合于所使用的光致抗蚀剂层330的光掩模和光源（未示出）来暴露和图案化光致抗蚀剂层330。在暴露和图案化光致抗蚀剂层330之后，去除未图案化的光致抗蚀剂。
在去除未图案化的光致抗蚀剂之后，例如执行干化学蚀刻。干化学蚀刻将取决于用于第一电介质层315的材料而变化。对于BPSG，腐蚀气体可以是四氟化碳（CF4）、氟代甲烷（CHF3）和氧气（O2）的混合物，其中例如氩（Ar）被用作载气。在完成蚀刻工艺时，去除剩余的光致抗蚀剂结构330。
在图3D中，示出图案化的第一电介质层315。在第一电介质层315中已经形成几何结构340。在本公开的一个方面中，几何结构340在形状上粗略为圆形。几何结构340的深度345将取决于制造要求而变化。在本公开的一个方面中，深度345的范围例如将从100到300nm。几何结构340具有一致的间隔350。间隔350也将取决于应用而变化。在一个实施例中，间隔的范围将处于2到50μm之间。几何结构340也可以具有某一范围的直径355。几何结构340的直径355的范围例如可以处于1到5μm之间。在本公开的一个方面中，由干蚀刻产生的几何结构340可以具有底切的剖面，如在360处所示。
在图案化之后，器件通过所述工艺的剩余部分继续进行，如图2中在215、220和225处所示。该工艺产生在图3E处所示的示例性结构。
图4A-4D示出在本公开的一个方面中的用于产生具有增加的粘附的键合垫的另一方法。为了易于参考，用来标识各种层的附图标记与用来标识图1中的层的附图标记相一致。
图4A示出半导体器件，其包括管芯401、第一键合垫405和第一电介质层415。这对应于图2的步骤205。在该示例性实施例中，第一电介质层415包括硼磷硅玻璃（BPSG）。
如图4B中所示，沉积光致抗蚀剂层430。光致抗蚀剂层430是通常在半导体器件光刻工艺中使用的类型。在该实施例中，光致抗蚀剂是通常用于湿蚀刻工艺的类型。
在图4C中，使用适合于所使用的光致抗蚀剂层430的光掩模和光源（未示出）来暴露和图案化光致抗蚀剂层430。在暴露和图案化光致抗蚀剂层430之后，去除未图案化的光致抗蚀剂。
在去除未图案化的光致抗蚀剂之后，执行湿化学蚀刻。湿化学蚀刻将取决于用于第一电介质层415的材料而变化。对于BPSG，蚀刻剂可以是例如氢氟酸（HF）/氟化铵（NH4F）缓冲的氧化物蚀刻溶液。在完成蚀刻工艺时，去除剩余的光致抗蚀剂结构430。
在图4D中，示出图案化的第一电介质层415。在第一电介质层415中已经形成几何结构440。在本公开的一个方面中，几何结构440在形状上粗略为圆形。几何结构440的深度445将取决于制造要求而变化。在本公开的一个方面中，深度445的范围例如将从100到300nm。几何结构440具有一致的间隔450。间隔450也将取决于应用而变化。在一个实施例中，间隔的范围将处于5到50μm之间。几何结构440也可以具有某一范围的直径455。孔440的直径455的范围例如可以处于1到5μm之间。由湿蚀刻产生的孔440可以具有倾斜的剖面，如在460处所示。
在图案化之后，器件通过所述工艺的剩余部分继续进行，如图2中在215、220和225处所示。该工艺产生在图4E处所示的示例性结构。
由这两种方法产生的几何结构的不同形状可能影响金属层保留。具体来说，一些金属/电介质***可能显示出与使用干蚀刻过程产生的几何结构的更好粘附，而其他可能受益于湿蚀刻***的使用。在本公开的一个方面中，当使用干蚀刻过程来产生几何结构时，BPSG上的钛层可能显示出更好的保留，如图3中所示。
本领域技术人员将认识到，可以形成上面的示例性实施例的组合。例如，在本公开的一些方面中，湿蚀刻和干蚀刻过程这二者对于在第一电介质层中产生适当大小和形状的几何结构可能是必要的。此外，本公开预期下述可能性，即可能需要多种材料和沉积步骤以形成在所公开的实施例中被称为“第一电介质层”的电介质层。类似地，可以使用多个金属层来形成再分布迹线。
虽然已经参考本公开的特定方面特别地示出和描述了本发明，但是本领域技术人员应该理解，在不偏离如由所附权利要求限定的本发明的精神和范围的情况下，可以在其中做出形式和细节上的各种改变。因此，本发明的范围由所附权利要求来指示，并且因此意图包括处在权利要求的等同物的含义和范围内的所有改变。

Claims (18)

1.一种半导体器件结构，包括：
至少一个半导体器件；
邻接所述半导体器件的电介质层；
在所述电介质层中形成的几何结构；以及
在所述电介质层上沉积的导电层，其中所述导电层至少部分地位于所述几何结构上，并且所述几何结构在形状上为圆形、具有深度和底切的剖面以增加所述导电层与所述电介质层之间的粘附；
其中底切的剖面的侧壁的形状是外凸曲线。
2.根据权利要求1所述的半导体器件结构，其中，所述导电层包括键合垫。
3.根据权利要求2所述的半导体器件结构，其中，所述键合垫位于所述几何结构上。
4.根据权利要求1所述的半导体器件结构，还包括分散在第一导电层上的第二电介质层。
5.根据权利要求1所述的半导体器件结构，其中，所述导电层是钛。
6.根据权利要求1所述的半导体器件结构，其中，第一电介质层包括硼磷硅玻璃（BPSG）。
7.根据权利要求1所述的半导体器件结构，其中，所述几何结构具有范围从100nm到300nm的深度。
8.根据权利要求1所述的半导体器件结构，其中，所述几何结构具有范围从2μm到15μm的间隔。
9.根据权利要求1所述的半导体器件结构，其中，所述几何结构具有在15-30μm的范围内形成的间隔。
10.根据权利要求1所述的半导体器件结构，其中，所述几何结构具有在1-5μm的范围内形成的直径。
11.一种在半导体器件上沉积导电层的方法，所述方法包括：
提供至少一个半导体器件；
在所述半导体器件上形成至少一个电介质层；
在所述电介质层中形成多个几何结构；以及
在第一电介质层上沉积第一导电层，第一导电层至少部分地位于所述多个几何结构上，并且所述多个几何结构在形状上为圆形、具有深度和底切的剖面以增加所述第一导电层与所述第一电介质层之间的粘附；
其中底切的剖面的侧壁的形状是外凸曲线。
12.根据权利要求11所述的沉积导电层的方法，其中，所述多个几何结构以100nm与300nm之间的深度来形成。
13.根据权利要求11所述的沉积导电层的方法，其中，所述多个几何结构以范围从5μm到15μm的间隔来形成。
14.根据权利要求11所述的沉积导电层的方法，其中，所述多个几何结构以范围从15μm到30μm的间隔来形成。
15.根据权利要求11所述的沉积导电层的方法，其中，所述多个几何结构被形成具有在1-5μm的范围内的直径。
16.根据权利要求11所述的沉积导电层的方法，其中，所述导电层包括位于所述几何结构上的键合垫。
17.根据权利要求11所述的沉积导电层的方法，其中，所述导电层包括Ti。
18.根据权利要求11所述的沉积导电层的方法，其中，第一电介质层包括BPSG。
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