CN103500736A - 芯片封装结构和芯片封装方法 - Google Patents
芯片封装结构和芯片封装方法 Download PDFInfo
- Publication number
- CN103500736A CN103500736A CN201310371229.1A CN201310371229A CN103500736A CN 103500736 A CN103500736 A CN 103500736A CN 201310371229 A CN201310371229 A CN 201310371229A CN 103500736 A CN103500736 A CN 103500736A
- Authority
- CN
- China
- Prior art keywords
- chip
- pad
- syndeton
- inductance value
- bonding line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Coils Or Transformers For Communication (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310371229.1A CN103500736B (zh) | 2013-08-22 | 2013-08-22 | 芯片封装结构和芯片封装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310371229.1A CN103500736B (zh) | 2013-08-22 | 2013-08-22 | 芯片封装结构和芯片封装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103500736A true CN103500736A (zh) | 2014-01-08 |
CN103500736B CN103500736B (zh) | 2017-04-26 |
Family
ID=49865927
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310371229.1A Active CN103500736B (zh) | 2013-08-22 | 2013-08-22 | 芯片封装结构和芯片封装方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103500736B (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104810242A (zh) * | 2014-01-24 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | 一种测试结构及其制作方法 |
CN105742263A (zh) * | 2014-12-30 | 2016-07-06 | 美国亚德诺半导体公司 | 高频集成电路及其封装 |
CN109065517A (zh) * | 2014-09-23 | 2018-12-21 | 华为技术有限公司 | 射频功率组件及射频信号收发设备 |
WO2019148598A1 (zh) * | 2018-02-01 | 2019-08-08 | 深圳市华讯方舟微电子科技有限公司 | 微组装方法及芯片装置 |
CN115513187A (zh) * | 2022-11-23 | 2022-12-23 | 广东工业大学 | 一种集成片上电感的芯片、集成电路及电子装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060186554A1 (en) * | 2005-02-10 | 2006-08-24 | Ralf Otremba | Semiconductor device with a number of bonding leads and method for producing the same |
CN1957463A (zh) * | 2004-05-20 | 2007-05-02 | 德克萨斯仪器股份有限公司 | 引线接合互连的双倍密度方法 |
CN201804856U (zh) * | 2010-09-05 | 2011-04-20 | 四川大雁微电子有限公司 | 表面贴装型半导体元件 |
CN102804372A (zh) * | 2009-12-22 | 2012-11-28 | 泰塞拉公司 | 具有降低电感的结合键合元件的微电子组件 |
-
2013
- 2013-08-22 CN CN201310371229.1A patent/CN103500736B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1957463A (zh) * | 2004-05-20 | 2007-05-02 | 德克萨斯仪器股份有限公司 | 引线接合互连的双倍密度方法 |
US20060186554A1 (en) * | 2005-02-10 | 2006-08-24 | Ralf Otremba | Semiconductor device with a number of bonding leads and method for producing the same |
CN102804372A (zh) * | 2009-12-22 | 2012-11-28 | 泰塞拉公司 | 具有降低电感的结合键合元件的微电子组件 |
CN201804856U (zh) * | 2010-09-05 | 2011-04-20 | 四川大雁微电子有限公司 | 表面贴装型半导体元件 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104810242A (zh) * | 2014-01-24 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | 一种测试结构及其制作方法 |
CN104810242B (zh) * | 2014-01-24 | 2017-12-19 | 中芯国际集成电路制造(上海)有限公司 | 一种测试结构及其制作方法 |
CN109065517A (zh) * | 2014-09-23 | 2018-12-21 | 华为技术有限公司 | 射频功率组件及射频信号收发设备 |
CN105742263A (zh) * | 2014-12-30 | 2016-07-06 | 美国亚德诺半导体公司 | 高频集成电路及其封装 |
WO2019148598A1 (zh) * | 2018-02-01 | 2019-08-08 | 深圳市华讯方舟微电子科技有限公司 | 微组装方法及芯片装置 |
CN115513187A (zh) * | 2022-11-23 | 2022-12-23 | 广东工业大学 | 一种集成片上电感的芯片、集成电路及电子装置 |
Also Published As
Publication number | Publication date |
---|---|
CN103500736B (zh) | 2017-04-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20210066190A1 (en) | Molded embedded bridge for enhanced emib applications | |
CN112117264A (zh) | 具有一体式器件的嵌入式桥衬底 | |
CN103500736A (zh) | 芯片封装结构和芯片封装方法 | |
US8294256B2 (en) | Chip package structure and method of making the same | |
US10595409B2 (en) | Electro-magnetic interference (EMI) shielding techniques and configurations | |
US9368271B2 (en) | Three-dimension symmetrical vertical transformer | |
US20140167900A1 (en) | Surface-mount inductor structures for forming one or more inductors with substrate traces | |
US10818638B2 (en) | Die and package | |
US20160343653A1 (en) | Package Structure and Three Dimensional Package Structure | |
US10083922B2 (en) | Inductor interconnect | |
US20150137337A1 (en) | Semiconductor package and lead frame | |
US9474179B2 (en) | Electronic component package | |
US20150137342A1 (en) | Inductor/transformer outside of silicon wafer | |
CN113727513A (zh) | 封装基板、印刷电路板、封装器件和电子装置 | |
EP2966661A2 (en) | Three-dimension symmetrical vertical transformer | |
US9633931B2 (en) | Chip rotated at an angle mounted on die pad region | |
US20190229056A1 (en) | Bridge die design for high bandwidth memory interface | |
US20180365192A1 (en) | Die and package | |
US9577022B2 (en) | Inductor | |
TWI660483B (zh) | 電子裝置及其製造方法 | |
US20140374888A1 (en) | Semiconductor device | |
CN105633058A (zh) | 器件标识结构及其制造方法 | |
CN104821641B (zh) | 一种无线充电装置 | |
KR20140092018A (ko) | 역방향 스택 인터포저를 갖는 스택 패키지 및 제조방법 | |
CN103413821A (zh) | 半导体器件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140414 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20140414 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: Zuchongzhi road in Pudong Zhangjiang hi tech park Shanghai city Pudong New Area No. 1399 201203 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |