CN1957463A - 引线接合互连的双倍密度方法 - Google Patents
引线接合互连的双倍密度方法 Download PDFInfo
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- CN1957463A CN1957463A CNA2005800161144A CN200580016114A CN1957463A CN 1957463 A CN1957463 A CN 1957463A CN A2005800161144 A CNA2005800161144 A CN A2005800161144A CN 200580016114 A CN200580016114 A CN 200580016114A CN 1957463 A CN1957463 A CN 1957463A
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Abstract
在一个集成电路封装件(96)中,第一导线(109)接合于第一管芯接合垫(98),以形成第一接合(108),并且第一导线109接合于接合柱(104),以形成第二接合(106)。第二导线(111)接合于第一接合(108)并且耦合于接合柱(104)。
Description
技术领域
【0001】本发明涉及用于集成电路管芯的引线接合。
背景技术
【0002】对高性能集成电路设计的日益增加的需求,可能促使在一固定管芯尺寸上输入/输出(I/O)连接(即接合垫)数目的增加。I/O连接数目的增加目前可以利用至少两种公知技术中的一种来提供。在第一种技术中,多行I/O连接交错,其中每行的接合垫相对于另一行的接合垫偏移。交错设计通常需要增加管芯尺寸,因此交错设计会使不合需要的产品成本的增加。而且,附加的接合指可能需要提供附加功率和接地连接,以维持IC的功能性,由此进一步增加了制造成本。
【0003】用于增加I/O连接数目的第二种技术包括,减小接合垫尺寸,由此允许在管芯上形成数目更多的接合垫。但是,减小的接合垫尺寸需要直径(即导线的横截面积)减小的引线接合导线。更小的导线直径带来了多种不利情况。一种不利情况是,导线中的阻抗和电感增加,从而降低了IC的性能质量。另一种不利情况是由共同成型处理中导线“偏移”(即移出原来位置)效应引起的。为了克服导线偏移,必须减小导线长度,由此增加了制造复杂度。第三种不利情况是在具有交错设计和减小的接合垫尺寸的管芯中出现的。由于密集的接合垫管脚间距,接合导线可能紧密放置在一起,由此增加了多条导线交叉的风险。
【0004】导线直径的减小(其增加了导线的电感),可带来若干种额外的不利情况。例如,为使IC正确运行,增加的导线电感可能需要增加功率和接地连接的数目。而功率和接地连接数目的增加又会限制可用于I/O连接的管芯空间量。为了维持高性能级别,I/O连接可落于衬底上,由此使可用的衬底布线面积减少。
发明内容
【0005】利用多条导线来连接管芯接合垫和接合柱的方法可解决上面指出的大部分问题。一个示例性实施例可以包括,接合第一导线至单管芯接合垫以形成第一接合,接合第一导线至接合柱以形成第二接合,接合第二导线至第一接合,并耦合第二导线至接合柱。
附图说明
【0006】图1a-1d示出了根据本发明的实施例,在管芯和衬底接合指之间形成引线接合。
【0007】图2a-2c说明了适合图1a-1d所示的接合垫至管芯连接的各种工艺过程。
【0008】图3a-3c说明了接合垫和接合柱之间导线连接的替代性实施例。
【0009】图4说明了关于图3a-3d的实施例的工艺过程。
【0010】图5a-5c示出了在多个管芯之间的接合垫上形成引线接合连接的替代性实施例。
【0011】图6示出了关于图5a-5d的实施例的工艺过程。
【0012】图7a-7c示出了在多个管芯之间的接合垫上形成引线接合连接的另一个实施例。
【0013】图8示出了关于图7a-7c的实施例的工艺过程。
【0014】某些术语在下文和权利要求书中用来指代特定的***组件。本领域技术人员可意识到,各个公司可能会用不同的名字来指代同一组件。本文并无意区分名字不同而功能相同的组件。在下面的讨论中,以及在权利要求中,术语“包括”和“包含”是以开放式的方式来使用的,因此应该被解释为“包括但并不限于…”,同样,术语“耦合”用来表示间接或直接的电连接。因此,如果第一设备耦合于第二设备,则这种连接可以通过直接电连接,或通过其他设备和连接来间接地电连接。术语“接合或焊点(bond)”和“引线接合或丝焊(wirebond)”用作名词时表示两个或更多实体的电连接。术语“接合(bond)”用作动词表示上文定义的接合的实现。而且,术语“接合柱或焊柱(bondpost)”可以和术语“接合指或焊指(bond finger)”和/或任意通常使用的同义术语替换使用。术语“外部管芯垫(outer die pad)”,“接合垫或焊盘(bond pad)”,“管芯接合垫(die bond pad)”以及“外部管芯接合垫(outerdie bond pad)”也可以替换使用。
具体实施方式
【0015】下面的讨论涉及本发明的各个实施例。本领域技术人员应该理解,下面的描述具有广泛的应用,并且对任何实施例的讨论仅仅是那个实施例的示例。
【0016】这里给出的技术用来在现有接合的顶上建立多个球形接合,同时对IC可靠性仅有最小的影响。这些技术增加了管芯(die)上I/O连接的数目,而不会造成先前提到的一些或所有困难。根据本发明的各种优选实施例,通过利用支架型针脚引线接合技术(Stand Off StitchWirebond technology,SSB)(或者其他合适的接合技术)来连接多个接合,并增加在这些接合之间的导线总数,下面接着要给出的技术增加(相对于单导线连接的横截面积)了每条导线连接的横截面积。这种导线横截面积的增加,减小了连接阻抗,改善了连接电感,并允许在不损失性能质量的情况下,在大小固定的管芯上增加I/O连接数目。
【0017】图1a和1b示出了一个示例性实施例,图2a示出了与这个实施例相关联的工艺过程。图1a和1b示出了包括一对管芯100和102的IC封装件96。每个管芯包括一个或多个外部管芯垫98。外部管芯垫98和外部管芯垫88用来提供管芯上形成的电路与IC封装件96外部的设备之间的电连通性。IC封装件96还包括多个接合柱104。每个接合柱104可以电连接于一个或多个外部管芯垫98或一个或多个外部管芯垫88。接合柱的目的是帮助在外部设备和管芯的外部管芯垫之间建立连接。在图1a的例子中,在IC封装件96内的导线109将管芯垫98之一互连至接合柱104之一。这样,导线109的一端接合于管芯垫98,导线109的另一端接合于接合柱104。在至少一些实施例中,外部管芯垫98的大小可以被设计成,使得可以在管芯102上形成所需数目的外部管芯垫98。
【0018】现在参考图1a和2a,优选的工艺过程开始于建立低环引线接合(low loop wirebond)(图2a中的块200),其中导线109连接在接合柱104和外部管芯垫98之间。更具体地,楔形接合106形成于接合柱104上,由此电子联接导线109至接合柱104。而且,球形接合108形成于外部管芯垫98上,由此电子联接导线109的另一端至外部管芯垫98。因此,电流路径在外部管芯垫98和接合柱104之间形成。在其他实施例中,任何类型的接合可以用于楔形接合106和/或球形接合108。例如,可根据需要用球形结合替代楔形结合。而且,许多环形轮廓中任意一个(即物理导线布置)可以用来实现根据需要改变角度和形状的导线。
【0019】在如图1a所示接合导线109就位后,如图1b所示和图2a的块202中所描述的,使第二导线111接合就位。在至少一个实施例中,利用SSB技术或其他合适的接合技术,导线111被接合就位。更具体地,该工艺过程包括在接合柱104上形成球形接合110,以及在球形接合108的顶上形成楔形接合112。在图1b的实施例中,导线109和111粘附于接合柱104上的两个独立位置上,同时导线109和111粘附于外部管芯垫98上的相同位置。而且,由于是用两条导线将接合垫98连接至接合柱104,结合的导线109和111的横截面积比仅用一条导线时大,这有效地减小了接合垫98和接合柱104之间的阻抗。因为管芯之间的低导线高度要求,所公开的技术可用于层叠管芯IC。
【0020】图1c说明了一个替代性实施例,其中粘附于接合柱104的导线109和111的末端被粘附于接合柱104上的一个共同位置,而不是如图1b所示的两个独立位置。在图1c中描述的技术也在图2b中描述,并且包括建立低环引线接合(块250),其中导线109在利用楔形接合106的接合柱104和利用球形接合108的外部管芯垫98之间接合就位,如上面所描述的以及如图1a所示出的。在块252中,球形接合或任意合适类型的接合可以如图1c所示建立,其中导线111被接合就位。更具体地,通过在楔形接合106上形成的球形接合110,导线111的一端粘附于接合柱104。通过在球形接合108的顶上形成楔形接合112,导线111的另一端粘附于外部管芯柱98。
【0021】图1d又说明了另一个替代性实施例,其与图1c所示的实施例除了附加导线113接合于接合柱104和楔形接合112外,几乎相同。图1d所描述的技术也在图2c中示出,并且包括建立低环引线接合(块276),其中导线109在利用楔形接合106的接合柱104和利用球形接合108的外部管芯垫98之间接合就位,如上面描述的和如图1a所示出的。在块278中,球形接合110或者类似的接合(例如,SSB技术)则可以如图1c所示建立,其中导线111如上所述地接合就位。在块280中,通过楔形接合116将导线113的一端粘附于结合柱104。通过在楔形接合112的顶上形成的球形接合114,导线113的另一端粘附于外部管芯垫98,如图1d所示。以这种方式,连接外部管芯垫98和接合柱104的导线的横截面积,比只有导线之一使用时的横截面积更大,充分地减少了导线阻抗,增加了传导率,并减少IC设计和制造成本。以这种方式,通过接合任意数目的导线至外部管芯垫98和接合柱104,可以提高性能。
【0022】图3a-3c说明了另一种这样的技术,其中图3a与图1a大致相同,以方便下文的讨论。图3a-3c每一个都示出了包括多个接合柱104的IC96,以及堆叠在包括多个外部管芯垫98的管芯102上面的管芯100。图3a-3c所描述的技术也在图4中说明,并且包括在外部管芯垫98上建立球形接合302,以及去除附连于球形接合302的导线(块400)。在块402中,球形接合304可以在接合柱104上形成,并且通过导线303,连接于在球形接合302的顶上形成的楔形接合310,如图3b所示。在块404中,通过楔形接合306,导线305可以粘附于接合柱104,并且通过形成于楔形接合顶上的球形接合308,粘附于外部管芯垫98。就像先前提到的,所公开的范围并不仅限于上面描述的接合类型。接合类型可以自由的根据需要变换。例如,在另一个实施例中,通过利用球形接合而结合于接合柱104并且利用任意类型的接合(未示出)而接合于楔形接合310的导线305,块404可以包括电连接接合柱104和接合垫98。
【0023】在一个例子中,外部管芯垫98是这样的大小,使得最大0.8mm直径导线可以接合于外部管芯垫98。具有比0.8mm更大的直径的导线一般不会使用,因为这种导线会接触附近导线或外部管芯垫98,造成短路电路,并危及IC 96的功能的完整性。因为1mm直径导线被认为是标准尺寸导线,更小的0.8mm直径导线比标准尺寸导线具有更大的电感。但是,实现上面描述的任意一种技术,会造成连接外部管芯垫98到接合柱104的导线的总横截面积,比连接外部管芯垫98至接合柱104的单导线的横截面积更大。因此,导线的总电感可能等于或高于0.8mm导线的电感,或者甚至1mm导线的电感。同样地,导线的阻抗基本上可低于单导线的阻抗,由此允许更大量的电流在外部管芯垫98和接合柱104之间传送。
【0024】这里公开的技术并不仅限于接合管芯垫至接合柱。这种多接合技术还可以用于连接管芯接合垫至其他管芯接合垫的导线,如图5a-5c所示。图5a-5c中每一个都示出了包括叠在管芯102顶上的管芯100的IC 96。管芯100包括多个外部管芯垫88,并且管芯102包括多个拉长的外部管芯垫99。图5a-5c所图示的技术也在图6中说明,并且包括在外部管芯垫88上形成球形接合500,以及去除附连于球形接合500的导线(块600)。在块602,通过球形接合502,导线603粘附于外部管芯垫99,通过在球形接合500上形成的楔形接合504,粘附于外部管芯垫88,如图5b所示。在块604中,通过形成于外部管芯垫99顶上的球形接合506,导线605可以粘附于外部管芯垫99,通过形成于楔形接合504顶上的楔形接合508,粘附于外部管芯垫88,如图5c所示。在至少一些实施例中,任意数目的导线可以接合或者以其它方式电连接至外部管芯垫88和外部管芯垫99。公开的范围并不仅限于先前描述的接合的类型;根据需要,接合类型可以用多种接合类型中任意一些代替。
【0025】另一个管芯至管芯双接合技术在图7a-7c中说明。图7a-7c中每一个都示出了IC 96,其包括堆叠在管芯102顶上的管芯100。管芯100包括多个外部管芯垫88,并且管芯102包括多个外部管芯垫98。图7a-7c所示的技术也在图8中说明,并且包括接合SSB球形接合700或其他合适的接合,至管芯102的外部管芯垫98,以及,去除导线,从而在接合垫98上只留下球形接合700(块800)。然后第二球形接合702接合于管芯100的外部管芯垫88,并且通过导线706被电连接于形成于球形接合700顶上的楔形接合704(块802)。最后,球形接合708接合于球形接合702,并且通过导线712电连接于一个楔形接合710,楔形接合710形成于楔形接合704的顶上(块804)。
【0026】本文公开的主题内容可以应用于单导线或多导线。虽然上述实施例描述了特定类型的接合,任意类型的接合可以被特殊接合代替(例如,球形接合替代楔形接合)。上文描述的所有接合和双接合,可以利用任意接合技术建立,诸如SD引线接合环和它的任意变形(例如,所有低环和超低环接合技术,其包括SSB接合,楔形接合,UL接合,蜗牛接合(escargot bonds)、FJ环接合,以及折叠环接合)。例如,上面描述的楔形接合可以用蜗牛接合替代。各种变形和改进对于本领域技术人员来说是明显的。
Claims (24)
1.一种方法,包括:
接合第一导线至单管芯接合垫,以形成第一接合;
接合所述第一导线至接合柱,以形成第二接合;
接合第二导线至所述第一接合;以及
耦合所述第二导线至所述接合柱。
2.根据权利要求1所述的方法,其中耦合所述第二导线包括接合所述第二导线至所述第二接合。
3.根据权利要求1所述的方法,其中接合包括利用支架型针脚引线接合技术SSB。
4.根据权利要求1所述的方法,其中耦合所述第二导线包括接合所述第二导线至所述接合柱。
5.根据权利要求4所述的方法,进一步包括,接合第三导线至所述接合柱以及通过接合所述第二导线至所述第一接合所形成的接合。
6.根据权利要求1所述的方法,进一步包括:
在接合所述第二导线之前,去除所述第一导线的至少一些;
接合所述第二导线至所述第一接合,以形成第三接合;
接合所述第二导线至所述接合柱;以及
接合第三导线至所述接合柱以及所述第三接合。
7.根据权利要求6所述的方法,其中接合包括形成一组接合中的任意一种,其中这组接合包括楔形接合、球形接合、环接合、以及折叠环接合。
8.根据权利要求1所述的方法,进一步包括利用三条和更多导线,电连接所述第一接合至所述接合柱,每条导线电连接于所述第一接合和所述接合柱。
9.一种方法,包括:
接合第一导线至第一管芯垫,以形成第一接合;
去除所述导线的至少一部分;
接合第二导线至所述第二管芯垫,以形成第二接合;以及
接合所述第二导线至所述第一接合,以形成第三接合。
10.根据权利要求9所述的方法,进一步包括接合第三导线至所述第二接合和所述第三接合。
11.根据权利要求9所述的方法,进一步包括利用三条或更多的导线电连接所述第二接合和所述第三接合,每条导线电连接于所述第二接合和所述第三接合。
12.根据权利要求9所述的方法,其中接合包括利用支架型针脚引线接合技术。
13.一种集成电路封装件,包括:
接合指;以及
管芯接合垫,其利用多条导线耦合于所述接合指,每条导线电连接于所述接合指和所述管芯接合垫。
14.根据权利要求13所述的封装件,其中每条导线利用一组接合中的任意一种电连接于所述接合指和所述管芯接合垫,其中这组接合包括楔形接合、球形接合、环接合、以及折叠环接合。
15.根据权利要求13所述的封装件,其中第一导线利用第一楔形接合被接合于所述接合指,并且利用第一球形接合被接合于所述管芯接合垫。
16.根据权利要求15所述的封装件,其中第二导线利用第二球形接合被接合于所述接合指,并且利用第二楔形接合被接合于所述第一球形接合。
17.根据权利要求15所述的封装件,其中第二导线利用第二球形接合被接合于所述第一楔形接合,并且利用第二楔形接合被接合于所述第一球形接合。
18.根据权利要求17所述的封装件,其中第三导线利用第三楔形接合被接合于所述接合指,并利用第三球形接合被接合于所述第二楔形接合。
19.根据权利要求13所述的封装件,其中第一导线利用球形接合被接合于所述接合指,并利用第一楔形接合被接合于在所述管芯接合垫顶上的现有接合。
20.根据权利要求19所述的封装件,其中,第二导线利用第二楔形接合被接合于所述接合指,并利用球形接合被接合于所述第一楔形接合。
21.一种集成电路封装件,其包括:
第一管芯,其包括第一接合垫;以及
第二管芯,其包括第二接合垫,所述第二接合垫利用多条导线电连接于所述第一接合垫,每条导线接合于所述第一接合垫和所述第二接合垫。
22.根据权利要求21所述的封装件,其中第一导线利用第一球形接合被接合于所述第一接合垫,并利用第一楔形接合被接合于所述第二接合垫顶上的现有接合。
23.根据权利要求22所述的封装件,其中第二导线利用第二球形接合被接合于所述第一球形接合,并且利用第二楔形接合被接合于所述第一楔形接合。
24.根据权利要求21所述的封装件,其中所述第二管芯被堆叠在所述第一管芯的顶上。
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US10/850,495 | 2004-05-20 | ||
US10/850,495 US7078808B2 (en) | 2004-05-20 | 2004-05-20 | Double density method for wirebond interconnect |
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US (2) | US7078808B2 (zh) |
JP (1) | JP2007538412A (zh) |
KR (1) | KR100911778B1 (zh) |
CN (1) | CN1957463A (zh) |
WO (1) | WO2005114731A2 (zh) |
Cited By (2)
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CN103370785A (zh) * | 2010-12-17 | 2013-10-23 | 泰塞拉公司 | 具有中心触点的增强堆叠微电子组件 |
CN103500736A (zh) * | 2013-08-22 | 2014-01-08 | 上海宏力半导体制造有限公司 | 芯片封装结构和芯片封装方法 |
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DE102006025867A1 (de) * | 2006-06-02 | 2007-12-06 | Robert Bosch Gmbh | Bondverbindung sowie Verfahren zum Bonden zweier Kontaktflächen |
JP5481769B2 (ja) * | 2006-11-22 | 2014-04-23 | 日亜化学工業株式会社 | 半導体装置及びその製造方法 |
US20080246129A1 (en) * | 2007-04-04 | 2008-10-09 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing semiconductor device and semiconductor device |
DE102008001671A1 (de) * | 2008-05-09 | 2009-11-12 | Robert Bosch Gmbh | Elektrische Bondverbindungsanordnung |
JP5062283B2 (ja) | 2009-04-30 | 2012-10-31 | 日亜化学工業株式会社 | 半導体装置及びその製造方法 |
US8008785B2 (en) | 2009-12-22 | 2011-08-30 | Tessera Research Llc | Microelectronic assembly with joined bond elements having lowered inductance |
US8553420B2 (en) | 2010-10-19 | 2013-10-08 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
US8928153B2 (en) | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
US8338963B2 (en) | 2011-04-21 | 2012-12-25 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8304881B1 (en) | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
US8633576B2 (en) | 2011-04-21 | 2014-01-21 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US9013033B2 (en) | 2011-04-21 | 2015-04-21 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8952516B2 (en) | 2011-04-21 | 2015-02-10 | Tessera, Inc. | Multiple die stacking for two or more die |
JP2014011396A (ja) * | 2012-07-02 | 2014-01-20 | Aoi Electronics Co Ltd | 半導体装置の実装構造および半導体装置の実装方法 |
KR101963314B1 (ko) | 2012-07-09 | 2019-03-28 | 삼성전자 주식회사 | 반도체 패키지 및 이의 제조 방법 |
US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
JP2018110169A (ja) * | 2016-12-28 | 2018-07-12 | 富士電機株式会社 | 半導体装置および半導体装置製造方法 |
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JP2856220B2 (ja) * | 1991-01-22 | 1999-02-10 | 松下電器産業 株式会社 | 電子チップ部品の製造方法及びボンディング方法 |
JP3631120B2 (ja) * | 2000-09-28 | 2005-03-23 | 沖電気工業株式会社 | 半導体装置 |
JP4804643B2 (ja) * | 2001-05-08 | 2011-11-02 | 三菱電機株式会社 | 高周波回路装置とその製造方法 |
JP2003249606A (ja) * | 2002-02-25 | 2003-09-05 | Sony Corp | 半導体装置及びインターポーザー |
SG148877A1 (en) * | 2003-07-22 | 2009-01-29 | Micron Technology Inc | Semiconductor substrates including input/output redistribution using wire bonds and anisotropically conductive film, methods of fabrication and assemblies including same |
-
2004
- 2004-05-20 US US10/850,495 patent/US7078808B2/en not_active Expired - Lifetime
-
2005
- 2005-05-20 CN CNA2005800161144A patent/CN1957463A/zh active Pending
- 2005-05-20 JP JP2007527457A patent/JP2007538412A/ja not_active Abandoned
- 2005-05-20 WO PCT/US2005/017652 patent/WO2005114731A2/en active Application Filing
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- 2006-05-24 US US11/440,342 patent/US7655552B2/en active Active
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN103370785A (zh) * | 2010-12-17 | 2013-10-23 | 泰塞拉公司 | 具有中心触点的增强堆叠微电子组件 |
US9461015B2 (en) | 2010-12-17 | 2016-10-04 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts |
CN103370785B (zh) * | 2010-12-17 | 2016-11-23 | 泰塞拉公司 | 具有中心触点的增强堆叠微电子组件 |
CN103500736A (zh) * | 2013-08-22 | 2014-01-08 | 上海宏力半导体制造有限公司 | 芯片封装结构和芯片封装方法 |
CN103500736B (zh) * | 2013-08-22 | 2017-04-26 | 上海华虹宏力半导体制造有限公司 | 芯片封装结构和芯片封装方法 |
Also Published As
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US7655552B2 (en) | 2010-02-02 |
US7078808B2 (en) | 2006-07-18 |
WO2005114731A3 (en) | 2006-06-01 |
US20050258538A1 (en) | 2005-11-24 |
KR100911778B1 (ko) | 2009-08-12 |
US20060208359A1 (en) | 2006-09-21 |
KR20070029749A (ko) | 2007-03-14 |
JP2007538412A (ja) | 2007-12-27 |
WO2005114731A2 (en) | 2005-12-01 |
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