CN103985695B - 一种扇出型封装结构及其制作工艺 - Google Patents
一种扇出型封装结构及其制作工艺 Download PDFInfo
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- CN103985695B CN103985695B CN201410211122.5A CN201410211122A CN103985695B CN 103985695 B CN103985695 B CN 103985695B CN 201410211122 A CN201410211122 A CN 201410211122A CN 103985695 B CN103985695 B CN 103985695B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 238000004806 packaging method and process Methods 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 93
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052802 copper Inorganic materials 0.000 claims abstract description 38
- 239000010949 copper Substances 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 229910000679 solder Inorganic materials 0.000 claims abstract description 8
- 238000009713 electroplating Methods 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 26
- 238000005516 engineering process Methods 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 4
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 125000000962 organic group Chemical group 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 238000003825 pressing Methods 0.000 abstract description 3
- 230000017525 heat dissipation Effects 0.000 abstract 1
- 238000002844 melting Methods 0.000 abstract 1
- 230000008018 melting Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 238000005538 encapsulation Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000446313 Lamella Species 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- -1 referring to Fig. 8 Substances 0.000 description 1
- 238000002407 reforming Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410211122.5A CN103985695B (zh) | 2014-05-19 | 2014-05-19 | 一种扇出型封装结构及其制作工艺 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410211122.5A CN103985695B (zh) | 2014-05-19 | 2014-05-19 | 一种扇出型封装结构及其制作工艺 |
Publications (2)
Publication Number | Publication Date |
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CN103985695A CN103985695A (zh) | 2014-08-13 |
CN103985695B true CN103985695B (zh) | 2017-07-25 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201410211122.5A Active CN103985695B (zh) | 2014-05-19 | 2014-05-19 | 一种扇出型封装结构及其制作工艺 |
Country Status (1)
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CN (1) | CN103985695B (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104966677B (zh) * | 2015-07-08 | 2018-03-16 | 华进半导体封装先导技术研发中心有限公司 | 扇出型芯片封装器件及其制备方法 |
CN105161466B (zh) * | 2015-07-08 | 2018-04-17 | 华进半导体封装先导技术研发中心有限公司 | 高功率器件扇出型封装结构及生产工艺 |
CN105590906B (zh) * | 2016-01-11 | 2019-02-01 | 江苏科技大学 | 一种用于扇出式圆片级封装的散热构件及制造方法 |
CN105957836A (zh) * | 2016-06-01 | 2016-09-21 | 格科微电子(上海)有限公司 | 半导体器件的扇出型晶圆级封装方法 |
CN106129023A (zh) * | 2016-08-30 | 2016-11-16 | 华天科技(昆山)电子有限公司 | 双面贴装的扇出封装结构及封装方法 |
KR102185706B1 (ko) * | 2017-11-08 | 2020-12-02 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
CN109309064A (zh) * | 2018-08-10 | 2019-02-05 | 北京嘉楠捷思信息技术有限公司 | 芯片器件、电路板及数字货币挖矿机 |
CN112151469A (zh) * | 2020-09-21 | 2020-12-29 | 青岛歌尔微电子研究院有限公司 | 一种散热封装结构及其制备方法、以及电子器件 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1452245A (zh) * | 2002-04-19 | 2003-10-29 | 富士通株式会社 | 半导体器件及其制造方法 |
CN1971862A (zh) * | 2005-11-25 | 2007-05-30 | 全懋精密科技股份有限公司 | 芯片埋入半导体封装基板结构及其制法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012074497A (ja) * | 2010-09-28 | 2012-04-12 | Denso Corp | 回路基板 |
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2014
- 2014-05-19 CN CN201410211122.5A patent/CN103985695B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1452245A (zh) * | 2002-04-19 | 2003-10-29 | 富士通株式会社 | 半导体器件及其制造方法 |
CN1971862A (zh) * | 2005-11-25 | 2007-05-30 | 全懋精密科技股份有限公司 | 芯片埋入半导体封装基板结构及其制法 |
Also Published As
Publication number | Publication date |
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CN103985695A (zh) | 2014-08-13 |
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Effective date of registration: 20180530 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Institute of Microelectronics of the Chinese Academy of Sciences Address before: 100029 Microelectronics Institute, Chinese Academy of Sciences, 3 north earth road, Chaoyang District, Beijing Co-patentee before: National Center for Advanced Packaging Co.,Ltd. Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
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Effective date of registration: 20180710 Address after: 221000 the east side of Gaoxin Road, Xuzhou economic and Technological Development Zone, Jiangsu, and the south side of Chuang Chuang road. Patentee after: JIANGSU ZHONGKE ZHIXIN INTEGRATION TECHNOLOGY Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
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Effective date of registration: 20180815 Address after: 221000 the east side of Gaoxin Road, Xuzhou economic and Technological Development Zone, Jiangsu, and the south side of Chuang Chuang road. Patentee after: JIANGSU ZHONGKE ZHIXIN INTEGRATION TECHNOLOGY Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Beijing Zhongke micro Investment Management Co.,Ltd. Effective date of registration: 20180815 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences Effective date of registration: 20180815 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Institute of Microelectronics of the Chinese Academy of Sciences Address before: 221000 the east side of Gaoxin Road, Xuzhou economic and Technological Development Zone, Jiangsu, and the south side of Chuang Chuang road. Patentee before: JIANGSU ZHONGKE ZHIXIN INTEGRATION TECHNOLOGY Co.,Ltd. |