CN103312130A - Bidirectional thyristor trigger circuit and method - Google Patents
Bidirectional thyristor trigger circuit and method Download PDFInfo
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Abstract
The invention provides bidirectional thyristor trigger circuit and method. The circuit comprises a full-wave rectifier unit, a direct-current voltage-stabilized power unit, a zero-crossing synch pulse generation unit, an input signal photoelectric isolation unit, a phase shift trigger unit, and a bidirectional thyristor master circuit unit. According to the method, phase shifting is achieved by directly counting of input phase shift control frequency signals with a counter, and phase can be shifted by changing the input phase shift control frequency signals; the phase shift control signals input to the counter are subjected to photoelectric isolation and Schmitt rectification. The circuit is low in cost, small in size, stable and reliable in operation, and applicable as alternating-current voltage regulating switches in automatic control systems.
Description
Technical field
The invention belongs to the thyristor gating circuit technical field, particularly a kind of Bidirectional thyristor trigger circuit and method.
Background technology
Device parameters is comparatively disperseed in the traditional analog trigger, debugging and use inconvenience, and poor reliability, power consumption is high, and price is high; Use analog signal to carry out phase shifting control, control signal transmission poor anti jamming capability.
The conventional digital trigger adopts microcontroller as control core, and function is strong, but its price is high, easily causes program fleet out of control when running into strong jamming.
Application number is the patent " a kind of Bidirectional thyristor trigger circuit and method " of CN201010529936.5, adopt PWM as the input phase-shifted control signal, circuit is simple, cost is low, but pwm signal need to convert direct voltage to by filter circuit, conversion accuracy is not high, and this circuit uses diac as the trigger comparator part, and phase shifting angle hour minimum phase shifting angle is wayward, triggers poor stability when phase shifting angle is large.
Summary of the invention
One of purpose of the present invention is to overcome the shortcoming of above-mentioned prior art with not enough, provide a kind of rational in infrastructure, price is low, debugging is simple, reliability is high, can carry out by the input different frequency signals Bidirectional thyristor trigger circuit of phase shifting control, may be used on serving as in the automatic control system AC voltage adjusting switch.
Another object of the present invention is to provide the bidirectional thyristor triggering method that is realized by above-mentioned Bidirectional thyristor trigger circuit.
Technical scheme of the present invention is: a kind of Bidirectional thyristor trigger circuit is comprised of full-wave rectification unit, D.C. regulated power supply unit, zero passage lock-out pulse generation unit, input signal photoelectricity isolated location, phase-shift trigger unit, bidirectional thyristor main circuit unit.
Described full-wave rectification unit is provided with the first ac input end, the second ac input end, full-wave direct current voltage output end, commutating voltage negative output terminal; The common reference ground that described commutating voltage negative output terminal is described Bidirectional thyristor trigger circuit; Described the first ac input end is connected to the AC power phase line, and described the second ac input end is connected to the AC power zero line.
Described D.C. regulated power supply unit is provided with full-wave direct current voltage input end, dc power output end; Described full-wave direct current voltage input end is connected to the full-wave direct current voltage output end of described full-wave rectification unit.
Described zero passage lock-out pulse generation unit is provided with full-wave direct current voltage input end, zero passage lock-out pulse output; Described full-wave direct current voltage input end is connected to the full-wave direct current voltage output end of described full-wave rectification unit.
Described input signal photoelectricity isolated location is provided with phase shifting control frequency signal input end, dc supply input, phase shifting control frequency signal output; Described dc supply input is connected to the dc power output end of described D.C. regulated power supply unit.
Described phase-shift trigger unit is provided with zero passage clock terminal, phase shifting control frequency signal input end, dc supply input, the first triggering signal output, the second triggering signal output; Described zero passage clock terminal is connected to the zero passage lock-out pulse output of described zero passage lock-out pulse generation unit, and described dc supply input is connected to the dc power output end of described D.C. regulated power supply unit.
Described phase-shift trigger unit triggers driver by counter, the first NAND gate, the second NAND gate, the 3rd NAND gate, the 4th NAND gate, the first resistance, the second resistance, the isolation of phase shift type photoelectricity and forms.
Wherein,
Described phase shift type photoelectricity isolation triggers internal drive and comprises the first light-emitting diode, optical controlled bidirectional thyrister, and the outside comprises that the control electric current flows into end, control outflow of bus current end, the first phase shifting control output, the second phase shifting control output.
Described counter has frequency signal input end, carry signal output, reset signal input, power supply positive input terminal, power-input; The power supply positive input terminal of described counter is connected to described dc supply input, and the power-input of described counter is connected to described common reference ground.
Be connected to the zero passage clock terminal of described phase-shift trigger unit, the reset signal input that output is connected to described counter after two input parallel connections of described the first NAND gate; An input of described the second NAND gate is connected to the phase shifting control frequency signal input end of described phase-shift trigger unit, and another input is connected to the output of described the 4th NAND gate; Be connected to the output of described the second NAND gate after two input parallel connections of described the 3rd NAND gate, the output of described the 3rd NAND gate is connected to the frequency signal input end of described counter; Be connected to the carry signal output of described counter after two input parallel connections of described the 4th NAND gate; The output of described the 4th NAND gate also is connected to the control outflow of bus current end that described phase shift type photoelectricity isolation triggers driver except an input that is connected to described the second NAND gate; The control electric current that described phase shift type photoelectricity isolation triggers driver flows into the end that end is connected to described the first resistance, and the other end of described the first resistance is connected to described dc supply input; Described the first phase shifting control output be connected to described the first triggering signal output after described the second resistance is connected, described the second phase shifting control output is connected to described the second triggering signal output.
Described bidirectional thyristor main circuit unit is comprised of bidirectional thyristor and load; The first electrode of described bidirectional thyristor is connected to the phase line of AC power and the second triggering signal output of described phase-shift trigger unit simultaneously; The control utmost point of described bidirectional thyristor is connected to the first triggering signal output of described phase-shift trigger unit; The second electrode of described bidirectional thyristor is connected to the zero line of AC power with after described load is connected.
Described full-wave rectification unit is comprised of the first diode, the second diode, the 3rd diode, the 4th diode, described the first ac input end is the tie-point of described the first diode anode and described the 3rd diode cathode, described the second ac input end is the tie-point of described the second diode anode and described the 4th diode cathode, described full-wave direct current voltage output end is the tie-point of described the first diode cathode and described the second diode cathode, and described commutating voltage negative output terminal is the tie-point of described the 3rd diode anode and described the 4th diode anode.
Described D.C. regulated power supply unit is comprised of the 5th diode, the first electric capacity, the 3rd resistance, the first voltage-stabiliser tube, described the 5th diode anode is connected to described full-wave direct current voltage input end, described the 5th diode cathode and described the first capacitance cathode end, the 3rd resistance one client link are together, described the first electric capacity negative polarity end is connected to described common reference ground, an other end of described the 3rd resistance and described the first voltage-stabiliser tube negative electrode are connected to described dc power output end after connecting, and described the first voltage-stabiliser tube anodic bonding is to described common reference ground.
Described zero passage lock-out pulse generation unit is comprised of the 4th resistance, the 5th resistance, the second voltage-stabiliser tube, one end of described the 4th resistance is connected to described full-wave direct current voltage input end, one end of an other end of described the 4th resistance, described the 5th resistance and described the second voltage-stabiliser tube negative electrode are connected to described zero passage lock-out pulse output after connecting, and an other end of described the 5th resistance and described the second voltage-stabiliser tube anodic bonding are to described common reference ground.
Described input signal photoelectricity isolated location is comprised of switching mode photoelectrical coupler, the 6th resistance, the 7th resistance; Described switching mode photoelectrical coupler inside comprises the second light-emitting diode, light-operated triode, and the outside comprises the reception input, receives output, exports collector terminal, exports emitter terminal; After described the 7th resistance, switching mode photoelectrical coupler reception input, reception output are connected in series successively, be connected to the phase shifting control frequency signal input end of described input signal photoelectricity isolated location; Described output emitter terminal is connected to described common reference ground, be connected to the phase shifting control frequency signal output of described input signal photoelectricity isolated location behind one client link of described output collector terminal and described the 6th resistance, the other end of described the 6th resistance is connected to described dc supply input.
Described the first NAND gate, the second NAND gate, the 3rd NAND gate, the 4th NAND gate adopt with 4 two in the integrated NAND gate circuit of a slice CMOS independent NAND gate of input, and the power supply positive input terminal of the integrated NAND gate circuit of described CMOS is connected to described common reference ground with being connected to described dc supply input, power supply.
Described counter is for using CD4040 to consist of
NThe system up counter.
Bidirectional thyristor triggering method by foregoing circuit is realized comprises:
The full-wave rectification unit that is comprised of the first diode, the second diode, the 3rd diode, the 4th diode is rectified into full-wave direct current voltage with AC power; The bleeder circuit dividing potential drop that full-wave direct current voltage forms through the 4th resistance, the 5th resistance, and by behind the second voltage-stabiliser tube amplitude limit, obtain the zero passage synchronization pulse; Described zero passage synchronization pulse is undersuing.
During the AC power zero passage, make on the one hand the bidirectional thyristor cut-off, making on the other hand the zero passage synchronization pulse is low level, this low level through the first NAND gate shaping and anti-phase after, the output high level is to the reset signal input of counter; Reset signal is that high level is effective, makes counter output zero clearing; The carry signal output of counter is low level, and this low level makes the 4th NAND gate output high level; The high level of the 4th NAND gate output is controlled the first light-emitting diode and the optical controlled bidirectional thyrister cut-off that the isolation of phase shift type photoelectricity triggers internal drive on the one hand, do not export triggering signal, control on the other hand the second NAND gate open, make the phase shifting control frequency signal after the second NAND gate, the 3rd NAND gate shaping, deliver to the frequency signal input end of counter.
After the AC power zero passage, the zero passage synchronization pulse becomes high level, and the first not gate output low level is to the reset signal input of counter, when reset signal is low level zero clearing invalid, counter begins the phase shifting control frequency signal of input is counted; When the input of counter frequency signal input part
NBehind the individual count pulse, the carry signal output of counter becomes high level from low level, makes the output of the 4th NAND gate become low level from high level; The low level of the 4th NAND gate output is on the one hand through after the first resistance current limliting, the isolation of control phase shift type photoelectricity triggers the first lumination of light emitting diode of internal drive, its inner optical controlled bidirectional thyrister conducting, after the second resistance current limliting, export triggering signal by the first triggering signal output, the second triggering signal output to bidirectional thyristor, the conducting of control bidirectional thyristor; The low level of the 4th NAND gate output is blocked the second NAND gate on the other hand, make the phase shifting control frequency signal can not deliver to by the second NAND gate the frequency signal input end of counter, the frequency signal input end of counter keeps low level, and the output of counter temporarily remains unchanged and continues to bidirectional thyristor output triggering signal by the first triggering signal output, the second triggering signal output; Until AC power zero passage next time, when the zero passage synchronization pulse became low level again, bidirectional thyristor ended again, and counter is exported again zero clearing, removes triggering signal.
When described counter is
NThe system up counter, the minimum value that described phase shifting angle phase shift range requires is
α Min, maximum is
α MaxThe time, the frequency range of corresponding phase-shifted control signal is
The maximum phase-shifted control signal frequency of corresponding minimum phase shifting angle
f Max=(
N* 180)/(
α Min * 10) kHz;
The minimum phase-shifted control signal frequency of corresponding maximum phase shifting angle
f Min=(
N* 180)/(
α Max * 10) kHz.
Within maximum phase-shifted control signal frequency and minimum phase-shifted control signal frequency range, reduce the frequency of phase-shifted control signal, phase shifting angle increases; Increase the frequency of phase-shifted control signal, phase shifting angle reduces.
Described phase shifting control frequency signal is undertaken delivering to phase-shift trigger unit after the photoelectricity isolation by input signal photoelectricity isolated location again.
Compared with prior art, the present invention has following advantage and beneficial effect:
The core devices of phase shifting control is the CMOS counter, the mode phase shift that usage counter is directly counted the phase shifting control frequency signal of input, and the phase shifting control frequency signal that changes input gets final product phase shift, and principle is simple; The phase-shifted control signal that inputs to counter has carried out the photoelectricity isolation and Schmidt's shaping, reset signal have carried out Schmidt's shaping, working stability, reliably; Cmos nand gate input impedance is high, and the zero passage synchronizing signal can be used 2 large resistance small-power resistance and a voltage-stabiliser tube, directly the interchange all-wave voltage behind the ac voltage rectifier is carried out dividing potential drop and obtains, and need not to use synchrotrans; Circuit power consumption is low, and DC-stabilized circuit is only used 1 diode 1, individual electric capacity, 1 resistance, 14 small-power element such as voltage-stabiliser tube.
Description of drawings
Fig. 1 is the structured flowchart of circuit embodiments of the present invention.
Fig. 2 is the circuit diagram of circuit embodiments of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with embodiment and accompanying drawing, but embodiments of the present invention are not limited to this.
The structured flowchart of a kind of Bidirectional thyristor trigger circuit embodiment is comprised of full-wave rectification unit 100, D.C. regulated power supply unit 200, zero passage lock-out pulse generation unit 300, input signal photoelectricity isolated location 400, phase-shift trigger unit 500, bidirectional thyristor main circuit unit 600 as shown in Figure 1.
The circuit diagram of circuit embodiments of the present invention as shown in Figure 2.
Described full-wave rectification unit 100 is provided with the first ac input end 1, the second ac input end 2, full-wave direct current voltage output end U1, commutating voltage negative output terminal 0; The common reference ground GND that described commutating voltage negative output terminal 0 is described Bidirectional thyristor trigger circuit.Described the first ac input end 1 is connected to AC power phase line L, and described the second ac input end 2 is connected to AC power zero line N.
Described AC power is that voltage is the single phase alternating current power supply of 220V.
Described full-wave rectification unit 100 is comprised of the first diode D1, the second diode D2, the 3rd diode D3, the 4th diode D4, described the first ac input end 1 is the tie-point of the first diode D1 anode and the 3rd diode D3 negative electrode, described the second ac input end 2 is the tie-point of the second diode D2 anode and the 4th diode D4 negative electrode, described full-wave direct current voltage output end U1 is the tie-point of the first diode D1 negative electrode and the second diode cathode D2, and described commutating voltage negative output terminal 0 is the tie-point of the 3rd diode D3 anode and the 4th diode anode D4.
Described D.C. regulated power supply unit 200 is provided with full-wave direct current voltage input end U1, dc power output end U2; Described full-wave direct current voltage input end U1 is connected to the full-wave direct current voltage output end U1 of full-wave rectification unit 100.
Described D.C. regulated power supply unit 200 is by the 5th diode D5, the first capacitor C 1, the 3rd resistance R 3, the first voltage-stabiliser tube DW1 forms, described the 5th diode D5 anodic bonding is to full-wave direct current voltage input end U1, described the 5th diode D5 negative electrode and described the first capacitor C 1 positive ends, the 3rd resistance R 3 one client links together, described the first capacitor C 1 negative polarity end is connected to described common reference ground GND, an other end of described the 3rd resistance R 3 and described the first voltage-stabiliser tube DW1 negative electrode are connected to described dc power output end U2 after connecting, and described the first voltage-stabiliser tube DW1 anodic bonding is to described common reference ground GND.
Described dc power output end U2 output+5V direct voltage.
Described zero passage lock-out pulse generation unit 300 is provided with full-wave direct current voltage input end U1, zero passage lock-out pulse output P1; Described full-wave direct current voltage input end U1 is connected to the full-wave direct current voltage output end U1 of full-wave rectification unit 100.
Described zero passage lock-out pulse generation unit 300 is comprised of the 4th resistance R 4, the 5th resistance R 5, the second voltage-stabiliser tube DW2, one end of described the 4th resistance R 4 is connected to full-wave direct current voltage input end U1, an other end of the 4th resistance R 4 and an end of the 5th resistance R 5, the second voltage-stabiliser tube DW2 negative electrode are connected to zero passage lock-out pulse output P1 after connecting, and an other end of described the 5th resistance R 5, the second voltage-stabiliser tube DW2 anodic bonding are to common reference ground GND.
Described input signal photoelectricity isolated location 400 is provided with phase shifting control frequency signal input end P2, dc supply input U2, phase shifting control frequency signal output P3; Described dc supply input U2 is connected to D.C. regulated power supply unit 200+5V dc power output end U2.
Described input signal photoelectricity isolated location 400 is comprised of switching mode photoelectrical coupler M1, the 6th resistance R 6, the 7th resistance R 7.The present embodiment switching mode photoelectrical coupler M2 selects 4N25.
Described switching mode photoelectrical coupler M2 inside comprises the second LED 2, light-operated triode VT, and the outside comprises reception input 12, receives output 13, exports collector terminal 14, exports emitter terminal 15.
After described the 7th resistance R 7, switching mode photoelectrical coupler reception input 12, reception output 13 are connected in series successively, be connected to phase shifting control frequency signal input end P2.
Described output emitter terminal 15 is connected to common reference ground GND, is connected to phase shifting control frequency signal output P3 behind the client link of described output collector terminal 14 and the 6th resistance R 6, and the other end of described the 6th resistance R 6 is connected to+the 5V DC power supply.
Described phase-shift trigger unit 500 is provided with zero passage clock terminal P1, phase shifting control frequency signal input end P3, dc supply input U2, the first triggering signal output G1, the second triggering signal output G2.
Described zero passage clock terminal P1 is connected to the zero passage lock-out pulse output P1 of zero passage lock-out pulse generation unit 300, described dc supply input U2 be connected to D.C. regulated power supply unit 200+5V dc power output end U2.
Described phase-shift trigger unit 500 triggers driver M1 by counter, the first NAND gate F1, the second NAND gate F2, the 3rd NAND gate F3, the 4th NAND gate F4, the first resistance R 1, the second resistance R 2, the isolation of phase shift type photoelectricity and forms.
Described phase shift type photoelectricity isolation triggers driver M1 inside and comprises the first LED 1, optical controlled bidirectional thyrister V1, and the outside comprises that the control electric current flows into end 8, control outflow of bus current end 9, the first phase shifting control output 11, the second phase shifting control output 10; The isolation of the present embodiment phase shift type photoelectricity triggers driver M1 and selects MOC3023.
Described counter has frequency signal input end CP, carry signal output CO, reset signal input CR, power supply positive input terminal VDD, power-input VSS; The present embodiment counter is 12 binary string linage-counter CD4040, and carry signal output CO is terminal count output Q6, and described power supply positive input terminal VDD is connected to+the 5V DC power supply, and described negative input end VSS is connected to common reference ground GND.
Described the first NAND gate F1, the second NAND gate F2, the 3rd NAND gate F3, the 4th NAND gate F4 adopt with 4 two in the integrated NAND gate circuit of a slice CMOS independent NAND gate of input, and the power supply positive input terminal of the integrated NAND gate circuit of described CMOS is connected to+the 5V DC power supply, be connected to common reference ground GND power supply.The integrated NAND gate circuit of the present embodiment CMOS is the 74HC132 that inputs with Schmidt.
Be connected to the zero passage clock terminal P1 of described phase-shift trigger unit, the reset signal input CR that output is connected to counter after two input parallel connections of described the first NAND gate F1; The input of described the second NAND gate F2 is connected to the output that phase shifting control frequency signal input end P3, another input are connected to described the 4th NAND gate F4; Be connected to the output of the second NAND gate F2 after two input parallel connections of described the 3rd NAND gate F3, the output of described the 3rd NAND gate F3 is connected to the frequency signal input end CP of counter; Be connected to the carry signal output CO of counter after two input parallel connections of described the 4th NAND gate F4; The output of described the 4th NAND gate F4 also is connected to the control outflow of bus current end 9 that described phase shift type photoelectricity isolation triggers driver M1 except the input of described the second NAND gate F2; The control electric current that described phase shift type photoelectricity isolation triggers driver M1 flows into the end that end 8 is connected to the first resistance R 1, and the other end of described the first resistance R 1 is connected to+the 5V DC power supply; Described the first phase shifting control output 11 be connected to the first triggering signal output G1 after the second resistance R 2 is connected, described the second phase shifting control output 10 is connected to the second triggering signal output G2.
Described bidirectional thyristor main circuit unit 600 is comprised of bidirectional thyristor V and load.The first electrode T1 of described bidirectional thyristor V is connected to the phase line L of AC power and the second triggering signal output G2 of described phase-shift trigger unit 500 simultaneously; The control utmost point of described bidirectional thyristor V is connected to the first triggering signal output G1 of described phase-shift trigger unit 500; The second electrode T2 of described bidirectional thyristor V is connected to the zero line N of AC power with after load is connected.
The operation principle of the present embodiment Bidirectional thyristor trigger circuit is:
⑴ zero passage synchronization pulse
The full-wave rectification unit 100 that is comprised of the first diode D1, the second diode D2, the 3rd diode D3, the 4th diode D4 is rectified into full-wave direct current voltage U 1 with the 220V AC power, the road bleeder circuit dividing potential drop through the 4th resistance R 4, the 5th resistance R 5 compositions of U1, and after being maximum+5V by the second voltage-stabiliser tube DW2 amplitude limit, obtain zero passage synchronization pulse P1, P1 is the negative pulse synchronizing signal.
The minimum phase-shift control angle of circuits for triggering can be realized by the negative pulse width that changes zero-crossing pulse, for example, by increasing the 4th resistance R 4 resistances or reducing the voltage ratio that the 5th resistance R 5 resistances remove to reduce bleeder circuit, the negative pulse width of zero-crossing pulse broadens, and it is large that minimum phase-shift control angle becomes; Otherwise increase the voltage ratio of described bleeder circuit, minimum phase-shift control angle reduces.
⑵ D.C. regulated power supply
After another Lu Jingdi five diode D5 isolation of described full-wave direct current voltage U 1, deliver to 1 filtering of the first capacitor C, after the 3rd resistance R 3 current limlitings, obtain stable+5V direct voltage at the first voltage-stabiliser tube DW1, should+the 5V direct voltage as D.C. regulated power supply to 500 power supplies of input signal photoelectricity isolated location 400, phase-shift trigger unit.
⑶ the isolation of input signal photoelectricity
After input signal photoelectricity isolated location 400 will carry out from the phase shifting control frequency signal P2 of other controllers the photoelectricity isolation, from phase shifting control frequency signal output P3 output, deliver to phase-shift trigger unit 500.Between phase shifting control frequency signal P2 high period, after the 7th resistance R 7 current limlitings, inner the second LED 2 of switching mode photoelectrical coupler M2 is luminous and control light-operated triode VT saturation conduction, and phase shifting control frequency signal output P3 is low level; Between phase shifting control frequency signal P2 low period, inner the second LED 2 of switching mode photoelectrical coupler M2 and light-operated triode VT all end, and phase shifting control frequency signal output P3 is high level.Phase shifting control frequency signal P3 and phase shifting control frequency signal P2 single spin-echo, but frequency is identical.
⑷ phase shifting control principle
During 220V AC power zero passage, make on the one hand bidirectional thyristor V cut-off, making on the other hand zero passage synchronization pulse P1 is low level, through the first NAND gate F1 shaping and anti-phase after the output high level to the reset signal input CR of counter, this moment, reset signal CR was effective, counter output zero clearing, the carry signal output CO(Q6 of counter) be low level, make the 4th NAND gate F4 output high level; The high level of the 4th NAND gate F4 output is controlled the first LED 1 and the optical controlled bidirectional thyrister V1 cut-off that the isolation of phase shift type photoelectricity triggers driver M1 inside on the one hand, do not export triggering signal, control on the other hand the second NAND gate F2 open, make phase shifting control frequency signal P3 after the second NAND gate F2, the 3rd NAND gate F3 shaping, deliver to the frequency signal input end CP of counter.
After the 220V AC power zero passage, zero passage synchronization pulse P1 becomes high level, the first not gate F1 output low level is to the reset signal input CR of counter, and this moment, reset signal CR was invalid, and counter begins the phase shifting control frequency signal P3 of input CP input is carried out plus coujnt; Behind 64 count pulses of counter frequency signal input part CP input, the carry signal output CO(Q6 of counter) become high level from low level, make the output of the 4th NAND gate F4 become low level from high level; The low level of the 4th NAND gate F4 output is on the one hand through after the first resistance R 1 current limliting, the first LED 1 of control phase shift type photoelectricity isolation triggering driver M1 inside is luminous, its inner optical controlled bidirectional thyrister V1 conducting, after the second resistance R 2 current limlitings, to bidirectional thyristor V output triggering signal, control the bidirectional thyristor conducting by the first triggering signal output G1, the second triggering signal output G2; The low level of the 4th NAND gate F4 output is blocked the second NAND gate F2 on the other hand, make phase shifting control frequency signal P3 can not deliver to by the second NAND gate F2 the frequency signal input end CP of counter, the frequency signal input end CP of counter keeps low level, the output of counter temporarily remains unchanged, and the first triggering signal output G1, the second triggering signal output G2 continue to bidirectional thyristor V output triggering signal; Until 220V AC power zero passage next time, when zero passage synchronization pulse P1 became low level again, bidirectional thyristor V ended again, and counter is exported again zero clearing, removes triggering signal.
The frequency that changes input phase-shifted control signal P2 can change the triggering phase shifting angle, and when the phase-shifted control signal P2 frequency of input increased, the corresponding cycle reduced, and the time of full 64 count pulses of meter reduces, and triggers phase shifting angle and reduces; When the phase-shifted control signal P2 frequency of input reduced, the corresponding cycle increased, and the time of full 64 count pulses of meter increases, and triggered phase shifting angle and increased.If the minimum phase shifting angle that requires
α Min=30 °, maximum phase shifting angle
α Max=180 °, with minimum phase shifting angle
α MinThe frequency of corresponding maximum input phase-shifted control signal P2 is
f max＝(64×180)/(30×10)＝38.4kHz?；
With maximum phase shifting angle
α MaxThe frequency of corresponding minimum input phase-shifted control signal P2 is
f min＝64/10＝6.4kHz?。
When counter is
NThe system up counter, namely mould is
N, the minimum value that described phase shifting angle phase shift range requires is
α Min, maximum is
α MaxThe time, the frequency range of corresponding phase-shifted control signal P2 is
f max＝(
N×180)/(
α min ×10)?kHz?；
f min＝(
N×180)/(
α max ×10)?kHz?。
⑸ circuits for triggering characteristics
1. the core devices of phase shifting control is the CMOS counter, the mode phase shift that usage counter is directly counted the phase shifting control frequency signal of input, and the phase shifting control frequency signal that changes input gets final product phase shift, and principle is simple; The phase-shifted control signal that inputs to counter has carried out the photoelectricity isolation and Schmidt's shaping, reset signal have carried out Schmidt's shaping, working stability, reliably.
2. cmos nand gate input impedance is high, and the zero passage synchronizing signal can be used 2 large resistance small-power resistance and a voltage-stabiliser tube, directly the interchange all-wave voltage after the rectification of 220V phase voltage is carried out dividing potential drop and obtains, and need not to use synchrotrans.For example, the 4th resistance R 4, the 5th resistance R 5 be value 470k all, the second voltage-stabiliser tube DW2 voltage stabilizing value 5V, and the voltage effective value on the 4th resistance R 4 is 215V, its power consumption is 215 * 215 ÷ 470k=98mW; Voltage on the 5th resistance R 5 is by the second voltage-stabiliser tube DW2 amplitude limit, and power consumption is lower.
3. circuit power consumption is low.The maximum load of D.C. regulated power supply is that the photoelectricity isolation triggers the input control electric current of driver M1 and the saturation current of the light-operated triode VT of switching mode photoelectrical coupler M2, and the rated current of MOC3023 input side the first LED 1 is 5mA; When the 6th resistance R 6 was selected the 10k resistance, the saturation current of light-operated triode VT was 0.5mA; Therefore, the load current of whole D.C. regulated power supply is less than 6mA.
Claims (9)
1. a Bidirectional thyristor trigger circuit is comprised of full-wave rectification unit, D.C. regulated power supply unit, zero passage lock-out pulse generation unit, input signal photoelectricity isolated location, phase-shift trigger unit, bidirectional thyristor main circuit unit, it is characterized in that:
Described full-wave rectification unit is provided with the first ac input end, the second ac input end, full-wave direct current voltage output end, commutating voltage negative output terminal; The common reference ground that described commutating voltage negative output terminal is described Bidirectional thyristor trigger circuit; Described the first ac input end is connected to the AC power phase line, and described the second ac input end is connected to the AC power zero line;
Described D.C. regulated power supply unit is provided with full-wave direct current voltage input end, dc power output end; Described full-wave direct current voltage input end is connected to the full-wave direct current voltage output end of described full-wave rectification unit;
Described zero passage lock-out pulse generation unit is provided with full-wave direct current voltage input end, zero passage lock-out pulse output; Described full-wave direct current voltage input end is connected to the full-wave direct current voltage output end of described full-wave rectification unit;
Described input signal photoelectricity isolated location is provided with phase shifting control frequency signal input end, dc supply input, phase shifting control frequency signal output; Described dc supply input is connected to the dc power output end of described D.C. regulated power supply unit;
Described phase-shift trigger unit is provided with zero passage clock terminal, phase shifting control frequency signal input end, dc supply input, the first triggering signal output, the second triggering signal output; Described zero passage clock terminal is connected to the zero passage lock-out pulse output of described zero passage lock-out pulse generation unit, and described dc supply input is connected to the dc power output end of described D.C. regulated power supply unit;
Described phase-shift trigger unit triggers driver by counter, the first NAND gate, the second NAND gate, the 3rd NAND gate, the 4th NAND gate, the first resistance, the second resistance, the isolation of phase shift type photoelectricity and forms; Wherein,
Described phase shift type photoelectricity isolation triggers internal drive and comprises the first light-emitting diode, optical controlled bidirectional thyrister, and the outside comprises that the control electric current flows into end, control outflow of bus current end, the first phase shifting control output, the second phase shifting control output;
Described counter has frequency signal input end, carry signal output, reset signal input, power supply positive input terminal, power-input; The power supply positive input terminal of described counter is connected to described dc supply input, and the power-input of described counter is connected to described common reference ground;
Be connected to the zero passage clock terminal of described phase-shift trigger unit, the reset signal input that output is connected to described counter after two input parallel connections of described the first NAND gate; An input of described the second NAND gate is connected to the phase shifting control frequency signal input end of described phase-shift trigger unit, and another input is connected to the output of described the 4th NAND gate; Be connected to the output of described the second NAND gate after two input parallel connections of described the 3rd NAND gate, the output of described the 3rd NAND gate is connected to the frequency signal input end of described counter; Be connected to the carry signal output of described counter after two input parallel connections of described the 4th NAND gate; The output of described the 4th NAND gate also is connected to the control outflow of bus current end that described phase shift type photoelectricity isolation triggers driver except an input that is connected to described the second NAND gate; The control electric current that described phase shift type photoelectricity isolation triggers driver flows into the end that end is connected to described the first resistance, and the other end of described the first resistance is connected to described dc supply input; Described the first phase shifting control output be connected to described the first triggering signal output after described the second resistance is connected, described the second phase shifting control output is connected to described the second triggering signal output;
Described bidirectional thyristor main circuit unit is comprised of bidirectional thyristor and load; The first electrode of described bidirectional thyristor is connected to the phase line of AC power and the second triggering signal output of described phase-shift trigger unit simultaneously; The control utmost point of described bidirectional thyristor is connected to the first triggering signal output of described phase-shift trigger unit; The second electrode of described bidirectional thyristor is connected to the zero line of AC power with after described load is connected.
2. a kind of Bidirectional thyristor trigger circuit according to claim 1, it is characterized in that: described full-wave rectification unit is by the first diode, the second diode, the 3rd diode, the 4th diode forms, described the first ac input end is the tie-point of described the first diode anode and described the 3rd diode cathode, described the second ac input end is the tie-point of described the second diode anode and described the 4th diode cathode, described full-wave direct current voltage output end is the tie-point of described the first diode cathode and described the second diode cathode, and described commutating voltage negative output terminal is the tie-point of described the 3rd diode anode and described the 4th diode anode.
3. a kind of Bidirectional thyristor trigger circuit according to claim 2, it is characterized in that: described D.C. regulated power supply unit is by the 5th diode, the first electric capacity, the 3rd resistance, the first voltage-stabiliser tube forms, described the 5th diode anode is connected to described full-wave direct current voltage input end, described the 5th diode cathode and described the first capacitance cathode end, the 3rd resistance one client link together, described the first electric capacity negative polarity end is connected to described common reference ground, an other end of described the 3rd resistance and described the first voltage-stabiliser tube negative electrode are connected to described dc power output end after connecting, and described the first voltage-stabiliser tube anodic bonding is to described common reference ground.
4. a kind of Bidirectional thyristor trigger circuit according to claim 3, it is characterized in that: described zero passage lock-out pulse generation unit is comprised of the 4th resistance, the 5th resistance, the second voltage-stabiliser tube, one end of described the 4th resistance is connected to described full-wave direct current voltage input end, one end of an other end of described the 4th resistance, described the 5th resistance and described the second voltage-stabiliser tube negative electrode are connected to described zero passage lock-out pulse output after connecting, and an other end of described the 5th resistance and described the second voltage-stabiliser tube anodic bonding are to described common reference ground.
5. a kind of Bidirectional thyristor trigger circuit according to claim 4, it is characterized in that: described input signal photoelectricity isolated location is comprised of switching mode photoelectrical coupler, the 6th resistance, the 7th resistance; Described switching mode photoelectrical coupler inside comprises the second light-emitting diode, light-operated triode, and the outside comprises the reception input, receives output, exports collector terminal, exports emitter terminal; After described the 7th resistance, switching mode photoelectrical coupler reception input, reception output are connected in series successively, be connected to the phase shifting control frequency signal input end of described input signal photoelectricity isolated location; Described output emitter terminal is connected to described common reference ground, be connected to the phase shifting control frequency signal output of described input signal photoelectricity isolated location behind one client link of described output collector terminal and described the 6th resistance, the other end of described the 6th resistance is connected to described dc supply input.
6. a kind of Bidirectional thyristor trigger circuit according to claim 5, it is characterized in that: described the first NAND gate, the second NAND gate, the 3rd NAND gate, the 4th NAND gate adopt with 4 two in the integrated NAND gate circuit of a slice CMOS independent NAND gate of input, and the power supply positive input terminal of the integrated NAND gate circuit of described CMOS is connected to described common reference ground with being connected to described dc supply input, power supply.
7. a kind of Bidirectional thyristor trigger circuit according to claim 5 is characterized in that: described counter is for using CD4040 to consist of
NThe system up counter.
8. the bidirectional thyristor triggering method that is realized by each described circuit of claim 1-7 is characterized in that:
The full-wave rectification unit that is comprised of the first diode, the second diode, the 3rd diode, the 4th diode is rectified into full-wave direct current voltage with AC power; The bleeder circuit dividing potential drop that full-wave direct current voltage forms through the 4th resistance, the 5th resistance, and by behind the second voltage-stabiliser tube amplitude limit, obtain the zero passage synchronization pulse; Described zero passage synchronization pulse is undersuing;
During the AC power zero passage, make on the one hand the bidirectional thyristor cut-off, making on the other hand the zero passage synchronization pulse is low level, this low level through the first NAND gate shaping and anti-phase after, the output high level is to the reset signal input of counter; Reset signal is that high level is effective, makes counter output zero clearing; The carry signal output of counter is low level, and this low level makes the 4th NAND gate output high level; The high level of the 4th NAND gate output is controlled the first light-emitting diode and the optical controlled bidirectional thyrister cut-off that the isolation of phase shift type photoelectricity triggers internal drive on the one hand, do not export triggering signal, control on the other hand the second NAND gate open, make the phase shifting control frequency signal after the second NAND gate, the 3rd NAND gate shaping, deliver to the frequency signal input end of counter;
After the AC power zero passage, the zero passage synchronization pulse becomes high level, and the first not gate output low level is to the reset signal input of counter, when reset signal is low level zero clearing invalid, counter begins the phase shifting control frequency signal of input is counted; When the input of counter frequency signal input part
NBehind the individual count pulse, the carry signal output of counter becomes high level from low level, makes the output of the 4th NAND gate become low level from high level; The low level of the 4th NAND gate output is on the one hand through after the first resistance current limliting, the isolation of control phase shift type photoelectricity triggers the first lumination of light emitting diode of internal drive, its inner optical controlled bidirectional thyrister conducting, after the second resistance current limliting, export triggering signal by the first triggering signal output, the second triggering signal output to bidirectional thyristor, the conducting of control bidirectional thyristor; The low level of the 4th NAND gate output is blocked the second NAND gate on the other hand, make the phase shifting control frequency signal can not deliver to by the second NAND gate the frequency signal input end of counter, the frequency signal input end of counter keeps low level, and the output of counter temporarily remains unchanged and continues to bidirectional thyristor output triggering signal by the first triggering signal output, the second triggering signal output; Until AC power zero passage next time, when the zero passage synchronization pulse became low level again, bidirectional thyristor ended again, and counter is exported again zero clearing, removes triggering signal;
When described counter is
NThe system up counter, the minimum value that described phase shifting angle phase shift range requires is
α Min, maximum is
α MaxThe time, the frequency range of corresponding phase-shifted control signal is
The maximum phase-shifted control signal frequency of corresponding minimum phase shifting angle
f Max=(
N* 180)/(
α Min * 10) kHz;
The minimum phase-shifted control signal frequency of corresponding maximum phase shifting angle
f Min=(
N* 180)/(
α Max * 10) kHz;
Within maximum phase-shifted control signal frequency and minimum phase-shifted control signal frequency range, reduce the frequency of phase-shifted control signal, phase shifting angle increases; Increase the frequency of phase-shifted control signal, phase shifting angle reduces.
9. bidirectional thyristor triggering method according to claim 8 is characterized in that: described phase shifting control frequency signal is undertaken delivering to phase-shift trigger unit after the photoelectricity isolation by input signal photoelectricity isolated location again.
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| CN106067790B (en) * | 2016-06-15 | 2021-09-14 | 湖南工业大学 | De-jittering circuit |
| CN106067788B (en) * | 2016-06-15 | 2021-09-14 | 湖南工业大学 | High-frequency interference filtering circuit |
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