CN209151132U - A kind of clock signal missing detecting circuit - Google Patents
A kind of clock signal missing detecting circuit Download PDFInfo
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- CN209151132U CN209151132U CN201821911391.2U CN201821911391U CN209151132U CN 209151132 U CN209151132 U CN 209151132U CN 201821911391 U CN201821911391 U CN 201821911391U CN 209151132 U CN209151132 U CN 209151132U
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- switch
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- clock signal
- current
- phase inverter
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Abstract
A kind of clock signal missing detecting circuit, including first switch, the first end of first switch connect to power supply, and second end is connect with the first end of first capacitor, the first end of second switch respectively, the second end ground connection of first capacitor；The first end of third switch connects to power supply, and second end is connect with the first end of the first end of third capacitor, the 4th switch respectively, the second end ground connection of third capacitor；The second end of second switch is connect after connecting with the second end of the 4th switch with the first end of the second capacitor, the second end ground connection of the second capacitor；The first end of second capacitor and the input terminal of phase inverter connect, the output end output detection signal of phase inverter；Current limit circuit in parallel, the first end of current-limiting circuit are connected on the connecting line between the first end of the second capacitor and the input terminal of phase inverter on second capacitor, the second end ground connection of current-limiting circuit；Second switch, third switch connection control clock signal, first switch, the 4th switch connection control clock inverted signal.
Description
Technical field
The utility model belongs to electronic technology field, and in particular to a kind of clock signal missing detecting circuit.
Background technique
Clock signal is the reference signal of digital integrated electronic circuit and Digital Analog Hybrid Circuits work, may be in circuit system
Portion or external generation.In integrated circuits, clock signal is shaken by inner loop or external crystal-controlled oscillation generates.Since environment is such as warm
There is the possibility lost in degree, humidity, the influence of voltage, clock signal.For clock once losing, entire electronic system cannot be normal
Work is at this time handled with regard to needing a reset signal to be supplied to other circuits, to ensure that data are not lost, or is carried out
Clock recovery.Therefore a clock loss detection circuit is needed.
The prior art is that losing for A clock is then detected by B clock there are two clocks in a circuit system
It loses, the disadvantages of this solution is to need to use two clocks in a system, and once two clocks are lost simultaneously, just do not rise
Effect.
Summary of the invention
To solve the above problem existing for present technology, the utility model provides a kind of simple, effective, stable clock
Signal loss detection circuit.
The technical solution adopted in the utility model is:
A kind of clock signal missing detecting circuit, it is characterised in that: including first switch, second switch, third switch,
Four switches, first capacitor, the second capacitor, third capacitor, phase inverter,
The first end of the first switch is connect with power vd D, second end respectively with the first end of first capacitor, second
The first end of switch connects, the second end ground connection of the first capacitor；
The first end of third switch is connect with power vd D, second end respectively with the first end of third capacitor, the 4th
The first end of switch connects, the second end ground connection of the third capacitor；
The second end of the second switch is connect after connecting with the second end of the 4th switch with the first end of the second capacitor, institute
State the second end ground connection of the second capacitor；
The first end of second capacitor and the input terminal of phase inverter connect, the output end output detection letter of the phase inverter
Number；
Current limit circuit in parallel, the first end of the current-limiting circuit are connected to the first of the second capacitor on second capacitor
On connecting line between end and the input terminal of phase inverter, the second end of the current-limiting circuit is grounded；
The second switch, third switch connection control clock signal, when the first switch, the 4th switch connect control
Clock inverted signal.The utility model carries out the loss of clock signal by switched-capacitor circuit, when clock is normal, passes through switch
Off and on, promote the voltage of capacitor, after loss of clock, voltage decline on capacitor, detection circuit is simple, effectively, stablize；It is single
Clock system does not need that clock is in addition arranged, at low cost.
Further, the first switch, second switch, third switch, the 4th switch are the conductings in high level, low electricity
Usually disconnect.
Further, the current-limiting circuit is a resistance, passes through the electric current of resistance the second capacitor first end of limitation to ground.
Alternatively, the current-limiting circuit is a stable current circuit, the second capacitor first is limited by stabling current circuit
Hold the electric current to ground.
Further, the phase inverter is realized by comparator.
The beneficial effects of the utility model are: a clock is only needed, and it is at low cost, clock is completed by the decompression of capacitor
Signal loss detection is simple, effective, stable.
Detailed description of the invention
Fig. 1 is the electrical block diagram of the utility model.
Fig. 2 is a kind of electrical block diagram of stabling current circuit of the utility model.
Fig. 3 is the structural schematic diagram for the phase inverter being made of comparator that the utility model uses.
Specific embodiment
Combined with specific embodiments below the utility model to be further described, but the utility model is not limited to
In these specific embodiments.One skilled in the art would recognize that the utility model covers in Claims scope
All alternatives, improvement project and the equivalent scheme that may include.
Embodiment one
Referring to Fig.1, a kind of clock signal missing detecting circuit, including first switch 1, second switch are present embodiments provided
2, third switch 3, the 4th switch 4, first capacitor 5, the second capacitor 6, third capacitor 7, phase inverter 9.
The first end of first switch 1 described in the present embodiment is connect with power vd D, second end respectively with first capacitor 5
First end, the connection of the first end of second switch 2, the second end ground connection of the first capacitor 5；
The first end of the third switch 3 is connect with power vd D, second end respectively with the first end of third capacitor 7,
The first end of four switches 4 connects, the second end ground connection of the third capacitor 7；
The second end of the second switch 2 connects after connecting with the second end of the 4th switch 4 with the first end of the second capacitor 6
It connects, the second end ground connection of second capacitor 6；
The first end of second capacitor 6 is connect with the input terminal of phase inverter 9, and the output end of the phase inverter 9 exports inspection
Survey signal INT；
Current limit circuit in parallel on second capacitor 6, the first end of the current-limiting circuit are connected to the of the second capacitor 6
On connecting line between one end and the input terminal of phase inverter 9, the second end of the current-limiting circuit is grounded；
The second switch 2, the connection control clock signal clk of third switch 3, the first switch 1, the 4th switch 4 connect
Meet control clock inverted signal CLKZ.The utility model carries out the loss of clock signal by switched-capacitor circuit, and clock is normal
When, by the off and on of switch, promote the voltage of capacitor, after loss of clock, the voltage decline on capacitor, detection circuit letter
It is single, effective, stable；Single clock system does not need that clock is in addition arranged, at low cost.
First switch 1, second switch 2 described in the present embodiment, third switch 3, the 4th switch 4 are led in high level
Logical, when low level, disconnects.First capacitor 5, the second capacitor 6, third capacitor 7 are for saving charge.Phase inverter 9 is used for the second capacitor
6 first end voltage V1 generates high level when reducing.
Current-limiting circuit described in the present embodiment is a resistance 8, passes through the electric current of limitation 6 first end of the second capacitor of resistance 8 to ground.
When clock signal is normal:
1. control clock signal clk is high level, second switch 2 and third switch 3 are connected, and first switch 1 and the 4th is opened
It closes 4 to disconnect, third capacitor 7 is charged to VDD at this time.First capacitor 5 and 6 both end voltage of the second capacitor are equal.
2. to control clock signal clk be low level, first switch 1 and the 4th switch 4 are connected, second switch 2 and the
Three switches 3 disconnect.First capacitor 5 is charged to VDD at this time, and the voltage on the second capacitor 6 is VC2-1=VDD x C3/ (C2+C3).
3. next control clock signal clk is high level, second switch 2 and third switch 3 are connected, first switch
1 and the 4th switch 4 disconnect, third capacitor 7 is charged to VDD at this time.Voltage on second capacitor 6 is VC2-2=(C2x VC2+C1x
VDD)/(C2+C1)
The voltage V1 on the second capacitor 6 is promoted to high potential by repeatedly recycling, when V1 current potential is higher than the anti-of phase inverter 9
When turning threshold value, the INT of output is low level.
When clock dropout, there are two be in for first switch 1, second switch 2, third switch 3,4 federation of the 4th switch
On and off, VDD to V1 is off-state at this time, then the current potential of V1 is gradually pulled down to low level by resistance 8, when
When V1 voltage is lower than the turn threshold of phase inverter 9, the INT that phase inverter 9 exports is high potential, and this completes clock signal loss
Detection.
Embodiment two
The present embodiment and embodiment one pass through stabilization the difference is that the current-limiting circuit is a stabling current circuit
Current circuit limits 6 first end of the second capacitor to the electric current on ground.The stabling current circuit is shown in Fig. 2, using current-mirror structure.Its
Remaining structure and function is the same as example 1.
Embodiment three
The present embodiment the difference is that the phase inverter 9 is realized by comparator, is shown in Fig. 3, works as V1 with embodiment one
When level exceeds Vref, VOUT exports high level, when V1 level is lower than Vref, exports low level.Remaining structure and function is equal
It is the same as example 1.
It should be noted that above-described embodiment can be freely combined as needed.The above is only to the utility model
Preferred embodiment and principle be described in detail, for those of ordinary skill in the art, mention according to the utility model
The thought of confession, will change in specific embodiment, and these changes also should be regarded as the protection scope of the utility model.
Claims (5)
1. a kind of clock signal missing detecting circuit, it is characterised in that: including first switch, second switch, third switch, the 4th
Switch, first capacitor, the second capacitor, third capacitor, phase inverter,
The first end of the first switch is connect with power vd D, second end respectively with the first end of first capacitor, second switch
First end connection, the first capacitor second end ground connection；
The first end of the third switch is connect with power vd D, and second end is switched with the first end of third capacitor, the 4th respectively
First end connection, the third capacitor second end ground connection；
The second end of the second switch is connect after connecting with the second end of the 4th switch with the first end of the second capacitor, and described the
The second end of two capacitors is grounded；
The first end of second capacitor and the input terminal of phase inverter connect, the output end output detection signal of the phase inverter；
Current limit circuit in parallel on second capacitor, the first end of the current-limiting circuit be connected to the first end of the second capacitor with
On connecting line between the input terminal of phase inverter, the second end of the current-limiting circuit is grounded；
The second switch, third switch connection control clock signal, the first switch, the 4th switch connection control clock are anti-
Signal.
2. a kind of clock signal missing detecting circuit according to claim 1, it is characterised in that: the first switch,
Two switches, third switch, the 4th switch are the conductings in high level, and when low level disconnects.
3. a kind of clock signal missing detecting circuit according to claim 1 or 2, it is characterised in that: the current-limiting circuit
It is a resistance.
4. a kind of clock signal missing detecting circuit according to claim 1 or 2, it is characterised in that: the current-limiting circuit
It is a stable current circuit.
5. a kind of clock signal missing detecting circuit according to claim 1 or 2, it is characterised in that: the phase inverter is
It is realized by comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821911391.2U CN209151132U (en) | 2018-11-20 | 2018-11-20 | A kind of clock signal missing detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821911391.2U CN209151132U (en) | 2018-11-20 | 2018-11-20 | A kind of clock signal missing detecting circuit |
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| Publication Number | Publication Date |
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| CN209151132U true CN209151132U (en) | 2019-07-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201821911391.2U Active CN209151132U (en) | 2018-11-20 | 2018-11-20 | A kind of clock signal missing detecting circuit |
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| Country | Link |
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| CN (1) | CN209151132U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111913100A (en) * | 2020-08-10 | 2020-11-10 | 上海川土微电子有限公司 | Clock signal loss detection circuit |
-
2018
- 2018-11-20 CN CN201821911391.2U patent/CN209151132U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111913100A (en) * | 2020-08-10 | 2020-11-10 | 上海川土微电子有限公司 | Clock signal loss detection circuit |
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