CN103123897B - 萧基晶体管装置的制作方法 - Google Patents
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Abstract
本发明公开了萧基晶体管装置的制作方法,其特征在于包括提供一基底,具有一第一导电型;在基底上成长一外延层,其中外延层具有第一导电型;在外延层上形成一图案化介电层;在外延层的表面形成一金属硅化物层;在金属硅化物层上形成一掺质来源层,其中掺质来源层具有第二导电型的掺质;进行一热驱入工艺,使掺质来源层内第二导电型的掺质扩散进入外延层;及在金属硅化物层上形成一导电层。
Description
技术领域
本发明涉及萧基晶体管装置的技术领域,特别涉及一种可以避免漏电流现象的萧基晶体管装置的制作方法。
背景技术
萧基晶体管装置是一种适用在高频整流的晶体管。对应PN接面晶体管,萧基晶体管的接面不是PN接面,其接面是半导体(通常是N型)与金属,例如金、银或铂等等所构成的金属/半导体接面。因为金属/半导体接面主要以多数载子(majoritycarrier)传递电流讯号,因此在高频操作时,不会产生类似如PN接面电流讯号难以快速截止的现象。
在公知萧基晶体管装置的结构,至少具有一N型基底、一N型外延层、一环状场氧化层、一金属硅化物层、一源极导电层、和一漏极导电层。其中N型外延层借由外延工艺成长在N型基底上。环状场氧化层,例如二氧化硅,形成在N型外延层的表面上,用来定义出一有源区域。金属硅化物层形成在环状场氧化层定义出的有源区域内,而且导电层分别设置在金属硅化物层上和N型基底的底部。其中,漏极导电层与N型外延层构成一萧基接触(Schottkycontact)。除此之外,被环状场氧化层覆盖的N型外延层中还可以有P型保护环(guardring)结构,用来电性绝缘两相邻的装置和降低在晶体管末端结构因电场聚集效应(electricfieldcrowding)所造成的高漏电现象。
但是,上述的先前技术仍然有许多问题需要被解决。举例来说,因为外延工艺和自对准金属硅化物(Self-AlignedSilicide,salicide)工艺技术上的限制,有源区域内的N型外延层表面通常具有外延缺陷结构缺陷和形成金属硅化物时所产生的缺陷,这些缺陷是接下来工艺中形成金属硅化物与外延层接触时的缺陷来源。因为金属硅化物和外延缺陷结构间的耐压能力比一般金属/半导体接面的耐压能力差,所以当萧基晶体管装置处理电流讯号的时候,金属硅化物与外延缺陷结构所存在的区域容易产生反向漏电流的现象,使得萧基晶体管装置的耐压能力降低和漏电流上升。
所以,仍然需要改进的萧基晶体管装置的制作方法,用来解决上述漏电流的现象,使得萧基晶体管装置的电性表现和稳定性可以提升。
发明内容
本发明的目的在提供一种萧基晶体管装置的制作方法,用来解决外延缺陷结构所造成的反向漏电流的现象。
为了达到上述目的,根据本发明的一实施例,提供一种萧基晶体管装置的制作方法,包括:提供一基底,具有一第一导电型;在基底上成长一外延层,其中外延层具有第一导电型;在外延层上形成一图案化介电层;在外延层的一表面形成一金属硅化物层;在金属硅化物层上形成一掺质来源层,其特点在在掺质来源层具有第二导电型的掺质;进行一热驱入工艺,使掺质来源层内第二导电型的掺质扩散进入所述的外延层;和在金属硅化物层上形成一导电层。
根据本发明的另一实施例,提供一种萧基晶体管装置的制作方法,包括:提供一基底,具有一第一导电型;在基底上成长一外延层,其特点在在外延层具有第一导电型,且外延层具有至少一外延缺陷结构;在外延层上形成一金属硅化物层;在外延缺陷结构内形成一第二导电型的掺杂区,且掺杂区与外延层间具有一PN接面;和在金属硅化物层上形成一导电层。
本发明在萧基晶体管装置的外延层和外延缺陷结构间形成一PN接面,借由PN接面的反向耐压能力,避免外延缺陷结构产生漏电流现象,所以可以提升萧基晶体管装置的电性表现和稳定性。
为了让本发明的目的、特征和优点能更明显易懂,下文描述优选实施方式,并配合附图,详细说明如下。但优选实施方式和附图只供参考与说明,并不是用来对本发明加以限制。
附图说明
图1到图8所绘示的是根据本发明优选实施例的萧基晶体管装置的制作方法示意图。
其中,附图标记说明如下:
1萧基晶体管装置20基底
20a背面21外延层
23外延缺陷结构24保护环结构
28导电层30有源区域
31周边区域52场氧化层
53牺牲氧化层53a图案化牺牲氧化层
54氧化层60金属层
63金属硅化物层67缓冲层
69掺质来源层71载子浓度调整区
73掺杂区75PN接面
77导电层
具体实施方式
以下配合附图详细说明本发明萧基晶体管装置的制作方法。虽然本发明的优选实施例叙述例如下,但是并非用来限定本发明。任何擅长此技术的人员,在不脱离本发明的精神和范围内,可以对本发明作更动和润饰。因此本发明的保护范围会以权利要求的界定范围当作标准。并且为了让本发明的精神容易被理解,部分公知结构与工艺步骤的细节不会在此描述。
参考图1到图8,图1到图8绘示的是根据本发明优选实施例的萧基晶体管装置的制作方法示意图。首先,如图1,提供一第一导电型的重掺杂基底20,例如N+硅基底,而且基底20上定义有有源区域30和周边区域31,其中有源区域30是萧基接面(Schottkyjunction)存在的区域。除此之外,基底20的背面20a另外可以形成有一厚氧化层54,例如硅氧层,其厚度大约是4000埃(angstrom)至6000埃左右。接着,进行一般外延工艺,在基底20的正面成长出第一导电型的外延层21,例如N-硅基底,且外延层21的掺质浓度较佳小在基底20的掺质浓度。接下来利用热氧化的方式,在外延层21上方形成一场氧化层52,例如硅氧层。上述形成场氧化层52的工艺不限热氧化的方式,另外可以包含高密度等离子化学气相沈积(HighDensityPlasmaCVD,HDPCVD)、次常压化学气相沈积(SubAtmosphereCVD,SACVD)或旋涂式介电材料(SpinOnDielectric,SOD)等工艺。继续参考图1,由于外延工艺技术的限制,邻近外延层21表面的区域通常存在有外延缺陷结构(defects)23,例如:接缝缺陷(seamdefects)、空穴缺陷(voiddefects)和晶格错位(latticedislocation)。所述的缺陷会影响萧基晶体管装置的耐压能力,使得反向漏电流容易在外延缺陷结构23存在处产生。
如图2,在下面的步骤中,将接着定义出保护环结构24,用来避免萧基晶体管装置和邻近的装置产生电性上的干扰,其工艺步骤叙述如下:首先,利用光刻及蚀刻工艺(photolithographicandetchingprocess),暴露出部分外延层21的表面,这个时候,部分周边区域31的外延层21仍然被场氧化层52覆盖住。之后,利用热氧化工艺,在暴露出在场氧化层52的外延层21表面形成一牺牲氧化层53,目的在避免后续工艺的高能离子直接撞击外延层21的表面。接着,利用光刻工艺,在外延层21上方形成一图案化光阻(图未示),用来定义出保护环结构24存在的区域。之后进行离子注入工艺,在邻近外延层21表面的区域形成具有第二导电型的保护环结构24,例如P+型,且其浓度最佳大于邻近外延层21的掺质浓度。最后,去除图案化光阻并且施行一热退火工艺,用来激活保护环结构24的掺质。通过上述的工艺,就可以在外延层21中定义出保护环结构24。接着,如图3,利用另外的光刻及蚀刻工艺,去除位在有源区域30内的牺牲氧化层53,用来形成一图案化牺牲氧化层53a。此时,部分的保护环结构24会被覆盖在图案化牺牲氧化层53a下。
在下列的步骤中,将在有源区域30内的外延层21表面形成一金属硅化物层,用来形成萧基接面金属。参考图4和图5,如图4,形成一层金属层60,其可以当作是金属硅化物层63的金属来源层。其中,金属层60包含钛、镍、铂、钴、铬等金属或其合金,在本实施例中选用钛。接着,如图5,在惰性气体(例如氮气)的环境下,进行一快速热处理工艺,使得金属层60内的金属原子扩散进入外延层21内,并且产生一金属硅化物层63。金属硅化物层63的组成会对应金属层60的成分而改变。举例来说,当金属层60的组成是镍时,金属硅化物层63就是硅化镍(nickelsilicide,Ni2Si)。根据本优选实施例,金属层60是钛,而金属硅化物层63是硅化钛(titaniumsilicide,TiSi2)。另外,从附图可以知道,部分的外延缺陷结构23会位在金属硅化物层63内。最后,去除未反应的金属层60,用来暴露出外延层21上表面。
根据上述,当形成金属硅化物层63后,仍然会有部分的外延缺陷结构23在外延层21中。为了去除外延缺陷结构23对萧基晶体管装置电性的影响,本发明利用热扩散的方式,用来消除外延缺陷结构23所产生的电性不良影响。主要的技术特点叙述如下:如图6,首先,在外延层21上方形成一掺质来源层69,其具有多个第二导电型的掺质,例如硼。且掺质来源层69的成分包含外延硅、多晶硅、非晶硅或硼掺杂硅玻璃(borosilicateglass,BSG),但不受此限制。接着,如图7,进行一热驱入工艺(drive-in),使掺质来源层69内的掺质扩散进入外延层21中。另外,为了增加掺质扩散的均匀程度,另外可以在掺质来源层69和外延层21的接面形成一缓冲层(buffer)67,用来增进接面的接触性质。
上述的热驱入工艺可以包含快速热处理工艺(rapidthermalprocess,RTP)、瞬间热退火(spikethermalannealing)、激光热退火(LaserThermalAnnealing,LTA)或激光瞬间退火(LaserSpikeAnnealing,LSA),但不限在此。除此之外,根据本发明的另一优选实施例,另外可以使用气相扩散(vaporphasediffusion)工艺或离子注入(ionimplantation)工艺取代上述的热驱入工艺,也就是说,掺质来源层69不会形成在外延层21上,而且掺质由气相的形式扩散进入外延层21中或借由离子化的形式撞击进入外延层21中。
如图7,经过上述的热驱入工艺、气相扩散工艺或离子注入工艺后,会形成一紧邻在金属硅化物层63底部的载子浓度调整区71。在本发明的所有优选实施例中,载子浓度调整区71的导电型仍然是第一导电型,例如N型,而且其主要载子浓度实质低于邻近的第一导电型外延层21,例如介在1E12原子数/立方公分至1E19原子数/立方公分间。因此,载子浓度调整区71与外延层21间不会形成PN接面,而且会使得能量障碍提高一些并且降低漏电流现象的产生。在这边需注意的是,当形成载子浓度调整区71的同时,因为外延缺陷结构23的晶格排列比较松散,所述第二导电型的掺质会更容易扩散进入外延缺陷结构23中,而形成一具有第二导电型的掺杂区73,其浓度介在1E14原子数/立方公分至1E19原子数/立方公分间。其特点是掺杂区73的体积可刚好包含或大于外延缺陷结构23的体积。所以,掺杂区73与外延层21或载子浓度调整区71间会具有一PN接面75。当萧基晶体管装置受到一反向电压时,包覆住外延缺陷结构23的PN接面75会相对应地扩大其空乏区(depletionregion)。因为空乏区具有可以承受反向偏压的能力,所以反向漏电流便不会产生在外延缺陷结构23中。在此需注意的是,根据本发明的另一优选实施例,上述的第一导电型和第二导电型可以相互对调,也就是说第一导电型是P型,而第二导电型是N型。此时,掺杂区73与外延层21或载子浓度调整区71间仍然会具有一PN接面75。
最后,如图8,进行一抛光工艺,将位在基底20的背面20a的氧化层54去除,暴露出基底20的背面20a。并在金属硅化物层63上和基底20的背面20a分别形成导电层77及导电层28。其特点是导电层77与外延层21构成金属接触,而导电层28与基底20构成奥姆接触(ohmiccontact)。除此之外,上述导电层77及导电层28的材质可以是Ti、Ni、Ag、Al或其组合。到现在,就完成本发明的萧基晶体管装置1结构。
综合上文的叙述,本发明使用一热驱入、气相扩散或离子注入工艺,用来形成一PN接面75在有源区域30内的外延缺陷结构23与外延层21间。借由PN接面75的特性而提升因外延缺陷结构23造成的低萧基位障(Schottkybarrierheight),以增加外延缺陷结构23的耐压能力,进一步避免反向漏电流的现象产生。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (20)
1.一种萧基晶体管装置的制作方法,其特征在于包括:
提供一基底,具有一第一导电型;
在所述基底上成长一外延层,其中所述外延层具有所述第一导电型;
在所述外延层上形成一图案化介电层;
在所述外延层中形成一保护环结构,其中所述保护环结构具有一第二导电型;
在所述外延层的表面形成一金属硅化物层,其中所述金属硅化物层覆盖住所述保护环结构;
在所述金属硅化物层上形成一掺质来源层,其中所述掺质来源层具有所述第二导电型的掺质;
进行一热驱入工艺,使所述掺质来源层内所述第二导电型的掺质透过所述金属硅化物层扩散进入所述外延层,形成一具有所述第一导电型的载子浓度调整区以及一具有所述第二导电型的掺杂区;及
在所述金属硅化物层上形成一导电层。
2.根据权利要求1项所述的萧基晶体管装置的制作方法,其特征在于所述外延层的所述表面包括至少一外延缺陷结构。
3.根据权利要求2所述的萧基晶体管装置的制作方法,其特征在于所述的外延缺陷结构包含接缝缺陷、空穴缺陷或晶格错位。
4.根据权利要求1所述的萧基晶体管装置的制作方法,其特征在于所述掺杂区的所述第二导电型掺质的浓度介于1E14原子数/立方公分到1E19原子数/立方公分间。
5.根据权利要求1所述的萧基晶体管装置的制作方法,其特征在于在形成所述掺质来源层前,还包含:在所述金属硅化物层上形成一缓冲层。
6.根据权利要求5所述的萧基晶体管装置的制作方法,其特征在于在进行所述热驱入工艺后,还包含:去除所述掺质来源层和所述缓冲层。
7.根据权利要求6所述的萧基晶体管装置的制作方法,其特征在于所述的缓冲层包含氧化硅。
8.根据权利要求1所述的萧基晶体管装置的制作方法,其特征在于所述的第一导电型是N型,所述第二导电型是P型。
9.根据权利要求1所述的萧基晶体管装置的制作方法,其特征在于所述的金属硅化物层包括硅化钛、硅化镍、硅化铂、硅化钼或硅化钴。
10.根据权利要求1所述的萧基晶体管装置的制作方法,其特征在于所述的掺质来源层包括外延硅、多晶硅、非晶硅或硼掺杂硅玻璃。
11.根据权利要求1所述的萧基晶体管装置的制作方法,其特征在于所述第二导电型的掺质包括硼原子。
12.根据权利要求1所述的萧基晶体管装置的制作方法,其特征在于所述的热驱入工艺包含快速热处理工艺。
13.根据权利要求1所述的萧基晶体管装置的制作方法,其特征在于所述的导电层包含钛、镍、金、铝或其组合。
14.一种萧基晶体管装置的制作方法,其特征在于包括:
提供一基底,具有一第一导电型;
在所述基底上成长一外延层,其中所述外延层具有所述第一导电型,所述外延层具有至少一外延缺陷结构;
在所述外延层上形成一金属硅化物层;
进行掺杂工艺,在所述外延层的一表面形成一具有所述第一导电型的载子浓度调整区,并同时在所述外延缺陷结构形成一具有第二导电型的掺杂区,且所述掺杂区与所述外延层间或所述掺杂区与所述载子浓度调整区间具有一PN接面;及
在所述金属硅化物层上形成导电层。
15.根据权利要求14所述的萧基晶体管装置的制作方法,其特征在于所述掺杂工艺包含:
在所述金属硅化物层上形成一掺质来源层,其中所述掺质来源层具有所述第二导电型的掺质;及
进行一热驱入工艺,使所述的第二导电型的掺质扩散进入所述外延层。
16.根据权利要求14所述的萧基晶体管装置的制作方法,其特征在于所述的掺杂工艺是气相扩散工艺或离子注入工艺。
17.根据权利要求15所述的萧基晶体管装置的制作方法,其特征在于在形成所述掺质来源层前,还包含:在所述的金属硅化物层上形成一缓冲层。
18.根据权利要求17所述的萧基晶体管装置的制作方法,其特征在于在进行所述热驱入工艺后,还包含:去除所述掺质来源层和所述缓冲层。
19.根据权利要求14所述的萧基晶体管装置的制作方法,其特征在于所述掺杂区具有第二导电型的掺质,其掺杂浓度介于1E14原子数/立方公分至1E19原子数/立方公分间。
20.根据权利要求14所述的萧基晶体管装置的制作方法,其特征在于所述第一导电型是N型,所述第二导电型是P型。
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US9123634B2 (en) * | 2013-01-15 | 2015-09-01 | Epistar Corporation | Method for making semiconductor device and semiconductor device made thereby |
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US11328928B2 (en) * | 2018-06-18 | 2022-05-10 | Applied Materials, Inc. | Conformal high concentration boron doping of semiconductors |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5643821A (en) * | 1994-11-09 | 1997-07-01 | Harris Corporation | Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications |
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US5643821A (en) * | 1994-11-09 | 1997-07-01 | Harris Corporation | Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications |
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