CN103067015B - Circulation analog-digital converter and conversion method for complementary metal oxide semiconductor (CMOS) image sensor - Google Patents
Circulation analog-digital converter and conversion method for complementary metal oxide semiconductor (CMOS) image sensor Download PDFInfo
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Abstract
The invention relates to the field of integrated circuit design of microelectronics and aims to reduce chip power dissipation and area pay expenses of a complementary metal oxide semiconductor (CMOS) image sensor. The circulation analog-digital converter for CMOS image sensor is composed of linked switches 1-6, a capacitor C1, a capacitor C2, a digital to analog converter (DAC), 1.5b analog to digital converter (ADC) and an operational amplifier, and further comprises two groups of programmable sampling capacitors Cs1 and Cs2 and linked switches 8-11. Positive terminals of a first group of the programmable sampling capacitors Cs1 and Cs2 are respectively connected with virtual reality software and technology (Vrst) through linked switches 4 and 5, negative terminals of the first group of the programmable sampling capacitors Cs1 and Cs2 are respectively connected with a virtual computer (Vcom) through the linked switches 4 and 5, and the negative terminals of the first group of the programmable sampling capacitors Cs1 and Cs2 are connected with an inverted input end of the operational amplifier. Positive terminals of a second group of the programmable sampling capacitors Cs1 and Cs2 are connected with voltage signals (Vsig). The circulation analog-digital converter for CMOS image sensor is mainly used in design of the CMOS image sensor.
Description
Technical field
The present invention relates to microelectronic integrated circuit (IC) design field, particularly relate to a kind of circulation AD converter for cmos image sensor and conversion method.
Background technology
In the decades in past, imageing sensor market dominated by charge coupled device (Charge Coupled Device, CCD) imageing sensor always.But the shortcomings such as ccd image sensor exists drive circuit and signal processing circuit is difficult to and pel array single-chip integration, needs high voltage operation, and rate of finished products low cost is high.Cmos image sensor is not nearest product of the time in fact, the research of it and ccd image sensor is almost start to walk simultaneously, but due to by technological level at that time restriction cmos image sensor poor image quality, resolution is low, noise is high and luminous sensitivity inadequate, thus do not paid attention to and developed.Along with the development of standard CMOS large scale integrated circuit technology, the technical barrier in past cmos image sensor manufacturing process all have found the approach of corresponding solution, thus greatly facilitates cmos image sensor development.Cmos image sensor itself has the incomparable advantage of CCD device, such as: as rope array and treatment circuit single-chip integration, and the low and low cost of low-voltage, system complexity.Therefore cmos image sensor is progressively becoming the substitute of traditional ccd image sensor, the future thrust of cmos image sensor is great dynamic range, high-resolution, high sensitivity, microminiaturization and multifunction, this has higher requirement with regard to giving the design of cmos image sensor system, improving constantly particularly along with technological level, constantly reducing of size, Analog Circuit Design institute facing challenges is just increasing.Analog to digital converter (Analog to DigitalConvertor, ADC) be the interface of simulated world and digital world, be part and parcel in Analog Circuit Design, therefore find the analog to digital converter being suitable for cmos image sensor system to seem particularly important.In the prior art, cmos image sensor can adopt row Parallel ADC to carry out data transaction, and Cyclic ADC is a kind of common row Parallel ADC, and it can realize higher data throughput and higher conversion accuracy.But Cyclic ADC cannot carry out pre-amplification adjustment to front end analogue signal in prior art, generally in cmos image sensors can increase Digitally programmable amplifier (Digital Programmable Gain Amplifier before Cyclic ADC, DPGA) pre-amplification adjustment is carried out to the input analog signal of Cyclic ADC, but this will certainly increase the expense of chip power-consumption and area.
Summary of the invention
The present invention is intended to overcome the deficiencies in the prior art, reduce the expense of chip power-consumption and area, for achieving the above object, the technical scheme that the present invention takes is, for the circulation AD converter of cmos image sensor, be made up of linked switch 1-7, C1 capacitance group, C2 capacitance group, C3 capacitance group, DAC, 1.5bADC, amplifier, also comprise two groups of programmable sample electric capacity Cs1 and Cs2, linked switch 8-11, the 2nd switch in first electric capacity of the 1st switch of DAC in linked switch 2, C1 capacitance group, linked switch 2 is connected to amplifier inverting input, and 1st switch, the 1.5bADC of the first electric capacity in linked switch 1 of C1 capacitance group feed back to DAC, the 2nd switch in first electric capacity of the 1st switch of DAC in linked switch 3, C2 capacitance group, linked switch 3 is connected to amplifier inverting input, and 3rd switch, the 1.5bADC of the first electric capacity in linked switch 2 of C2 capacitance group feed back to DAC, the 5th switch in second electric capacity of the 4th switch of DAC in linked switch 2, C1 capacitance group, linked switch 2 is connected to amplifier in-phase input end, and 2nd switch, the 1.5bADC of the second electric capacity in linked switch 1 of C1 capacitance group feed back to DAC, the 4th switch in second electric capacity of the 3rd switch of DAC in linked switch 3, C2 capacitance group, linked switch 3 is connected to amplifier in-phase input end, and 6th switch, the 1.5bADC of the second electric capacity in linked switch 2 of C2 capacitance group feed back to DAC, the 3rd switch in linked switch 1 is connected with between two electric capacity outputs of C1 capacitance group, the 7th switch in linked switch 2 is connected with between two electric capacity outputs of C2 capacitance group, the anode of first group of programmable capacitor Cs1 and Cs2 is connected to Vrst respectively by the 1st switch in the switch of the 1st in linked switch 4, linked switch 5, the negative terminal of first group of programmable capacitor Cs1 and Cs2 is connected to Vcom respectively by the 2nd switch in the switch of the 2nd in linked switch 4, linked switch 5, and the negative terminal of first group of programmable capacitor Cs1 and Cs2 is connected to amplifier inverting input respectively by the 1st switch in the switch of the 1st in linked switch 8, linked switch 9, the anode of second group of programmable capacitor Cs1 and Cs2 is connected to Vsig respectively by the 1st switch in the switch of the 1st in linked switch 6, linked switch 7, the negative terminal of second group of programmable capacitor Cs1 and Cs2 is connected to Vcom respectively by the 2nd switch in the switch of the 2nd in linked switch 6, linked switch 7, and the negative terminal of second group of programmable capacitor Cs1 and Cs2 is connected to amplifier in-phase input end respectively by the 2nd switch in the switch of the 2nd in linked switch 8, linked switch 9, first electric capacity of C3 capacitance group is connected to amplifier inverting input by the switch of the 1st in linked switch 11, C3 capacitance group first electric capacity be connected to Vcom by the switch of the 1st in linked switch 10, first electric capacity of C3 capacitance group is connected to vrefn by the switch of the 2nd in linked switch 10, and first electric capacity of C3 capacitance group is connected to amplifier in-phase output end by the switch of the 2nd in linked switch 11, second electric capacity of C3 capacitance group is connected to amplifier in-phase input end by the switch of the 3rd in linked switch 11, second electric capacity of C3 capacitance group is connected to Vcom by the switch of the 3rd in linked switch 10, second electric capacity of C3 capacitance group is connected to vrefp by the switch of the 4th in linked switch 10, second electric capacity of C3 capacitance group is connected to amplifier reversed-phase output by the switch of the 4th in linked switch 11, wherein, Vcom is the common-mode voltage of circulation AD converter, Vrst is the reset signal that front end pixel exports, Vsig is the exposure signal that front end pixel exports, vrefp and vrefn is respectively the positive negative reference voltage of circulation AD converter.
The circulation D conversion method of cmos image sensor, realizes by means of aforementioned circulation AD converter, and comprises the steps:, by controlling linked switch 1-11, to realize two groups of each three kinds of states of programmable sample electric capacity Cs1 and Cs2, be followed successively by:
Cs1 electric capacity is sampled:
Cs2 in state 1: two group of programmable sample electric capacity connects amplifier homophase, inverting input respectively, electric capacity C3, another electric capacity C3 are respectively homophase, inverting feedback electric capacity, amplifier is exported by electric capacity C1, and the Cs1 in two groups of programmable sample electric capacity is connected between Vcom, Vrst;
State 2: the Cs2 in state 1 is changed to C1, the C1 in state 1 is changed to C2, and vrefp, vrefn are connected respectively to amplifier homophase, inverting input;
State 3: electric capacity C1, C2 reversing of position in state 2;
Cs2 electric capacity is sampled:
Cs1, Cs2 reversing of position in state 1:Cs1 electric capacity sample states 1;
State 2, state 3 and Cs1 electric capacity sample states 2,3 identical.
Technical characterstic of the present invention and effect:
Sampling capacitance is changed into two groups of programmable sample electric capacity by the basis of the Cyclic ADC provided in prior art and increases by 6 groups of switches simultaneously, Control timing sequence is adjusted, thus realize the combination of DPGA and Cyclic ADC, signal amplification process and the Cyclic ADC analog-to-digital conversion of CDS, DPGA can be realized according to pipeline system, improve data throughput, reduce chip area simultaneously.
Accompanying drawing explanation
The Cyclic adc circuit structure that Fig. 1 prior art provides.
The Cyclic adc circuit structure chart that Fig. 2 the present invention describes.
The Cyclic ADC Control timing sequence figure that Fig. 3 the present invention describes.
The Cyclic ADC different conditions equivalent circuit diagram that Fig. 4 the present invention describes.
The Cyclic ADC workflow diagram that Fig. 5 the present invention describes.
A kind of implementation method of programmable sample electric capacity in the Cyclic ADC that Fig. 6 the present invention describes.
Embodiment
The gain-adjusted function of the present invention integrated DPGA in Cyclic ADC, correlated-double-sampling (the Correlated Double Sample that continuous-flow type completes pixel output signal is got final product by Cyclic ADC, CDS), gain-adjusted and analog-to-digital conversion operation, reduce the expense of chip power-consumption and area.
The structural representation of the Cyclic ADC that prior art provides as shown in Figure 1, the switch that number in the figure is identical is linked switch, it is formed primarily of MDAC, register and RSD digital correction circuit, wherein MDAC circuit is the circuit module of most critical in Cyclic ADC, and it completes sampling to analog input signal and quantizing process.The MDAC circuit structure of the Cyclic ADC that the present invention proposes as shown in Figure 2, on the basis of its Cyclic ADC provided in prior art, sampling capacitance Cs is changed into two groups of programmable sample electric capacity Cs1 and Cs2, switch 5 is changed into the left and right pole plate that linked switch is connected on first sampling capacitance Cs2 respectively, switch 4 is changed into the left and right pole plate that linked switch is connected on first sampling capacitance Cs1 respectively, switch 6 is changed into the left and right pole plate that linked switch is connected on second sampling capacitance Cs1 respectively, increase the left and right pole plate that linked switch 7 is connected on second sampling capacitance Cs2 respectively, increase linked switch 8 simultaneously, switch 9, switch 10 and switch 11.
As shown in Figure 3, under the control of this sequential, this ADC signal sampling and signal quantization can water operations for the Control timing sequence of the Cyclic ADC that the present invention describes.Point state equivalent circuit diagram of the Cyclic ADC that the present invention describes as shown in Figure 4, sampling capacitance Cs1 and Cs2 alternate sampled signal, as the pixel reset signal Vrst that Cs1 sampling front-end pixel exports and exposure signal Vsig, this Cyclic ADC carries out pre-amplification process when state 1 to the picture element signal Vrst-Vsig gathered in Cs2, then through the continuous circulation of state 2 and state 3 until complete analog-to-digital conversion after reaching the conversion accuracy of needs, when Cs1 terminates to sample to pixel output signal, Cyclic ADC also completes and amplifies and analog-to-digital operation pixel output signal in Cs2, then Cs2 samples, and next organizes pixel output signal, and now Cyclic ADC amplifies the pixel output signal that Cs1 has just gathered and analog-to-digital conversion operation, and by that analogy, wherein the connection of two electric capacity C1 is realized by DAC.As shown in Figure 5, the Cyclic ADC that visible the present invention describes can realize operating pixel output signal collection and amplification, analog-to-digital conversion by pipeline system its flowing water workflow.Because this Cyclic ADC acquires pixel reset signal Vrst and pixel exposure signal Vsig simultaneously, be then carried out amplifying process to Vrst-Vsig in the signal pre-amplification stage, therefore it also completes CDS operation.By the size of programming Control sampling capacitance Cs1 and Cs2 just can control signal amplify processing stage gain, thus realize integrated DPGA function in Cyclic ADC.
Vcom is the common-mode voltage of ADC, and Vrst is the reset signal that front end pixel exports, and Vsig is the exposure signal that front end pixel exports, and Vrst-Vsig is the difference of these two signals, vrefp and vrefn is respectively the positive negative reference voltage of ADC
It is in the cmos image sensor of 500K that the Cyclic ADC that the present invention describes is applied in row read-out speed, and this CyclicADC continuous-flow type in 2us completes CDS, signal amplifies and data quantization operation.The data sampling rate of Cyclic ADC be 500K time per second.Wherein sampling capacitance can adopt the structure in accompanying drawing 6, uses S0-S3 and S0_b-S3_b control signal to control the size of sampling capacitance, thus realizes the parallel combination of different specific capacitance, and then realize the regulation and control to sampling capacitance size.Wherein the complexity of sampling capacitance is identical with sampling capacitance in DPGA, but owing to being integrated with DPGA function in Cyclic ADC, comparing and directly add in Cyclic ADC front end the amplifier that DPGA circuit saves a DPGA, therefore save chip area and power consumption.
Claims (2)
1. the circulation AD converter for cmos image sensor, it is characterized in that, be made up of linked switch 1-7, C1 capacitance group, C2 capacitance group, C3 capacitance group, DAC, 1.5bADC, amplifier, also comprise two groups of programmable sample electric capacity Cs1 and Cs2, linked switch 8-11, the 2nd switch in first electric capacity of the 1st switch of DAC in linked switch 2, C1 capacitance group, linked switch 2 is connected to amplifier inverting input, and 1st switch, the 1.5bADC of the first electric capacity in linked switch 1 of C1 capacitance group feed back to DAC, the 2nd switch in first electric capacity of the 1st switch of DAC in linked switch 3, C2 capacitance group, linked switch 3 is connected to amplifier inverting input, and 3rd switch, the 1.5bADC of the first electric capacity in linked switch 2 of C2 capacitance group feed back to DAC, the 5th switch in second electric capacity of the 4th switch of DAC in linked switch 2, C1 capacitance group, linked switch 2 is connected to amplifier in-phase input end, and 2nd switch, the 1.5bADC of the second electric capacity in linked switch 1 of C1 capacitance group feed back to DAC, the 4th switch in second electric capacity of the 3rd switch of DAC in linked switch 3, C2 capacitance group, linked switch 3 is connected to amplifier in-phase input end, and 6th switch, the 1.5bADC of the second electric capacity in linked switch 2 of C2 capacitance group feed back to DAC, the 3rd switch in linked switch 1 is connected with between two electric capacity outputs of C1 capacitance group, the 7th switch in linked switch 2 is connected with between two electric capacity outputs of C2 capacitance group, the anode of first group of programmable capacitor Cs1 and Cs2 is connected to Vrst respectively by the 1st switch in the switch of the 1st in linked switch 4, linked switch 5, the negative terminal of first group of programmable capacitor Cs1 and Cs2 is connected to Vcom respectively by the 2nd switch in the switch of the 2nd in linked switch 4, linked switch 5, and the negative terminal of first group of programmable capacitor Cs1 and Cs2 is connected to amplifier inverting input respectively by the 1st switch in the switch of the 1st in linked switch 8, linked switch 9, the anode of second group of programmable capacitor Cs1 and Cs2 is connected to Vsig respectively by the 1st switch in the switch of the 1st in linked switch 6, linked switch 7, the negative terminal of second group of programmable capacitor Cs1 and Cs2 is connected to Vcom respectively by the 2nd switch in the switch of the 2nd in linked switch 6, linked switch 7, and the negative terminal of second group of programmable capacitor Cs1 and Cs2 is connected to amplifier in-phase input end respectively by the 2nd switch in the switch of the 2nd in linked switch 8, linked switch 9, first electric capacity of C3 capacitance group is connected to amplifier inverting input by the switch of the 1st in linked switch 11, C3 capacitance group first electric capacity be connected to Vcom by the switch of the 1st in linked switch 10, first electric capacity of C3 capacitance group is connected to vrefn by the switch of the 2nd in linked switch 10, and first electric capacity of C3 capacitance group is connected to amplifier in-phase output end by the switch of the 2nd in linked switch 11, second electric capacity of C3 capacitance group is connected to amplifier in-phase input end by the switch of the 3rd in linked switch 11, second electric capacity of C3 capacitance group is connected to Vcom by the switch of the 3rd in linked switch 10, second electric capacity of C3 capacitance group is connected to vrefp by the switch of the 4th in linked switch 10, second electric capacity of C3 capacitance group is connected to amplifier reversed-phase output by the switch of the 4th in linked switch 11, wherein, Vcom is the common-mode voltage of circulation AD converter, Vrst is the reset signal that front end pixel exports, Vsig is the exposure signal that front end pixel exports, vrefp and vrefn is respectively the positive negative reference voltage of circulation AD converter.
2. the circulation D conversion method for cmos image sensor, it is characterized in that, realize by means of aforementioned circulation AD converter, and comprise the steps: by controlling linked switch 1-11, realize two groups of each three kinds of states of programmable sample electric capacity Cs1 and Cs2, be followed successively by:
Cs1 electric capacity is sampled:
Cs2 in state 1: two group of programmable sample electric capacity connects amplifier homophase, inverting input respectively, electric capacity C3, another electric capacity C3 are respectively homophase, inverting feedback electric capacity, amplifier is exported by electric capacity C1, and the Cs1 in two groups of programmable sample electric capacity is connected between Vcom, Vrst;
State 2: the Cs2 in state 1 is changed to C1, the C1 in state 1 is changed to C2, and vrefp, vrefn are connected respectively to amplifier homophase, inverting input;
State 3: electric capacity C1, C2 reversing of position in state 2;
Cs2 electric capacity is sampled:
Cs1, Cs2 reversing of position in state 1:Cs1 electric capacity sample states 1;
State 2, state 3 and Cs1 electric capacity sample states 2,3 identical.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103986469A (en) * | 2014-03-31 | 2014-08-13 | 天津大学 | Sigma-delta analog-to-digital converter adopting two-step process and hardware multiplexing |
| CN104038230B (en) * | 2014-06-26 | 2017-03-08 | 天津大学 | Focal plane block matrix conversion row parallel arithmetic D conversion method and transducer |
| CN104202049A (en) * | 2014-08-19 | 2014-12-10 | 合肥宁芯电子科技有限公司 | Circulation type analog-digital converter |
| CN106130561B (en) * | 2016-06-21 | 2020-01-17 | 芯海科技（深圳）股份有限公司 | ADC integrator with DAC function and measuring method |
| CN106130560B (en) * | 2016-06-21 | 2020-01-17 | 芯海科技（深圳）股份有限公司 | Integrator applied to sigma delta analog-to-digital conversion circuit with DAC function |
| CN112398475A (en) * | 2019-08-12 | 2021-02-23 | 天津大学青岛海洋技术研究院 | Cyclic ADC structure with CDS function |
| CN114245046B (en) * | 2021-10-27 | 2024-04-09 | 地太科特电子制造(北京)有限公司 | Circulating ADC for CMOS image sensor and circulating method thereof |
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| US7443333B2 (en) * | 2007-02-13 | 2008-10-28 | Freescale Semiconductor, Inc. | Single stage cyclic analog to digital converter with variable resolution |
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