CN104038230B - Focal plane block matrix conversion row parallel arithmetic D conversion method and transducer - Google Patents

Abstract

The present invention relates to microelectronic integrated circuit fields, for providing a kind of new row parallel arithmetic ADC, for realizing the accumulation operations in block matrix conversion.Accumulation operations in making block matrix change become an intrinsic part in ADC quantizing process, and do not make the excessive increase of hardware resource, hence in so that treatment effeciency is also ensured.For this reason, the present invention adopts the technical scheme that, focal plane block matrix changes row parallel arithmetic analog-digital converter, including：The first adder that is sequentially connected, second adder, multiplier, the 3rd adder；The output of first adder is also compared with reference voltage through first comparator, and comparative result exports second adder；The output of multiplier is also compared with reference voltage through the second comparator, and comparative result exports the 3rd adder；The output of the 3rd adder feeds back to first adder through chronotron.Present invention is mainly applied to IC design manufacture.

Description

Focal plane block matrix conversion row parallel arithmetic D conversion method and transducer

Technical field

The present invention relates to microelectronic integrated circuit fields, more particularly, to row parallel A/D converter.Specifically, it is related to For realizing the row parallel arithmetic analog-digital converter of focal plane block matrix conversion.

Technical background

In the last few years, cmos image sensor (CIS) rely on its can single-chip integration, bottom surface amass and the advantages of low-power consumption gradually Become the mainstream technology means in video acquisition field.In the field such as wireless sensing and biologic medical, for the data to magnanimity Preserved and transmitted the cost needing to pay costliness.The video processing technique such as compression of images can significantly alleviate transmission The pressure that bandwidth is subject to, but this typically requires accurate DSP (digital signal processor) to complete corresponding block matrix conversion Operation, its shared power consumption and area are all huge.

The image focal plane compress technique that sensor based system is realized can effectively reduce area and the power consumption of chip, its The low-power consumption of analog circuit, bottom surface can be utilized to amass simultaneously and digital circuit high accuracy.But this compressed format also faces Many challenges：On focal plane, limited silicon area governs the complexity of circuit, the relatively low signal to noise ratio (SNR) of ratio, and To carry out suitable compromise between limited circuit resource and the image compression algorithm of complexity.Block matrix conversion has as one kind Damage image compression algorithm, be widely used in many video acquisitions and process field by its larger compression ratio.

Inventor finds mostly the existing block matrix conversion method based on focal plane is using electric capacity in switched-capacitor circuit The ratio of value completes the multiplication operation of pixel value and corresponding core coefficient, recycles the means such as simulation accumulator to complete accumulation operations. All operations all complete in analog domain, and do so can make analog circuit unintentional nonlinearity and the shortcoming of low precision highlight Come, the result precision of image procossing is very limited.Additionally, the circuit module that with the addition of for block matrix conversion can substantially increase The process cycle of CIS.

Content of the invention

In order to overcome the deficiencies in the prior art, provide a kind of new row parallel arithmetic ADC, be used for realizing block matrix conversion In accumulation operations.Accumulation operations in making block matrix change become an intrinsic part in ADC quantizing process, and do not make hard The excessive increase of part resource, hence in so that treatment effeciency is also ensured.For this reason, the present invention adopts the technical scheme that, Jiao Ping Face block matrix conversion row parallel arithmetic analog-digital converter, including：The first adder that is sequentially connected, second adder, multiplier, 3rd adder；The output of first adder is also compared with reference voltage through first comparator, and comparative result exports second Adder；The output of multiplier is also compared with reference voltage through the second comparator, and comparative result exports the 3rd adder；The The output of three adders feeds back to first adder through chronotron.

Multiplier is paired multiplier.

Focal plane block matrix conversion row parallel arithmetic D conversion method：Using discrete input signal P [k], as following One of formula T_ij,h：

The formula that above formula is changed for block matrix, wherein I_hvIt is the pixel value of correspondence position, C_hvIt is corresponding core coefficient；Often One T_ijAll operated and obtained with accumulation operations by h × v multiplication, wherein h and v represents line number and the columns of image respectively；

Above-mentioned input signal is inputted aforementioned arithmetic analog-digital converter it is assumed that described ADC quantified precision is N-bit, then Period 1 terminates rear residual value：

w₂[1]=2 (P [1]-d₁[1])-d₂[1] (1)

In the remaining N-1 cycle, residual value is：

w₂[k]=2 (P [k]+w₂[k-1]-d₁[k])-d₂[k], k=2,3..., N (2)

Can obtain after the residual value in this N number of cycle is carried out adding up according to its binary weights：

Above formula is entered and can obtain after line translation：

Wherein, w₂[k] represents the kth time output of the 3rd adder, d₁[k]、d₂[k] represent respectively first comparator, second The kth time output of comparator；

To T_ij,hObtain the core coefficient after a conversion after carrying out adding up, can be seen that T to be calculated from formula (6)_ij,h Also the 2 bit number character codes extracting to be taken advantage of two with the operation being added, these operation need in the digital domain utilize adder Complete.

Complete specifically using adder in the digital domain, adder first will be according to weight by d₁[k]、d₂[k] is from simulation Domain is transformed into numeric field and is stored, then carries out add operation.

Compared with the prior art, the technical characterstic of the present invention and effect：

The present invention proposes a kind of arithmetic type ADC for the conversion of focal plane block matrix.By entering to conventional recycle type ADC Row improves, and with the addition of an analog comparater module and accumulation operations required for block matrix conversion have been dissolved in ADC so as to become For an intrinsic part in ADC quantizing process, substantially increase treatment effeciency.Avoid traditional image focal plane compression method Cause non-linear and low precision due to all completing all operations in analog domain, and due to not needing substantial amounts of switch Condenser network, can make the area of circuit and power consumption significantly reduce.

Brief description

Fig. 1 is structure chart and the fundamental diagram of traditional cyclic analog-to-digital converters；

Fig. 2 is the structure chart and fundamental diagram after the present invention makes improvements；

Fig. 3 is intended to d1 and d2 carries out the adder structure figure of add operation.

In figure 2 refers to the magnitude of voltage of input is carried out taking advantage of 2 operations；

Square frame and its internal waveform refer to by input voltage and reference voltage be compared with produce comparative result d1 or Person d2；

Z^-1Represent is delay operation, for output valve time delay returns to input port for a period of time afterwards；

Specific embodiment

The present invention adopts the technical scheme that：

The formula that above formula is changed for block matrix, wherein I_hvIt is the pixel value of correspondence position, C_hvIt is corresponding core coefficient.Can To find out, each T_ijAll operated and obtained with accumulation operations by h × v multiplication, wherein h and v represents the row of image respectively Number and columns.Traditional focal plane block matrix conversion method typically completes pixel value and corresponding first with switched-capacitor circuit The multiplication operation of core coefficient, next completes required accumulation operations twice using simulation accumulator.Because analog circuit is intrinsic Non-linear, completing so complicated computing can have a huge impact to result.

By observing above-mentioned operational formula the characteristic with reference to conventional recycle pattern number converter (ADC), inventor finds Can be by accumulation operations being dissolved in ADC and becoming the intrinsic part of its work process to the improvement of ADC structure.

The structure chart of conventional recycle type ADC and fundamental diagram, referring to Fig. 1, are carried out to input signal in a cycle Difference is fed back and carries out the quantization work of subsequent cycle after extract a quantized result by comparator by sampling Make.Due to value to be quantified of each cycle all than the previous cycle value few 1 in binary weights, therefore before circulation starts also Difference is carried out take advantage of 2 process to keep the amplitude range of input value.In order to incorporate accumulation function in conventional recycle type ADC, The present invention proposes a kind of new A DC structure, and structured flowchart and schematic diagram are referring to Fig. 2.Premise using this structure is input Signal must be discrete it is assumed that input signal expression formula is：

P [k]=Ic [k] (6)

P [k] is one of former formula T_ij,h.With unlike conventional recycle type ADC, mould to be quantified of each cycle Analog quantity is obtained from the P [k] newly inputting was added with the residual value in a upper cycle, therefore the peak value meeting of comparator input voltage Double, needing to maintain peak value using the circuit structure in Fig. 2 dotted line frame is normal value.This makes this arithmetic ADC each week Phase can obtain the digital code of 2 bits, is obtained by two comparators respectively, as shown in Figure 2.When all of input quantity all conveys After in ADC, ADC will be operated the digital code until creating N-bit according to the operation principle of conventional recycle type ADC.

Concrete operating principle is following it is assumed that this ADC quantified precision is N-bit, then the period 1 terminates rear residual value and is：

w₂[1]=2 (P [1]-d₁[1])-d₂[1] (7)

In the remaining N-1 cycle, residual value is：

w₂[k]=2 (P [k]+w₂[k-1]-d₁[k])-d₂[k], k=2,3..., N (8)

Can obtain after the residual value in this N number of cycle is carried out adding up according to its binary weights：

Above formula is entered and can obtain after line translation：

To T_ij,hJust the core coefficient after a conversion can be obtained, it can be seen that will count from formula (10) after carrying out adding up Calculate T_ij,hAlso the 2 bit number character codes extracting to be taken advantage of two with the operation being added, these operation need in the digital domain profit Completed with adder, as shown in figure 3, d1 and d2 will be transformed into numeric field from analog domain according to weight by this adder first carrying out Storage, then carry out add operation.

So far, complete the required accumulation operations of block matrix conversion during ADC quantization, and this structure is only than tradition The many analog comparaters of circular type ADC, but improve treatment effeciency and conversion accuracy.

For the more detailed operation principle illustrating this arithmetic type ADC, the quantizing process of concrete numerical value is presented below.

Hypothesis quantified precision is 8 bits, and comparator peak value is 3.3V, and reference voltage is 1.65V, and the discrete variable of input is 2V and 1V.Want to obtain be two input quantities add up by its binary weights and, then preferably result is 2V × 2-1+1V × 2-2=1.25V.

When completing above-mentioned cumulative process with this ADC, first, when the period 1 arrives, 2V is transported in ADC, obtains 2 ratios Special digital code is：1,0, residual volume is 0.7V.After second round arrives, residual volume 0.7V and second input variable 1V are added Input quantity 1.7V obtaining afterwards can be transported in ADC, and 2 bit number character codes of generation are：1,0, residual volume is 0.1V.So far, The sampling of all input signals completes, and next the residual volume of 0.1V is carried out with the operation principle according to conventional recycle type ADC Quantify until obtaining the digital code of 82 bits.Therefore 8 groups digital codes are respectively：1,0；1,0；0,0；0,0；0,0；0,0；0,1； 0,1.Therefore the value after quantization can be calculated according to formula (6) and be converted into decimal scale and be about 1.255, and desired result is similar.

Therefore this arithmetic type ADC can successfully accumulation operations be fused in the quantizing process of ADC.

Claims (3)

1. a kind of focal plane block matrix conversion row parallel arithmetic analog-digital converter, is characterized in that, including：First being sequentially connected adds Musical instruments used in a Buddhist or Taoist mass, second adder, multiplier, the 3rd adder；The output of first adder is also through first comparator and reference voltage Relatively, comparative result exports second adder；The output of multiplier is also compared with reference voltage through the second comparator, compares Result exports the 3rd adder；The output of the 3rd adder feeds back to first adder through chronotron；

Using discrete input signal P [k], as one of below equation T_ij,h：

$\underset{h=1}{\overset{H}{\Σ}}\underset{v=1}{\overset{V}{\Σ}}{C}_{hv}{I}_{hv}=\underset{h=1}{\overset{H}{\Σ}}{T}_{ij,h}$

The formula that above formula is changed for block matrix, wherein I_hvIt is the pixel value of correspondence position, C_hvIt is corresponding core coefficient；Each T_ijAll operated and obtained with accumulation operations by h × v multiplication, wherein h and v represents line number and the columns of image respectively；

Above-mentioned input signal is inputted aforementioned arithmetic analog-digital converter it is assumed that ADC quantified precision is N-bit, then the period 1 After end, residual value is：

w₂[1]=2 (P [1]-d₁[1])-d₂[1] (1)

In the remaining N-1 cycle, residual value is：

w₂[k]=2 (P [k]+w₂[k-1]-d₁[k])-d₂[k], k=2,3..., N (2)

Can obtain after the residual value in this N number of cycle is carried out adding up according to its binary weights：

$\underset{k=1}{\overset{N}{\Σ}}{2}^{-(k+1)}(2d_1\[k\]+d_2\[k\])=\underset{k=1}{\overset{N}{\Σ}}{2}^{-k}P\[k\]-2^{-(N+1)}{w}_2\[N\]---\left(3\right)$

Above formula is entered and can obtain after line translation：

$\underset{k=1}{\overset{N}{\Σ}}{2}^{-(k+1)}(2d_1\[k\]+d_2\[k\])=T_{ij,h}---\left(4\right)$

Wherein, w₂[k] represents the kth time output of the 3rd adder, d₁[k]、d₂[k] represents first comparator respectively, second compares The kth time output of device；

To T_ij,hObtain the core coefficient after a conversion after carrying out adding up, can be seen that T to be calculated from formula (4)_ij,hAlso to The 2 bit number character codes extracting are taken advantage of two with the operation being added, these operations need to complete using adder in the digital domain.

2. focal plane as claimed in claim 1 block matrix conversion row parallel arithmetic analog-digital converter, is characterized in that, multiplier is Paired multiplier.

3. focal plane as claimed in claim 1 block matrix conversion row parallel arithmetic analog-digital converter, is characterized in that, in numeric field Middle complete specifically using adder, adder first will be according to weight by d₁[k]、d₂[k] is transformed into numeric field from analog domain and enters Row storage, then carry out add operation.