CN103152049A - Successive approximation register type ADC (analog-digital converter) - Google Patents
Successive approximation register type ADC (analog-digital converter) Download PDFInfo
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- CN103152049A CN103152049A CN2013100609104A CN201310060910A CN103152049A CN 103152049 A CN103152049 A CN 103152049A CN 2013100609104 A CN2013100609104 A CN 2013100609104A CN 201310060910 A CN201310060910 A CN 201310060910A CN 103152049 A CN103152049 A CN 103152049A
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Abstract
The invention discloses a successive approximation register type ADC (analog-digital converter) comprising a sample holding circuit, a N-bit digital-analog converter, a comparer, a successive approximation register and a control logic, wherein the sample holding circuit finishes and holds the sample of an input signal through a sampling capacitor smaller than 2NC and a switch, and outputs sample holding voltage to a first input end of the comparer; the N-bit digital-analog converter is used for converting a digital quantization result saved in the successive approximation register into an analog quantity, and the output end of the N-bit digital-analog converter is connected with a second input end of the comparer; the comparer is used for comparing the analog quantities through conversion of the N-bit digital-analog converter with the sample holding voltage, outputting an existing result of quantizing the input signal, and writing the result into the successive approximation register; the successive approximation register is used for saving the result of quantizing the input signal and outputting the final result of analog-digital conversion; and the control logic is used for generating a control signal of a whole circuit. According to the successive approximation register type ADC disclosed by the invention, the conversion speed of ADC can be increased and the requirement on the output resistance of a signal source is reduced.
Description
Technical field
The present invention, about a kind of analog to digital converter, particularly relates to a kind of successive approximation register pattern number converter.
Background technology
Successive approximation register (successive approximation register, SAR) type simulated digital quantizer (Analog to Digital Converter, ADC) is the medium common structure to high-resolution applications of sampling rate lower than 5Msps (1,000,000 samplings of per second).The resolution of SAR ADC is generally 8 to 16, has the characteristics such as low-power consumption, small size.These characteristics make the type ADC have very wide range of application, such as portable/powered battery instrument, an input quantizer, Industry Control and data/signals collecting etc.
The basic block diagram that Fig. 1 is at present common successive approximation register type simulated digital quantizer.As shown in Figure 1, successive approximation register pattern number converter of the prior art comprises: the digital to analog converter (SH& that embeds sample/hold circuit (SH); DAC), comparator (CMP), SAR (successive approximation register) and control logic (Control Logic), analog input voltage (VIN) inputs to the digital to analog converter that embeds sample/hold circuit, SH& The DAC output is connected to the negative input end of comparator C MP, the positive input termination VREF/2 of comparator C MP, output termination SAR, SAR exports analog-to-digital result, and being connected to DAC, control logic is read in the clock etc. of SAR for the control signal that generates whole module as the RST that resets, sampling keep CKS, DAC capacitance switch control signal, comparative result.
Fig. 2 embeds the SH& of sample/hold circuit in Fig. 1; The thin portion connecting structure figure of DAC and comparator C MP.Below coordinate Fig. 2 that the operation principle of the SAR ADC of prior art is described: while starting ADC, control logic at first produce reset signal by switch N-1, switch N-2 ..., switch 1, switch 0 discharged with being switched to, during sampling, the high level of sampling inhibit signal CKS is connected the CKS switch, the common port of capacitor array (electric capacity upper end) is connected to VREF/2, control logic control switch N-1, switch N-2, ..., switch 1, switch 0 meets input signal VIN by the free end of N electric capacity (electric capacity lower end), form like this voltage VN=VREF/2-VIN on N electric capacity, the low level of sampling inhibit signal CKS disconnects the CKS switch, control logic is control switch N-1 simultaneously, switch N-2, ..., switch 1, switch 0 disconnects, the voltage VN=VREF/2-VIN that N electric capacity gathers while keeping sampling, while comparing for the first time, control logic is controlled MSB electric capacity 2
n-1the free termination reference voltage V REF of C, by MSB electric capacity 2
n-1the free end voltage of C is promoted to VREF, and this voltage is via MSB electric capacity 2
n-1c and all low level capacitances in series, the dividing potential drop produced at the common port of capacitor array is (2
n-1c)/(2
n-1c+2
n-2c+...+2C+C+C) * VREF=VREF/2, the common port of capacitor array (electric capacity upper end) voltage becomes VN1=VREF/2-VIN+VREF/2, this is comparator anti-phase input terminal voltage, and comparator in-phase input end voltage is VP=VREF/2, if VIN>VREF/2, VN1<VP, comparator is output as " 1 ", if VIN<VREF/2, VN1>VP, comparator is output as " 0 ", and it is D that the SAR register records this comparative result
n-1, and according to D
n-1control switch N-1 connects VREF and still connects ground GROUND, if D
n-1=" 1 " maintained switch N-1 is switched to VREF, otherwise is switched to ground GROUND, while comparing for the second time, control logic is controlled time high-order electric capacity 2
n-2the free termination reference voltage V REF of C, by inferior high-order electric capacity 2
n-2the free end voltage of C is promoted to VREF, and this voltage is via inferior high-order electric capacity 2
n-2c is connected with all other electric capacity, the dividing potential drop produced at the common port of capacitor array with on comparative result D once
n-1relevant.Work as D
n-1=1 o'clock this time dividing potential drop is (2
n-1c+2
n-2c)/(2
n-1c+2
n-2c+...+2C+C+C) * VREF=3*VREF/4=1*VREF/2+VREF/4; Work as D
n-1=0 o'clock this time dividing potential drop is (0+2
n-2c)/(2
n-1c+2
n-2c+...+2C+C+C) * VREF=VREF/4=0*VREF/2+VREF/4.So the common port of capacitor array (electric capacity upper end) voltage can be write as VN2=VREF/2-VIN+D
n-1* VREF/2+VREF/4, this is comparator anti-phase input terminal voltage, and comparator in-phase input end voltage is VP=VREF/2, if VIN>D
n-1* VREF/2+VREF/4, VN2<VP, comparator is output as " 1 ", if VIN<D
n-1* VREF/2+VREF/4, VN2>VP, comparator is output as " 0 ", and it is D that the SAR register records this comparative result
n-2, and according to D
n-2control switch N-2 connects VREF and still is connected to ground GROUND, if D
n-2=" 1 " maintained switch N-1 is switched to VREF, otherwise is switched to ground GROUND; By parity of reasoning, until the N time relatively obtains lowest order D
0logical value, the ADC EOC.
Yet but there is following shortcoming in existing this SAR ADC: during sampling, it is upper that all N+1 electric capacity all is connected to input signal VIN, its total capacitance C
sUM=2
n-1c+2
n-2c+......+2
1c+2
0c+C=2
nc is very large, this requires VIN to have very strong driving force, and a lot of occasion input signals are high resistants, there is no much driving forces, therefore use successive approximation register (SAR) analog to digital converter of prior art can have a strong impact on A/D conversion accuracy and speed.
Summary of the invention
For overcoming the problem of above-mentioned prior art, main purpose of the present invention is to provide a kind of successive approximation register pattern number converter, it is by using a sampling capacitance CS more much smaller than the total capacitance of prior art, the requirement of reduction to the driving force of input signal, make sampling to finish before estimating EOC first, can save like this clock cycle, thereby improve switching rate and reduce the requirement to signal source output impedance.
For reaching above-mentioned and other purpose, the present invention proposes a kind of successive approximation register pattern number converter, at least comprises:
Sampling hold circuit, by a ratio 2
nthe sampling capacitance that C is little and a switch complete sampling the maintenance to input signal, and the output sampling keeps the first input end of voltage to comparator;
N figure place weighted-voltage D/A converter, be converted into analog quantity for the digital quantization result that successive approximation register is preserved, the second input of its output termination comparator;
Comparator, keep voltage to compare for the analog quantity after this N figure place weighted-voltage D/A converter is transformed and this sampling, and export the current quantized result to this input signal, and result is write to successive approximation register;
Successive approximation register, for preserving the quantized result to this input signal, and export analog-to-digital final result; And
Control logic, for generating the control signal of whole circuit.
Further, this sampling capacitance is much smaller than 2
nc.
Further, this sampling capacitance can be as small as a specific capacitance of switched capacitor array.
Further, the specific capacitance that this sampling capacitance is 5 to 10 times.
Further, this sampling hold circuit connects the in-phase input end of this comparator, and this N figure place weighted-voltage D/A converter connects the inverting input of this comparator.
Further, this N figure place weighted-voltage D/A converter comprises that one by N electric capacity and an array that empty LSB electric capacity forms of arranging according to binary weighting, this N inverting input that is terminated at this comparator according to each electric capacity one in the electric capacity of binary weighting arrangement, the other end joins by two-way control switch and reference voltage or ground, this sky LSB electric capacity one is terminated at the inverting input of this comparator, other end ground connection.
Compared with prior art, a kind of successive approximation register pattern of the present invention number converter uses one than prior art total capacitance (C+C+2C+...+2 in sampling hold circuit
n-1c=2
nc) much smaller sampling capacitance CS is sampled to input signal and is kept, and has improved analog-to-digital speed.Because the little sampling time of sampling capacitance CS can be short a lot, little sampling capacitance CS can reduce the requirement to the driving force of input signal; Because sampling hold circuit (SH) and DAC electric capacity are on different paths, sampling can finish before estimating EOC first, can save like this clock cycle, thereby improves switching rate and reduce the requirement to signal source output impedance.
The accompanying drawing explanation
The basic block diagram that Fig. 1 is at present common successive approximation register type simulated digital quantizer;
Fig. 2 embeds the DAC of sample/hold circuit and the thin portion connecting structure figure of comparator in Fig. 1;
The circuit structure diagram that Fig. 3 is a kind of successive approximation register pattern of the present invention number converter
The connection detail structure chart that Fig. 4 is sampling hold circuit, DAC and comparator in preferred embodiment of the present invention;
The sequential chart of the control logic that Fig. 5 is Fig. 4;
The design frame chart of the successive approximation register pattern number converter of the 10bit that Fig. 6 is preferred embodiment of the present invention;
The simulation result figure of the control logic that Fig. 7 is preferred embodiment of the present invention;
The simulation result figure that Fig. 8 is DAC in preferred embodiment of the present invention;
The full wafer simulation result figure that Fig. 9 is preferred embodiment of the present invention.
Embodiment
Below, by specific instantiation accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention also can be different by other instantiation implemented or applied, the every details in this specification also can be based on different viewpoints and application, carries out various modifications and change not deviating under spirit of the present invention.
The circuit structure diagram that Fig. 3 is a kind of successive approximation register pattern of the present invention number converter.As shown in Figure 3, a kind of successive approximation register pattern of the present invention number converter at least comprises: sampling hold circuit (SH) 301, N position DAC302, comparator (CMP) 303, SAR304 and control logic (Control Logic) 305.
Wherein, sampling hold circuit 301 passes through one than prior art total capacitance (C+C+2C+...+2
n-1c=2
nc) much smaller sampling capacitance CS and K switch complete sampling the maintenance to input signal VIN, sampling keeps voltage to be connected to comparator 302 in-phase input ends, from the circuit aspect, the value of sampling capacitance CS can be as small as a specific capacitance C of switched capacitor array, consider the deviation of process aspect, the C value of getting 5 to 10 times in actual design is just enough; N position DAC302 is converted into for the digital quantization result that SAR304 is preserved the follow-up digital quantization that analog quantity is beneficial to analog input VIN, the inverting input of its output termination comparator 303; Comparator 303 keeps voltage to compare and export the current quantized result to input signal VIN for the analog quantity after DAC transforms that will quantize early stage with sampling, and result is write to SAR304; SAR304 is the quantized result to input signal VIN for preservation, and exports analog-to-digital final result; Control logic 305 control logics are read in the clock etc. of SAR for the control signal that generates whole circuit as the RST that resets, sampling keep CKS, DAC capacitance switch control signal, comparative result.
The connection detail structure chart that Fig. 4 is sampling hold circuit, DAC and comparator in preferred embodiment of the present invention.As shown in Figure 4, N position DAC302 comprises that one by N electric capacity and an array that " empty LSB " electric capacity forms of arranging according to binary weighting, this N inverting input that is terminated at comparator 303 according to each electric capacity one in the electric capacity of binary weighting arrangement, the other end is by two-way control switch (K
n-1, K
n-2, K
0) with reference voltage VREF and ground, join, " empty LSB " electric capacity one is terminated at the inverting input of comparator 303, other end ground connection.
The sequential chart that Fig. 5 is control logic in Fig. 4 of the present invention, below will coordinate Fig. 5 to further illustrate operation principle of the present invention.
Sampling time slot (CKS is high), sampling hold circuit (SH) 301 completes sampling the maintenance to input signal VIN, and this sampling keeps voltage to be connected to the comparator in-phase input end;
Simultaneously, during reset signal RST high level by the free ending grounding of DAC302, to the DAC capacitor discharge; Follow the high level control switch K of CKN-1
n-1the free end of the highest order MSB electric capacity of DAC302 is connected to VREF, the free ending grounding of other DAC electric capacity, this makes the output V (DACOUT) of DAC302=VREF/2, this output is connected to the inverting input of comparator 303, comparator 303 work, if VIN>VREF/2 MSB is " 1 ", otherwise is " 0 ", this result is preserved through delivering to SAR304; And then, the high level control switch N-2 of CKN-2 is connected to VREF by the free end of inferior high-order DAC electric capacity, the free end of other low levels DAC electric capacity is by respective switch ground connection, high-order (being now highest order MSB) has the content that SAR304 preserves to determine to connect VREF or ground, principle is that the preservation content is that height meets VREF, otherwise ground connection; So analogize until complete the output of lowest order LSB, ADC completes.
The design frame chart of the successive approximation register pattern number converter of the 10bit that Fig. 6 is preferred embodiment of the present invention.The simulation result figure of the control logic that Fig. 7 is preferred embodiment of the present invention, visible, the ADC of 10 more finally obtains ADC output through 10 times, and reset signal RST and sampled signal finish before relatively finishing for the first time, and sequential is correct.The simulation result figure that Fig. 8 is DAC in preferred embodiment of the present invention, it shows correct output required voltage.The full wafer simulation result figure that Fig. 9 is preferred embodiment of the present invention, ramp voltage is scanned, visible design is correct, be output as v (d9) v (d8) v (d7) v (d6) v (d5) v (d4) v (d3) v (d2) v (d1) v (d0), along with input voltage is low to high, visible output increases successively.
Visible, a kind of successive approximation register pattern of the present invention number converter uses one than prior art total capacitance (C+C+2C+...+2 in sampling hold circuit
n-1c=2
nc) much smaller sampling capacitance CS is sampled to input signal and is kept, and has improved analog-to-digital speed, experiment showed, 10 SAR type ADC of traditional structure, and sample phase generally needs 2 to 3 clock cycle; 12 SAR type ADC, sample phase generally needs 4 to 5 clock cycle; Its sampling of more high-resolution ADC needs the more clock cycle.And adopting structure of the present invention, sampling can only need a clock cycle.Because the little sampling time of sampling capacitance CS can be short a lot, little sampling capacitance CS can reduce the requirement to the driving force of input signal; Because sampling hold circuit (SH) and DAC electric capacity are on different paths, sampling can finish before estimating EOC first, can save like this clock cycle, thereby improves switching rate.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all can, under spirit of the present invention and category, modify and change above-described embodiment.Therefore, the scope of the present invention, should be as listed as claims.
Claims (6)
1. a successive approximation register pattern number converter at least comprises:
Sampling hold circuit, by a ratio 2
nthe sampling capacitance that C is little and a switch complete sampling the maintenance to input signal, and the output sampling keeps the first input end of voltage to comparator;
N figure place weighted-voltage D/A converter, be converted into analog quantity for the digital quantization result that successive approximation register is preserved, the second input of its output termination comparator;
Comparator, keep voltage to compare for the analog quantity after this N figure place weighted-voltage D/A converter is transformed and this sampling, and export the current quantized result to this input signal, and result is write to successive approximation register;
Successive approximation register, for preserving the quantized result to this input signal, and export analog-to-digital final result; And
Control logic, for generating the control signal of whole circuit.
2. a kind of successive approximation register pattern number converter as claimed in claim 1, it is characterized in that: this sampling capacitance is much smaller than 2
nc.
3. a kind of successive approximation register pattern number converter as claimed in claim 1, it is characterized in that: this sampling capacitance can be as small as a specific capacitance of switched capacitor array.
4. a kind of successive approximation register pattern number converter as claimed in claim 3, is characterized in that: the specific capacitance that this sampling capacitance is 5 to 10 times.
5. a kind of successive approximation register pattern number converter as claimed in claim 1, it is characterized in that: this sampling hold circuit connects the in-phase input end of this comparator, and this N figure place weighted-voltage D/A converter connects the inverting input of this comparator.
6. a kind of successive approximation register pattern number converter as claimed in claim 5, it is characterized in that: this N figure place weighted-voltage D/A converter comprises that one by N electric capacity and an array that empty LSB electric capacity forms of arranging according to binary weighting, this N inverting input that is terminated at this comparator according to each electric capacity one in the electric capacity of binary weighting arrangement, the other end joins by two-way control switch and reference voltage or ground, this sky LSB electric capacity one is terminated at the inverting input of this comparator, other end ground connection.
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