CN102595060A - Analog accumulator capable of implementing time delay integration (TDI) function inside complementary metal-oxide semiconductor (CMOS) image sensor - Google Patents

Abstract

The invention relates to the design field of analog integrated circuits. The technical scheme includes that an analog accumulator capable of implementing a TDI function inside a CMOS image sensor comprises two differential sample capacitors Cs+ and Cs-, fully differential operation, two input buses, two output buses, a n+1 group integrator, the CMOS-TID image sensor adopts roll exposure with an over-sampling rate of (n+1)/n, left electrode plates of sample capacitors Cs+ and Cs- are respectively connected with an array bus of a pixel array and a reference voltage Vref, and right electrode plates of sample capacitors Cs+ and Cs- are respectively connected with a positive input end and a negative input end of the fully differential operation, so that the CMOS image sensor can perform the TID function well and the application range of the TDI technology is extended. The analog accumulator is mainly applied to design and manufacture of semiconductor image sensors.

Description

The inner simulation accumulator of realizing the TDI function of cmos image sensor

Technical field

The present invention relates to the analog integrated circuit design field, specifically, relate to the simulation accumulator of the inner TDI of realization of cmos image sensor function.

Background technology

Imageing sensor can convert the light signal that camera lens obtains to and be easy to the electrical signal storing, transmit and handle.Imageing sensor can be divided into face formation and linear array type according to working method.The operation principle of face formation imageing sensor is to be the pel array that two-dimensional array arranges object to be taken to obtain two-dimensional image information; And the operation principle of linear array type imageing sensor is being pel array that one dimensional linear array arranges through the mode of object scanning shoot being obtained two-dimensional image information, and wherein the working method of linear array type imageing sensor can be with reference to figure 1.Various fields such as linear array type imageing sensor is widely used in its special working method and takes photo by plane, aerial image, machine vision and imaging of medical.But because object is moving all the time during the pixel exposure of online formation imageing sensor; Therefore the time for exposure of pixel seriously is subject to the translational speed of the relative subject of linear array type imageing sensor; Especially under high-speed motion low-light (level) applied environment the signal to noise ratio of (for example aerial image) linear array type imageing sensor (Signal to Noise Ratio SNR) can become very low.For solving the low problem of SNR; Someone has proposed the time delays integration, and (it can increase the SNR and the sensitivity of line scan image sensor for Time Delay Integration, TDI) technology; It is with its special scan mode; Through same target is carried out multiexposure, multiple exposure, realize very high SNR and sensitivity, therefore be specially adapted under the environment of high-speed motion low-light (level).The pel array that the basic principle of TDI is to use the face battle array to arrange is worked with the mode of linear array scanning; And then the pixel that can realize different rows is carried out multiexposure, multiple exposure to the same object in moving; And the result that will at every turn make public adds up; Equivalence has prolonged the exposure time of integration of pixel to object, therefore can significantly promote SNR and sensitivity.

The TDI technology be the earliest through charge coupled device (Charge Coupled Device, CCD) imageing sensor is realized, ccd image sensor also is a desirable device of realizing the TDI technology, it can realize that muting signal adds up.The TDI technology is applied in the ccd image sensor more at present; Rectangular Array CCD transducer of similar of the CCD-TDI imageing sensor that generally adopts; But its mode of sweeping with line is worked; As shown in Figure 2; The course of work of CCD-TDI imageing sensor is following: the n level CCD-TDI imageing sensor one total capable pixel of n; The a certain first directly output of the electric charge in first exposure cycle, collected of row pixel that lists, but the electric charge addition of in second exposure cycle, collecting with second pixel of same column are read according to the way of output of common line array CCD device after the electric charge collected for n-1 time of the electric charge collected of the pixel of CCD-TDI imageing sensor last column (n is capable) and front adds up by that analogy again.In the CCD-TDI imageing sensor; The amplitude of output signal is adding up of n pixel integration electric charge; Promptly be equivalent to collected electric charge in the pixel n times exposure cycle; Amplitude output signal enlarged n doubly and the amplitude of noise has only enlarged

doubly, so signal to noise ratio can improve doubly.

But because there are shortcomings such as the big integrated level of power consumption is low in ccd image sensor; Its application in every field is at present all being substituted by CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) imageing sensor gradually.If can realize TDI function (being the CMOS-TDI imageing sensor) through cmos image sensor, the cost of TDI camera will decline to a great extent and be more widely used so.In the prior art; Someone proposes to realize the CMOS-TDI imageing sensor through the method at the inner integrated analog signal accumulator of cmos image sensor; Be that the analog signal of pixel output is introduced into and accomplishes in the analog signal accumulator the adding up of identical exposure signal, the analog signal that then completion is added up is sent into ADC and is quantized output.But also there is not a kind of suitable simulation accumulator circuit to accomplish the TDI function in the prior art in cmos image sensor inside.

Summary of the invention

The present invention is intended to solve the deficiency that overcomes prior art; A kind of simulation accumulator is provided; Make cmos image sensor can realize the TDI function preferably, enlarge TDI The Application of Technology scope, for achieving the above object; The technical scheme that the present invention takes is; The inner simulation accumulator of realizing the TDI function of cmos image sensor comprises: it is that the drum-type of (n+1)/n is made public that two difference sampling capacitance Cs+ and Cs-, fully differential amplifier, two input buss, two output buss, n+1 group inte gration device, CMOS-TDI imageing sensor adopt over-sampling rate; The left pole plate of sampling capacitance Cs+ and Cs-be connected respectively on the column bus of pel array with certain reference voltage Vref on; The right pole plate of sampling capacitance Cs+ and Cs-is connected respectively to the positive and negative input of fully differential amplifier, and described two input buss are connected respectively to the positive and negative input of fully differential amplifier, and described two output buss are connected respectively to the positive and negative output of fully differential amplifier; Described n+1 group inte gration device is connected between input bus and the output bus, is respectively arranged with clock switch clk between the negative output terminal of fully differential amplifier and positive input terminal, positive output end and the negative input end.

The structure of group inte gration device is: integrating capacitor Ch1+ one end through and two switches connecing be connected to the input bus that links to each other with the negative input end of fully differential amplifier; One is reset switch Resetn in two switches; Another is the In switch, and this electric capacity other end is connected on the output bus that links to each other with the positive output end of fully differential amplifier through a switch; Another integrating capacitor Ch1-through and in addition two switches of connecing be connected to the input bus that links to each other with the positive input terminal of fully differential amplifier; One is reset switch Resetn in other two switches; Another is the In switch; N is the progression of corresponding integrator, and another integrating capacitor other end is connected to through a switch on the output bus that links to each other with the negative output terminal of fully differential amplifier, and aforementioned two integrating capacitors are connected between two end points of output bus and are provided with a switch.

Accumulator begins the signal of pixel 1 output of pel array is added up, and one group of signal of 1 pair of object A exposure of pixel back output is respectively pixel reset signal Vrst1 and pixel exposure signal V _Sig1, suppose that the 1st group inte gration device is corresponding in this moment pixel 1 and accumulator, the pixel column bus is exported V _Rst1During signal, the left polar plate voltage of sampling capacitance Cs+ at first becomes V _Rst1, this moment, clock switch clk was closed, reset switch Reset1 is closed, the I1 switch breaks off, the integrating capacitor in the 1st group inte gration device and left pole plate be connected respectively to the positive-negative input end of amplifier, and right pole plate short circuit is together, this moment sampling capacitance Cs+ and integrating capacitor C _H1+Middle charge stored summation is:

Q ₊＝C _s+×(V _rst1-V _{com_out})-C _h1+×V _os (1)

V wherein _{Com_out}Be fully differential amplifier output common mode voltage, simultaneously sampling capacitance C _S-With integrating capacitor C _H1-middle charge stored summation is:

Q _-＝C _s-×(V _ref-V _{com_out}) (2)

The signal of exporting when the pixel column bus becomes V _Sig1After, the left polar plate voltage of sampling capacitance Cs+ becomes V _Sig1, and sampling capacitance C _S-Left polar plate voltage still be V _RefConstant, this moment, clock switch clk broke off, and reset switch Reset1 breaks off, the I1 switch closure, and the charge stored summation is among sampling capacitance Cs+ and the integrating capacitor Ch1+ at this moment:

Q ₊＝C _s+×(V _sig1-V _{com_in})+C _h1+×(V _out--V _{com_in}-V _os) (3)

V wherein _{Com_in}Be amplifier common mode input, V _Out-Be accumulator negative output terminal, V _Out+Be the accumulator positive output end, simultaneously sampling capacitance C _S-With integrating capacitor C _H1-middle charge stored summation is:

Q _-＝C _s-×(V _ref-V _{com_in})+C _h1-×(V _out+-V _{com_in}) (4)

If sampling capacitance Cs+ is all Cs, integrating capacitor C mutually with the Cs-size _H1+And C _H1-Size is all C mutually _H1, therefore can draw according to the charge conservation equation:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})---\left(5\right)$

After pixel 2 was accomplished the exposure of A object, the signal of its output continued to be added to the first group inte gration device, and this moment, the output of accumulator became:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})]---\left(6\right)$

V wherein _Rst2And V _Sig2Be one group of signal of the 2 pairs of A objects of pixel exposure back output, n pixel is output as after the accumulator completion adds up for n time all the signal of output being added in the first group inte gration device after the exposure of A object, simulating at last one by one:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})+......+(V_{\mathrm{rstn}}-V_{\mathrm{sign}})]---\left(7\right)$

Signal after through the Read switch n time being added up at last reads in the level adc circuit of back and accomplishes signal quantization.

Technical characterstic of the present invention and effect:

Simulation accumulator of the present invention is eliminated the influence of offset voltage to simulation accumulator output result through input imbalance memory technology, reduced imageing sensor row fixed pattern noise (Fixed Pattern Noise, FPN).Continuously the Vrst of pixel output is sampled with Vsig through sampling capacitance and to realize that Vrst-Vsig handles, (Correlated Double Sample CDS) operates to accomplish correlated-double-sampling to pixel output signal.Integrating capacitor resets through the pole plate short circuit in the accumulator, and reset mode simply need not to introduce additional reference voltage.Can realize that through described simulation accumulator circuit to the adding up of voltage signal, adding up that the present invention proposes can directly be applied in the CMOS-TDI imageing sensor, realize the TDI technology better.

Description of drawings

Fig. 1 is the mode of operation sketch map of the line scan image sensor that provides of prior art.

Fig. 2 is the operation principle sketch map of the CCD-TDI imageing sensor that provides of prior art.

Fig. 3 is the circuit diagram of simulation accumulator provided by the invention.

Fig. 4 is the over-sampling exposure time series sketch map that prior art provides.

Fig. 5 is the control timing figure of simulation accumulator provided by the invention.

Fig. 6 is the concrete application example of simulation accumulator provided by the invention.

Embodiment

The circuit diagram of described simulation accumulator is with reference to figure 3, and it mainly comprises: sampling capacitance Cs, fully differential amplifier, two input buss, two output buss, n+1 group inte gration device, voltage source V os is used for representing the input offset voltage of amplifier.Make the CMOS-TDI imageing sensor adopt drum-type exposure the synchronism to realize different rows pixel to same object make public of over-sampling rate for (n+1)/n.So-called over-sampling rate is gone and is increased single exposure again and begin for the drum-type exposure of (the n+1)/n back the 1st of promptly in an exposure cycle, make public one by one from the 1st row pixel to the capable pixel of n, and the capable pixel of n can be exported n+1 data in an exposure cycle like this.In the pel array in capable pixel of n and the described accumulator corresponding relation of n+1 group inte gration device as shown in Figure 4, read line by line at an exposure cycle interior pixel array, and signal added up in the into corresponding integrator.Described accumulator adopts the fully differential structure; The left pole plate of its two difference sampling capacitance Cs+ and Cs-be connected respectively on the column bus of pel array with certain reference voltage Vref on; The right pole plate of sampling capacitance Cs+ and Cs-is connected respectively to the positive-negative input end of amplifier; Described two input buss are connected respectively to the input of amplifier, and described two output buss are connected respectively to the output of amplifier, and described n+1 group inte gration device is connected between input bus and the output bus.Wherein direct voltage source Vos is used to simulate the equivalent input noise voltage of fully differential amplifier, and this voltage source is necessary being in structure not.

The work schedule of accumulator is with reference to figure 4; Its course of work is following: after pixel 1 is to certain object A end exposure; Accumulator begins the signal of pixel 1 output is added up; Pixel 1 readout is exported one group of signal, is respectively pixel reset signal Vrst1 and pixel exposure signal Vsig1, supposes that the 1st group inte gration device is corresponding in this moment pixel 1 and accumulator.During pixel column bus output Vrst1 signal; The left polar plate voltage of sampling capacitance Cs+ at first becomes Vrst1; The switch closure of clk control this moment, the switch closure of Reset1 control, the switch of I1 control breaks off; Integrating capacitor Ch1+ in the 1st group inte gration device and the left pole plate of Ch1-are connected respectively to the positive-negative input end of amplifier, and right pole plate short circuit together.Because the storage of the right pole plate of integrating capacitor is differential signal, so its polar plate voltage can become the output common mode voltage of amplifier behind the short circuit, promptly accomplishes the reset operation to the electric charge in the integrating capacitor, this moment sampling capacitance Cs+ and integrating capacitor C _H1+Middle charge stored summation is:

Q ₊＝C _s+×(V _rst1-V _{com_out})-C _h1+×V _os (1)

V wherein _{Com_out}Be amplifier output common mode voltage, simultaneously sampling capacitance Cs-and integrating capacitor C _H1-Middle charge stored summation is:

Q _-＝C _s-×(V _ref-V _{com_out}) (2)

The signal of exporting when the pixel column bus becomes V _Sig1After, the left polar plate voltage of sampling capacitance Cs+ becomes V _Sig1, and the left polar plate voltage of sampling capacitance Cs-still is V _RefConstant, the switch that this moment, clk controlled breaks off, and the switch of Reset1 control breaks off, the switch closure of I1 control, sampling capacitance Cs+ and integrating capacitor C at this moment _H1+Middle charge stored summation is:

Q ₊＝C _s+×(V _sig1-V _{com_in})+C _h1+×(V _out--V _{com_in}-V _os) (3)

V wherein _{Com_in}Be amplifier common mode input, V _Out-Be accumulator negative output terminal, V _Out+Be the accumulator positive output end, simultaneously sampling capacitance Cs-and integrating capacitor C _H1-Middle charge stored summation is:

Q _-＝C _s-×(V _ref-V _{com_in})+C _h1-×(V _out+-V _{com_in}) (4)

Because the input of amplifier belongs to floating empty node, so sampling capacitance Cs+ and integrating capacitor C in these two processes _H1+Middle charge stored summation can not become, and promptly formula (1) equates with formula (3); This is equally applicable to sampling capacitance Cs-and integrating capacitor C _H1-, promptly formula (2) equates with formula (4), establishes sampling capacitance Cs+ and is all Cs, integrating capacitor C mutually with the Cs-size _H1+And C _H1-Size is all C mutually _H1, therefore can draw according to the charge conservation equation:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})---\left(5\right)$

After pixel 2 was accomplished the exposure of A object, the signal of its output continued to be added to the first group inte gration device, and this moment, the output of accumulator became:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})]---\left(6\right)$

V wherein _Rst2And V _Sig2Be one group of signal of the 2 pairs of A objects of pixel exposure back output, n pixel is output as after the accumulator completion adds up for n time all the signal of output being added in the first group inte gration device after the exposure of A object, simulating at last one by one:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})+......+(V_{\mathrm{rstn}}-V_{\mathrm{sign}})]---\left(7\right)$

Signal after through the Read switch n time being added up at last reads in the level adc circuit of back and accomplishes signal quantization; By above-mentioned visible; The simulation accumulator that the present invention describes was accomplished the CDS operation of input signal and the operation that adds up in a control clock cycle, had eliminated the influence of fully differential offset voltage to accumulator output result simultaneously.

For making the object of the invention, technical scheme and advantage more clear, will combine an instance to provide the specific descriptions of embodiment of the present invention below.The simulation accumulator that the present invention is proposed is applied in the cmos image sensor; Described imageing sensor framework is with reference to figure 6; Wherein pixel array sized is 128 row * 1024 row; The simulation accumulator adopts the row parallel schema, and the simulation accumulator carries out voltage accumulation with the exposure signal to same object of every row pixel output, will accomplish signal after adding up for 128 times at last and output to row and walk abreast and quantize among the monocline ADC; At last the digital signal of every row output is exported through the shift register serial, realized 128 grades of CMOS-TDI imageing sensors.

Claims (3)

1. the inner simulation accumulator of realizing the TDI function of a cmos image sensor; It is characterized in that; Comprise: two difference sampling capacitance Cs+ and Cs-, fully differential amplifier, two input buss, two output buss, n+1 group inte gration device; It is the drum-type exposure of (n+1)/n that the CMOS-TDI imageing sensor adopts over-sampling rate; The left pole plate of sampling capacitance Cs+ and Cs-be connected respectively on the column bus of pel array with certain reference voltage Vref on; The right pole plate of sampling capacitance Cs+ and Cs-is connected respectively to the positive and negative input of fully differential amplifier, and described two input buss are connected respectively to the positive and negative input of fully differential amplifier, and described two output buss are connected respectively to the positive and negative output of fully differential amplifier; Described n+1 group inte gration device is connected between input bus and the output bus, is respectively arranged with clock switch clk between the negative output terminal of fully differential amplifier and positive input terminal, positive output end and the negative input end.

2. simulation accumulator as claimed in claim 1 is characterized in that, the structure of group inte gration device is: an integrating capacitor C _H1+One end through and two switches connecing be connected to the input bus that links to each other with the negative input end of fully differential amplifier; One is reset switch Resetn in two switches; Another is the In switch, and this electric capacity other end is connected on the output bus that links to each other with the positive output end of fully differential amplifier through a switch; Another integrating capacitor C _H1-Through and in addition two switches of connecing be connected to the input bus that links to each other with the positive input terminal of fully differential amplifier; One is reset switch Resetn in other two switches; Another is the In switch; N is the progression of corresponding integrator, and another integrating capacitor other end is connected to through a switch on the output bus that links to each other with the negative output terminal of fully differential amplifier, and aforementioned two integrating capacitors are connected between two end points of output bus and are provided with a switch.

3. simulation accumulator as claimed in claim 2 is characterized in that, accumulator begins the signal of pixel 1 output of pel array is added up, and one group of signal of 1 pair of object A exposure of pixel back output is respectively pixel reset signal V _Rst1With pixel exposure signal V _Sig1, suppose that the 1st group inte gration device is corresponding in this moment pixel 1 and accumulator, the pixel column bus is exported V _Rst1During signal, the left polar plate voltage of sampling capacitance Cs+ at first becomes V _Rst1, this moment, clock switch clk was closed, reset switch Reset1 is closed, the I1 switch breaks off, the integrating capacitor in the 1st group inte gration device and left pole plate be connected respectively to the positive-negative input end of amplifier, and right pole plate short circuit is together, this moment sampling capacitance Cs+ and integrating capacitor C _H1+Middle charge stored summation is:

Q ₊＝C _s+(V _rst1-V _{com_out})-C _h1+V _os (1)

V wherein _{Com_out}Be fully differential amplifier output common mode voltage, simultaneously sampling capacitance C _S-With integrating capacitor C _H1-middle charge stored summation is:

Q _-＝V _s-(V _ref-V _{com_out}) (2)

The signal of exporting when the pixel column bus becomes V _Sig1After, the left polar plate voltage of sampling capacitance Cs+ becomes V _Sig1, and sampling capacitance C _S-Left polar plate voltage still be V _RefConstant, this moment, clock switch clk broke off, and reset switch Reset1 breaks off, the I1 switch closure, and the charge stored summation is among sampling capacitance Cs+ and the integrating capacitor Ch1+ at this moment:

Q ₊＝C _s+(V _sig1-V _{com_in})+C _h1+(V _out--V _{com_in}-V _os)?(3)

V wherein _{Com_in}Be amplifier common mode input, V _Out-Be accumulator negative output terminal, V _Out+Be the accumulator positive output end, simultaneously sampling capacitance C _S-With integrating capacitor C _H1-middle charge stored summation is:

Q _-＝C _s-(V _ref-V _{com_in})+C _h1-(V _out+-V _{com_in}) (4)

If sampling capacitance Cs+ is all Cs, integrating capacitor C mutually with the Cs-size _H1+And C _H1-Size is all C mutually _H1, therefore can draw according to the charge conservation equation:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})---\left(5\right)$

After pixel 2 was accomplished the exposure of A object, the signal of its output continued to be added to the first group inte gration device, and the output that simulate accumulator this moment becomes:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})]---\left(6\right)$

V wherein _Rst2And V _Sig2Be one group of signal of the 2 pairs of A objects of pixel exposure back output, n pixel is output as after the accumulator completion adds up for n time all the signal of output being added in the first group inte gration device after the exposure of A object, simulating at last one by one:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})+......+(V_{\mathrm{rstn}}-V_{\mathrm{sign}})]---\left(7\right)$

Signal after through the Read switch n time being added up at last reads in the level adc circuit of back and accomplishes signal quantization.

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