CN102611854B - Realization device of column-level analog-to-digital converter (ADC) in complementary metal-oxide semiconductor (CMOS) image sensor - Google Patents
Realization device of column-level analog-to-digital converter (ADC) in complementary metal-oxide semiconductor (CMOS) image sensor Download PDFInfo
- Publication number
- CN102611854B CN102611854B CN201210074364.5A CN201210074364A CN102611854B CN 102611854 B CN102611854 B CN 102611854B CN 201210074364 A CN201210074364 A CN 201210074364A CN 102611854 B CN102611854 B CN 102611854B
- Authority
- CN
- China
- Prior art keywords
- switch
- adc
- digital converter
- analog
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The invention relates to the field of analog integrated circuit design. In order to provide an analog-to-digital converter (ADC) structure which has a simple structure and a short conversion cycle, and achieve the purpose of improving the dynamic scope of a sensor, the technical adopts the following technical scheme that: a realization device of a column-level ADC in complementary metal-oxide semiconductor (CMOS) image sensor comprises a single-slope ADC, a successive approximation ADC and two slope signal generators; the single-slope ADC, the successive approximation ADC and a group of six switches form a unit, and each column in a sensor pixel array is provided with the unit; and two slope signal generators are shared by each column of the sensor pixel array. The realization device of the column-level ADC in the CMOS image sensor is mainly applied in the design and manufacturing of the semi-conductor image sensor.
Description
Technical field
The present invention relates to analog integrated circuit design field, relate in particular to the implement device of a kind of row level ADC applying in imageing sensor, be i.e. the implement device of row level ADC in cmos image sensor.
Background technology
Along with developing rapidly of digital technology, semiconductor fabrication, cmos image sensor becomes object current and that future market is paid close attention to.At present, the analog to digital converter (ADC) being applied in cmos image sensor has three kinds of different types: Pixel-level, row level, chip-scale.Fig. 1 is row level ADC Organization Chart, and row level ADC compares with chip-scale ADC, low to ADC rate request, has therefore reduced power consumption and the design difficulty of chip.Row level ADC compares with Pixel-level ADC simultaneously, and ADC is by transferring in pixel outside pel array, and this has improved fill factor, curve factor greatly, thereby has improved the sensitivity of imageing sensor.Therefore row level ADC has a wide range of applications in imageing sensor.But the layout size of row level ADC is subject to the restriction of Pixel Dimensions, this has increased the layout design difficulty of row level ADC.
Monocline ADC (SS ADC, Single Slope ADC) and successive approximation analog to digital C (SA ADC, Successive Approximation ADC) are two kinds of common implementations in row level ADC.Fig. 2 is N position SS adc circuit structure chart, and in cmos image sensor, all row SS ADC share Yi Ge slope, and each row only needs a comparator and 1 N bit register, so simplicity of design, and every row chip area is little, is easy to realize.The shortcoming of SS ADC is that the change-over period is long, and N position SS ADC needs 2
n-1 clock cycle just can complete once conversion.Fig. 3 is N position SAADC circuit structure diagram, compare with SS ADC, the change-over period of SA ADC is very short, the SA ADC of N position only needs N clock cycle just can complete once conversion, its shortcoming is that each row all needs a complete N position ADC, therefore the chip area of every row is very large, has increased design difficulty.
Summary of the invention
The present invention is intended to solution and overcomes the deficiencies in the prior art, the row level ADC that a kind of chip area is little, the change-over period is little structure is provided, the technical scheme that the present invention takes is, the implement device of row level ADC in a kind of cmos image sensor, it is characterized in that, comprising: two ramp signal generators, pulse latches, M bit register, gradually-appoximant analog-digital converter; Pulse latches, M bit register, gradually-appoximant analog-digital converter and one group of 6 switch form Yi Ge unit; In sensor pixel array, every row are provided with an aforementioned unit;
Two ramp signal generators are that the every row of sensor pixel array share, two ramp signal generators are corresponding respectively provides height reference potential by the 4th switch in one group of 6 switch, the 5th switch for gradually-appoximant analog-digital converter, and one of them ramp signal generator is connected to the comparator inverting input of monocline analog to digital converter by the 1st switch in one group of 6 switch;
In sensor pixel array, the output of every row is connected to the in-phase input end of the comparator of monocline analog to digital converter, and the output of the comparator of monocline analog to digital converter connects the pulse latches of monocline analog to digital converter after by the 6th switch in one group of 6 switch successively, high M bit register carries out high M position and exports;
The N-M figure place weighted-voltage D/A converter of gradually-appoximant analog-digital converter is connected to the comparator inverting input of monocline analog to digital converter by the 2nd switch in one group of 6 switch, the N-M position logic control of gradually-appoximant analog-digital converter is connected to the output of the comparator of monocline analog to digital converter by the 3rd switch in one group of 6 switch;
The 1st switch in one group of 6 switch, the 6th switch gearing; The 2nd switch in one group of 6 switch, the 3rd switch gearing; The high level pulse that pulse latches produces is controlled the 4th switch, the 5th switch gearing.
Between the 4th switch, the 5th switch and gradually-appoximant analog-digital converter, pass through respectively a capacity earth.
Described N < 15, M < N.
Technical characterstic of the present invention and effect:
Of the present invention is that row level SS ADC and row level SAADC are combined, utilize SS ADC to carry out high position data conversion, utilize SA ADC to carry out low data conversion, because SS ADC only need to carry out high-order portion data transaction, switching rate is compared with independent SS ADC and is index lifting, meanwhile, and because SA ADC only need to carry out low portion data transaction, every row chip area is compared and is index decreased with independent SAADC, thus the good compromise of the speed of obtaining and area.
Accompanying drawing explanation
Fig. 1 is listed as a grade ADC Organization Chart.
The row level SS adc circuit structure chart that Fig. 2 is traditional.
The row level SA adc circuit structure chart that Fig. 3 is traditional.
Fig. 4 row level provided by the invention adc circuit structure chart.
The fundamental diagram of Fig. 5 row level provided by the invention ADC.
Embodiment
Take the scheme shown in Fig. 4 as example, all row share Liang Ge slope, produce the binary system code value on slope 1 than producing the binary system code value Duo Yiwei， slope 1 on slope 2 and signal that slope 2 produces and receive respectively by sampling hold circuit and voltage buffer (buffer) in the SA ADC of every row on the needed height reference voltage of DAC.The required circuit structure of every row and SA ADC are similar, but have increased switch S 4, S5 and sampling capacitance C1, C2 and two buffer.The comparator negative terminal of each row has double switch, and when carrying out the conversion of high M position, comparator negative terminal connects the ramp signal that slope 1 produces; When carrying out the conversion of low N-M position, negative terminal connects the signal that in SAADC, DAC produces, so SS ADC and the shared comparator of SAADC.
Operation principle is as follows:
First stage: first outside sequencing control switch S 1, S6 closure, switch S 2, S3 disconnect, the ramp signal vramp1 that slope 1 produces receives the negative terminal of comparator, the input signal vin that the positive termination of comparator need to be changed, the SS ADC that at this moment integrated circuit provided by the invention is equivalent to a M position is in work.Quantizing process is as shown in Fig. 5-1, when vin is greater than vramp1, comparator overturns, pulse latches produces high level pulse, the high M bit code value of changing out is deposited in high M bit register, high level pulse control switch S4 meanwhile, S5 is closed, vramp1 and vramp2 corresponding when comparator is overturn sample sampling capacitance C1, on C2, then high level pulse finishes, pulse latches output low level, control switch S4, S5 disconnects, sampling capacitance C1, magnitude of voltage on C2 remains comparator vramp1 corresponding to when upset, the magnitude of voltage of vramp2, these two voltages provide needed height reference voltage to DAC respectively by buffer.
Second stage: outside sequencing control switch S 2, S3 closure, switch S 1, S6 disconnect.Quantizing process is as shown in Fig. 5-2, and now the height reference voltage of DAC is between the sloped region at first stage vin place, and SAADC only need to successively approach vin in this interval.At this moment circuit provided by the invention is equivalent to the SAADC of a N-M position.After N-M clock cycle, the output valve Vout SA of DAC equals vin within the scope of error requirements, and logic control element has produced corresponding low N-M code value simultaneously, and this code value and high M bit code merge the complete N bit code value of last output.
N provided by the invention ranks in grade ADC, and SS ADC is partly responsible for conversion high M position, and SA ADC is partly responsible for conversion low N-M position (M < N).
The speed ratio of N provided by the invention position ADC and N position SS ADC is: N position SS ADC required change-over time is 2
n-1 clock cycle, be 2 the change-over time of N provided by the invention position ADC
mthe individual clock cycle of-1+ (N-M), than SS ADC speed, be index and promote.
The chip area comparison of N provided by the invention position ADC and N position SA ADC: N position SA ADC comprises a N position DAC, a comparator and a N position logic control element, wherein most of area is shared by N position DAC, adopts the N position DAC of traditional binary capacitance structure to need 2
nindividual specific capacitance.N provided by the invention position ADC increases Liao Liangge slope, switch S 1-S6, capacitor C 1-C2 and two buffer memory buffer than N position SAADC, and N position DAC is reduced to N-M position DAC simultaneously, and the logic control of N position is reduced to the logic control of N-M position.Because Liang Ge slope is that all row share, the area therefore increasing than the whole chip area ，Zhe Liangge slope of all row is negligible.Because the logic control of N position is reduced to the logic control of N-M position, the logic control of N-M position with lacked M switch being connected of DAC, therefore, the switch S 1-S6 of increase can not increase area substantially.Therefore because buffer only drives the electric capacity in row, so the area of buffer is less, and two the buffer areas and two electric capacity (C1, the C2) area that increase are very little.But because SAADC part only need to be changed N-M position, so adopt the DAC of traditional binary capacitance structure only to need 2
n-Mindividual specific capacitance, therefore than DAC in the SA ADC of N position required 2
nindividual specific capacitance DAC chip area of the present invention is index decreased.Because DAC has taken the overwhelming majority of whole chip area, so the required chip area of N provided by the invention position ADC is compared and is index decreased with N position SAADC.
For the row provided by the invention level ADC of 10 precision, it is high 5 that SS ADC is partly responsible for conversion, and it is low 5 that SAADC is partly responsible for conversion, i.e. M=5, N=10.
The speed ratio of 10 ADC provided by the invention and 10 SS ADC is: during 10 required conversions of SS ADC, be 1023 clock cycle, be 36 clock cycle the change-over time of 10 ADC provided by the invention, and its conversion speed is about 28 times of 10 SS ADC conversion speeds.
The chip area comparison of 10 ADC provided by the invention and 10 SAADC: 10 the every row of SAADC DAC need 1024 specific capacitances, 10 the every row of ADC DAC provided by the invention need 32 specific capacitances, and the required DAC area of its every row is 3.1% of SAADC.
Row level ADC execution mode provided by the invention had both met 10 required precisions, can realize again the best compromise of speed and area.
N=14, M=12 or 13; Or N=2, under the limiting case of M=1, the present invention still can bring into play good effect, and just at N=10, under the situation of M=5, compromise effect is better.
Claims (3)
1. an implement device of row levels ADC in cmos image sensor, is characterized in that, comprising: the comparator of two ramp signal generators, pulse latches, M bit register, gradually-appoximant analog-digital converter, monocline analog to digital converter; The comparator of pulse latches, M bit register, gradually-appoximant analog-digital converter, monocline analog to digital converter and one group of 6 switch form Yi Ge unit; In sensor pixel array, every row are provided with an aforementioned unit;
Two ramp signal generators are that in sensor pixel array, all row share, two ramp signal generators are corresponding respectively provides height reference potential by the 4th switch in one group of 6 switch, the 5th switch for gradually-appoximant analog-digital converter, and one of them ramp signal generator is connected to the comparator inverting input of monocline analog to digital converter by the 1st switch in one group of 6 switch;
In sensor pixel array, the output of every row is connected to the in-phase input end of the comparator of monocline analog to digital converter, and the output of the comparator of monocline analog to digital converter connects the pulse latches of monocline analog to digital converter after by the 6th switch in one group of 6 switch successively, high M bit register carries out high M position and exports;
The N-M figure place weighted-voltage D/A converter of gradually-appoximant analog-digital converter is connected to the comparator inverting input of monocline analog to digital converter by the 2nd switch in one group of 6 switch, the N-M position logic control of gradually-appoximant analog-digital converter is connected to the output of the comparator of monocline analog to digital converter by the 3rd switch in one group of 6 switch;
The 1st switch in one group of 6 switch, the 6th switch gearing; The 2nd switch in one group of 6 switch, the 3rd switch gearing; The high level pulse that pulse latches produces is controlled the 4th switch, the 5th switch gearing.
2. the implement device of row level ADC in cmos image sensor as claimed in claim 1, is characterized in that, passes through respectively a capacity earth between the 4th switch, the 5th switch and gradually-appoximant analog-digital converter.
3. the implement device of row level ADC in cmos image sensor as claimed in claim 1, is characterized in that described N < 15, M < N.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210074364.5A CN102611854B (en) | 2012-03-20 | 2012-03-20 | Realization device of column-level analog-to-digital converter (ADC) in complementary metal-oxide semiconductor (CMOS) image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210074364.5A CN102611854B (en) | 2012-03-20 | 2012-03-20 | Realization device of column-level analog-to-digital converter (ADC) in complementary metal-oxide semiconductor (CMOS) image sensor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102611854A CN102611854A (en) | 2012-07-25 |
| CN102611854B true CN102611854B (en) | 2014-01-15 |
Family
ID=46528990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210074364.5A Expired - Fee Related CN102611854B (en) | 2012-03-20 | 2012-03-20 | Realization device of column-level analog-to-digital converter (ADC) in complementary metal-oxide semiconductor (CMOS) image sensor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102611854B (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8969774B2 (en) * | 2012-12-27 | 2015-03-03 | Omnivision Technologies, Inc. | Conversion circuitry for reducing pixel array readout time |
| CN103595411A (en) * | 2013-10-14 | 2014-02-19 | 天津市晶奇微电子有限公司 | Single-ramp ADC digital correlative double-sampling circuit of CMOS imaging sensor |
| US9906745B2 (en) * | 2013-12-12 | 2018-02-27 | Cista System Corp. | Column comparator system and method for comparing a ramping signal and an input signal |
| CN103746694B (en) * | 2014-01-14 | 2017-02-01 | 复旦大学 | Slope conversion circuit applied to two-step type integral analog-to-digital converter |
| WO2016029858A1 (en) * | 2014-08-28 | 2016-03-03 | Mediatek Inc. | Hybrid analog-to-digital converter using digital slope analog-to-digital converter and related hybrid analog-to-digital conversion method thereof |
| CN106209091B (en) * | 2015-07-18 | 2019-07-19 | 芯视达***公司 | The implementation method of the ramp signal of slope duration variation |
| CN105262488A (en) * | 2015-10-22 | 2016-01-20 | 天津大学 | Column-level ADC for high-speed linear CMOS image sensor and implement method |
| CN106130559A (en) * | 2016-06-17 | 2016-11-16 | 中国科学院微电子研究所 | A kind of high accuracy row level analog-digital converter and D conversion method thereof |
| CN106657833A (en) * | 2016-11-04 | 2017-05-10 | 刘强 | Column level ADC (Analog to Digital Converter) circuit for CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor |
| CN107896308B (en) * | 2017-10-27 | 2020-08-18 | 天津大学 | Pulse array type retina-imitating image sensor |
| CN107734273B (en) * | 2017-10-27 | 2019-11-05 | 中国电子科技集团公司第四十四研究所 | For arranging the high-speed data reading circuit of grade ADC framework cmos image sensor |
| CN108988862A (en) * | 2018-08-13 | 2018-12-11 | 中国科学院微电子研究所 | Analog-digital converter and D conversion method |
| CN112398477B (en) * | 2019-08-13 | 2023-03-24 | 天津大学青岛海洋技术研究院 | Monoclinic ADC circuit structure with condition-dependent multi-sampling technology |
| US11196949B2 (en) * | 2019-10-02 | 2021-12-07 | Omnivision Technologies, Inc. | Subrange ADC for image sensor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347769A (en) * | 2011-05-26 | 2012-02-08 | 天津大学 | Control circuit of analog-to-digital converter and control method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7015844B1 (en) * | 2004-08-30 | 2006-03-21 | Micron Technology, Inc. | Minimized SAR-type column-wide ADC for image sensors |
| KR100843554B1 (en) * | 2006-08-31 | 2008-07-04 | 삼성전자주식회사 | Multi-channel pipelined signal converter |
-
2012
- 2012-03-20 CN CN201210074364.5A patent/CN102611854B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347769A (en) * | 2011-05-26 | 2012-02-08 | 天津大学 | Control circuit of analog-to-digital converter and control method thereof |
Non-Patent Citations (6)
| Title |
|---|
| Martijn F.Snoeij 等.Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors.《IEEE JOURNAL OF SOLID-STATE CIRCUITS》.2007,第42卷(第12期),2968-2977. |
| Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors;Martijn F.Snoeij 等;《IEEE JOURNAL OF SOLID-STATE CIRCUITS》;20071231;第42卷(第12期);349-353 * |
| 一种用于CMOS图像传感器的Column-Level模数转换器;王亚杰 等;《光电子·激光》;20060331;第17卷(第3期);290-294 * |
| 张娜 等.用于CMOS图像传感器的列并行高精度ADC.《固体电子学研究与进展》.2006,第26卷(第3期),349-353. |
| 王亚杰 等.一种用于CMOS图像传感器的Column-Level模数转换器.《光电子·激光》.2006,第17卷(第3期),290-294. |
| 用于CMOS图像传感器的列并行高精度ADC;张娜 等;《固体电子学研究与进展》;20060831;第26卷(第3期);2968-2977 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102611854A (en) | 2012-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102611854B (en) | Realization device of column-level analog-to-digital converter (ADC) in complementary metal-oxide semiconductor (CMOS) image sensor | |
| CN102801422B (en) | Gradual approaching A/D converter | |
| CN103986470B (en) | Low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and converter | |
| US8717221B2 (en) | Successive approximation register analog-to-digital converter | |
| CN101729069B (en) | Successive approximation type analog-to-digital converter with binary fault tolerant mechanism | |
| CN102545902B (en) | Multistep single-ramp analog digital signal conversion device | |
| KR102431242B1 (en) | Successive approximation register analog-digital converting apparatus and system, and cmos image sensor thereof | |
| CN102111156B (en) | Successive approximation register analog-to-digital conversion circuit for realizing minimal dynamic range | |
| CN105811986B (en) | A kind of Approach by inchmeal adc circuit of high-speed transitions | |
| CN105007079A (en) | Fully differential increment sampling method of successive approximation type analog-digital converter | |
| CN104967451A (en) | Successive approximation type analog-to-digital converter | |
| CN108306644B (en) | Front-end circuit based on 10-bit ultra-low power consumption successive approximation type analog-to-digital converter | |
| CN104320141B (en) | A kind of bit stream line type gradually-appoximant analog-digital converter of low-power consumption 12 | |
| CN105187065A (en) | Successive approximation ADC ultra-low power consumption capacitor array and logic control method thereof | |
| CN103595412A (en) | Low-power-consumption small-area capacitor array and reset method and logic control method thereof | |
| CN103532553A (en) | Time domain ADC based on cycle time digital converter | |
| CN113193870A (en) | SAR ADC with low power consumption and low layout area | |
| CN104333352B (en) | Ramp generator and imageing sensor | |
| CN204376879U (en) | There is the SAR ADC of mixed type DAC capacitor array structure | |
| CN108111171A (en) | Suitable for differential configuration gradual approaching A/D converter dullness formula method of switching | |
| CN219555082U (en) | Analog-to-digital converter and readout circuit | |
| CN112332847A (en) | Two-level switching method applied to successive approximation type analog-to-digital converter | |
| JP5695629B2 (en) | Successive comparison type A / D converter and multi-bit delta-sigma modulator using the same | |
| CN104779957A (en) | High-speed successive approximation analog-to-digital converter | |
| US8928516B2 (en) | Method and apparatus for conversion of voltage value to digital word |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140115 Termination date: 20210320 |