CN103021943B - 阵列基板及其制造方法、显示装置 - Google Patents
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Abstract
本发明提供了一种阵列基板及其制造方法、显示装置,其中制造方法包括:步骤A、在基板的一侧依次形成第一导电层、源漏电极、有源层和绝缘层的图形,其中所述绝缘层上设置有至少一个过孔;步骤B、在形成所述第一导电层、源漏电极、有源层和绝缘层的基板上依次形成栅金属层和钝化层,其中所述栅金属层包括栅电极和栅线,所述栅金属层通过所述至少一个过孔与所述第一导电层连接,形成将静电疏散的通路。可以在Array工艺中提前多步工艺完成ESD回路的形成,使ESD组件充分发挥其疏散电荷的作用,有效的降低了ESD的发生率。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种阵列基板及其制造方法、显示装置。
背景技术
高级超维场转换技术(Advanced Super Dimension Switch,简称ADS),通过同一狭缝电极边缘所产生的电场及狭缝电极层与板状电极层间产生的电场形成多维电场,使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转,从而提高了液晶工作效率并增大了透光效率。高级超维场开关技术可以提高TFT-LCD(Thin Film Transistor-Liquid Crystal Display,薄膜场效应晶体管液晶显示器)产品的画面品质,具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹等优点。
ADS液晶显示器与其他显示器相比具有扩大视角的优点,在当前平板显示器市场占据了重要的地位。然而对于ADS液晶显示器来说,阵列基板及其制造工艺决定了其产品的性能和价格。该阵列基板在传统的工艺在Array段工艺过程中,会随着像素区内的TFT沉积形成的同时形成防静电的ESD(Electro-Static discharge,静电释放)组件回路,但是ESD回路往往形成于Array工艺的后期(像素电极沉积之后),因此在Array工艺中,ESD组件还不能发挥其防静电的作用,造成诸多此阶段由静电引发的各种不良。
发明内容
为了解决上述技术问题,本发明提供一种阵列基板及其制造方法、显示装置,使ESD组件充分发挥其疏散电荷的作用,有效的降低了ESD的发生率。
根据本发明的一个方面,提供了一种阵列基板的制造方法,包括:步骤A、在基板的第一表面依次形成第一导电层、源漏电极、有源层和绝缘层的图形,其中所述绝缘层上设置有至少一个过孔;步骤B、在形成所述第一导电层、源漏电极、有源层和绝缘层的基板上依次形成栅金属层和钝化层,其中所述栅金属层包括栅电极和栅线,所述栅金属层通过所述至少一个过孔与所述第一导电层连接,形成将静电疏散的通路。
根据本发明的另一个方面,提供了一种阵列基板,包括:基板;基板的第一表面依次形成有第一导电层、源漏电极、有源层和绝缘层的图形,其中所述绝缘层上设置有至少一个过孔;在形成有所述第一导电层、源漏电极、有源层和绝缘层的基板上依次形成有栅金属层和钝化层,其中所述栅金属层包括栅电极和栅线,所述栅金属层通过所述至少一个过孔与所述第一导电层连接,形成将静电疏散的通路。
根据本发明的又一个方面,提供了一种显示装置,包括如上所述的阵列基板。
由上述技术方案可知,本发明的实施例具有如下有益效果:可以在Array工艺中提前多步工艺完成ESD回路的形成,使ESD组件充分发挥其疏散电荷的作用,有效的降低了ESD的发生率,减少了ESD所造成的诸多电学不良。
附图说明
图1表示本发明的一个实施例中阵列基板的制造方法的流程图;
图2表示执行图1中制造方法的步骤S101后对应的阵列基板的截面示意图;
图3表示执行图1中制造方法的步骤S102后对应的阵列基板的截面示意图;
图4表示执行图1中制造方法的步骤S103后对应的阵列基板的截面示意图;
图5表示执行图1中制造方法的步骤S104后对应的阵列基板的截面示意图;
图6表示执行图1中制造方法的步骤S105后对应的阵列基板的截面示意图;
图7表示执行图1中制造方法的步骤S106后对应的阵列基板的截面示意图;
图8表示执行图1中制造方法的步骤S107后对应的阵列基板的截面示意图;
图9表示本发明的实施例中阵列基板的结构示意图。
具体实施方式
为了使本发明实施例的目的、技术方案和优点更加清楚明白,下面结合实施例和附图,对本发明实施例做进一步详细地说明。在此,本发明的示意性实施例及说明用于解释本发明,但并不作为对本发明的限定。
在现有的TFT-LCD工艺中,ESD组件有效的起到将工艺中产生的电荷均匀扩散的作用,但是传统的ESD回路均是在ITO(氧化铟锡)层沉积后(即Array工艺结束后)才得以形成,因此在Array工艺过程中ESD组件不能发挥其扩散电荷的作用。本发明的实施例以ADS模式产品为例,改变源漏电极、有源层、栅金属层的沉积顺序,相比于传统的Array工艺可以提前形成ESD回路,有效的减少了Array段ESD对膜层以及像素造成的破坏。
根据本发明的一个实施例,首先在基板的第一表面依次形成第一导电层、源漏电极、有源层和绝缘层的图形,其中绝缘层上设置有至少一个过孔;然后在形成绝缘层的基板上依次形成栅金属层和钝化层,其中栅金属层包括栅电极和栅线,栅金属层通过至少一个过孔与第一导电层连接,形成将静电疏散的通路。
具体地,结合图1~图8来描述本发明的一个实施例中阵列基板的制造方法100的流程,该制造方法100包括以下步骤:
步骤S101、在基板1的第一表面上形成第一导电层2的图形;
步骤S102、在形成第一导电层2的基板1上形成源漏电极3的图形;
步骤S103、在形成源漏电极3的基板1上形成有源层4的图形;
步骤S104、在形成有源层4的基板1上形成绝缘层5,该绝缘层5上包括至少一个过孔9。
步骤S105、在形成绝缘层5的基板上形成栅金属6的图形,其中栅金属层6包括栅电极和栅线,栅金属层6通过至少一个过孔9与第一导电层2连接,形成将静电疏散的通路。
步骤S106、在形成栅金属层6的基板1上形成钝化层7的图形。
步骤S107、在基板1的第二表面形成用于作为有效显示区域(AA)的公共电极的第二导电层8的图形。
根据本发明的一个实施例,第一导电层2和第二导电层8的材料为透明导电材料。可选地,透明导电材料为铟锡氧化物。
本发明通过改变Array工艺中各膜层的沉积顺序及刻蚀步骤,达到了使TFT-LCD工艺中用于防止静电发生的ESD回路提前形成的效果,从而解决了ESD组件在Array工艺后期才能形成,不能尽早发生作用,导致ESD高发的技术问题。
具体地,首先提前实现ESD回路,有效降低了静电对产品造成的破坏。而且过孔9的下端的金属层的材料可选用ITO,相对于传统的金属更为稳定不易被氧化。其次过孔9处沉积金属,从导电性角度考虑,要优于传统的过孔处沉积ITO的导电性。最后相对于传统的工艺,大量减少了过孔的数量,减少了由于过孔处接触问题造成不良的几率。
参见图9,表示本发明的实施例中阵列基板900的结构示意图,该阵列基板900包括:
基板1;
在基板1的第一表面依次形成有第一导电层2、源漏电极3、有源层4和绝缘层5的图形,其中绝缘层5上设置有至少一个过孔9;
在形成绝缘层5的基板1上依次形成栅金属层6和钝化层7,其中栅金属层6包括栅电极和栅线,栅金属层6通过至少一个过孔9与第一导电层2连接,形成将静电疏散的通路。
根据本发明的另一个实施例,在基板1的第二表面形成有用于作为有效显示区域的公共电极的第二导电层8的图形。
可选地,第一导电层2和第二导电层8的材料为透明导电材料。例如透明导电材料为铟锡氧化物(ITO)。
本发明的实施例还提供一种显示装置,该显示装置包括如上所述的阵列基板。该显示装置可以为:液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (5)
1.一种阵列基板的制造方法,其特征在于,包括:
步骤A、在基板的第一表面依次形成第一导电层、源漏电极、有源层和绝缘层的图形,其中所述绝缘层上设置有至少一个过孔;
步骤B、在形成所述第一导电层、源漏电极、有源层和绝缘层的基板上依次形成栅金属层和钝化层,其中所述栅金属层包括栅电极和栅线,所述栅金属层通过所述至少一个过孔与所述第一导电层连接,形成将静电疏散的通路。
2.根据权利要求1所述的制造方法,其特征在于,所述步骤A包括:
步骤A1、在所述基板的第一表面形成第一导电层的图形;
步骤A2、在形成所述第一导电层的基板上形成源漏电极的图形;
步骤A3、在形成所述源漏电极的基板上形成有源层的图形;
步骤A4、在形成所述有源层的基板上形成绝缘层,所述绝缘层上包括至少一个过孔。
3.根据权利要求1~2任一所述的制造方法,其特征在于,所述方法还包括:
在所述基板的第二表面形成用于作为有效显示区域的公共电极的第二导电层的图形,所述基板的第二表面与所述基板的第一表面相对。
4.根据权利要求3所述的制造方法,其特征在于,所述第一导电层和第二导电层的材料为透明导电材料。
5.根据权利要求4所述的制造方法,其特征在于,所述透明导电材料为铟锡氧化物。
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