CN104022775A - FIFO protocol based digital interface circuit for SerDes technology - Google Patents
FIFO protocol based digital interface circuit for SerDes technology Download PDFInfo
- Publication number
- CN104022775A CN104022775A CN201410237883.8A CN201410237883A CN104022775A CN 104022775 A CN104022775 A CN 104022775A CN 201410237883 A CN201410237883 A CN 201410237883A CN 104022775 A CN104022775 A CN 104022775A
- Authority
- CN
- China
- Prior art keywords
- fifo
- write
- data
- clock
- serdes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention belongs to the field of a SerDes serial communication technology, and specifically relates to a FIFO protocol based digital interface circuit for a SerDes technology. The FIFO protocol based digital interface circuit is composed of two major parts, i.e., a sending end digital circuit and a receiving end digital circuit. According to the invention, classic synchronization and asynchronous FIFO and series-parallel and parallel-series conversion circuits in a digital system design are introduced to a SerDes digital-analog interface, the digital-analog interface is packaged to be a simple interface supporting a FIFO read-write protocol, the FIFO protocol based digital interface circuit is simple and feasible and facilitates scheduling. The ingenious use of the FIFO effectively solves the problem of signal integrity including clock zone crossing data transmission among chips, large transmission delay of a feedback control signal channel and the like. The series-parallel and parallel-series conversion circuits solve the problem of mismatch between a bus and a SerDes bid width, facilitate bit width expansion of the bus and enhance the adaptability of a circuit design scheme.
Description
Technical field
The invention belongs to SerDes serial communication technology field, be specifically related to a kind of towards the digital interface circuit based on FIFO agreement in SerDes technology.
Background technology
Along with the development of electronic communication, the transmission rate to data-interface and bandwidth chahnel have proposed more and more higher requirement in the industry.Speed SerDes serial line interface faster, that passage bit wide resource overhead is less becomes mainstream solution gradually.
SerDes interfacing is the abbreviation of English Serializer and Deserializer associating, and indication circuit is made up of a pair of serializer and deserializer.It is a kind of time division multiplexing (Time Division Multiplex, TDM) of extensive use and the serial communication technology of point-to-point (Point-to-Point, P2P).SerDes technology converts multi-path parallel signal to high speed serialization differential signal at transmitting terminal, by transmission medium (optical cable, copper cash or low-resistance dielectric etc.), thereby finally at receiving terminal, high-speed serial signals is merged into original low-speed parallel signal and completes the transmitting procedure of data.This time-division multiplexing (TDM) takes full advantage of the channel capacity of transmission medium, thereby has reduced transmission channel and device pin number has reduced channel resource expense, is convenient to the integrated of system.In addition, adopt the transmission of differential signal also to there is strong interference immunity, the advantage that the error rate is low.
The serializer of SerDes interface circuit and deserializer are generally formed by analog circuit Custom Design, and on sheet digital system normally eda tool automation complete, thereby at VLSI(very lagre scale integrated circuit (VLSIC)) design in, the problems of Signal Integrity such as the interface on SerDes circuit and sheet between digital system easily occurs sequential, crosstalks, bit wide is not mated, brings larger challenge to design cycle.
Summary of the invention
The object of the present invention is to provide a kind of towards the digital interface circuit based on FIFO agreement in SerDes technology, effectively to solve the problems of Signal Integrity such as chip chamber cross clock domain transfer of data, feedback control signal channel transfer postpone that large and bus and SerDes bit wide are not mated.
The present invention propose towards the digital interface circuit based on FIFO agreement in SerDes technology, as shown in Figure 1, it is made up of transmitting terminal digital circuit and receiving terminal digital circuit two large divisions its overall structure.At transmitting terminal, data write a synchronous first-in first-out buffer queue by FIFO agreement, the parallel-to-serial converter of rear one-level reads bus data and splits into some sections of serial datas from buffer queue gives SerDes serializer, data are given deserializer by differential transfer passage after bit serial, write clock, write enable, write in advance the low speed control signal such as full by buffer(buffer) through transmission channel.At receiving terminal, first the data of deserializer output write an asynchronous first-in first-out buffer queue, the serial-parallel conversion circuit of rear one-level finally writes synchronous first-in first-out buffer queue after reading and being merged into complete parallel bus data after serial data again, reads for receiving terminal user.
In the present invention, described transmitting terminal synchronization fifo and receiving terminal synchronization fifo, its structure is consistent, it is consistent with phase place with the frequency of reading clock that synchronization representation is write clock, adopt FIFO read-write protocol to carry out data communication, that is: data w_data enables w_en and is write clock w_clk the high level valid period to deposit writing, and writes when full when data, and w_full feedback signal is drawn high; Read data r_data is read clock r_clk and is taken out reading to enable the r_en high level valid period, and in the time that data run through, r_empty feedback signal is drawn high.It is consistent with phase place with the frequency of reading clock that synchronization representation is write clock.Synchronization fifo has the implementation of multiple classics.
In the present invention, described receiving terminal asynchronous FIFO, clock is write in asynchronous expression does not have correlation with frequency and the phase place of reading clock, writes clock w_clk and comes from the transmitting terminal clock through the output of buffering transmission single channel, reads the work clock that clock r_clk comes from receiving terminal.In addition, write the full signal w_full_before of writing of end and be designed to shift to an earlier date some clock cycle generations, the delay with offseting signal in buffering transmission single channel.
SerDes interface circuit is generally made up of serializer, the deserializer of analog circuit Custom Design, the problems of Signal Integrity such as the interface on itself and sheet between digital system easily occurs sequential, crosstalks, bit wide is not mated, brings larger challenge to VLSI (very large scale integrated circuit) designs.
The present invention in SerDes digital analog interface, introduced in Design of Digital System classical synchronous, asynchronous FIFO and string also, parallel-to-serial converter, digital analog interface is packaged into the interface of simple support FIFO read-write protocol, simple possible, be convenient to call.The ingenious use of FIFO, efficiently solve chip chamber cross clock domain transfer of data, feedback control signal channel transfer and postpone the problems of Signal Integrity such as large, string also, parallel-to-serial converter solved bus and SerDes bit wide mismatch problem, the bit wide of being convenient to bus is expanded, and has strengthened the adaptability of circuit design scheme.
Brief description of the drawings
Fig. 1 SerDes digital interface circuit overall structure figure.
Fig. 2 parallel-to-serial converter FSM state flow chart.
Fig. 3 serial-parallel conversion circuit FSM state flow chart.
Embodiment
At transmitting terminal, bus data writes a synchronous first-in first-out buffer queue by FIFO agreement, FIFO agreement refers to: data w_data enables w_en and write clock w_clk the high level valid period to deposit writing, and writes when full when data, and w_full feedback signal is drawn high; Read data r_data is read clock r_clk and is taken out reading to enable the r_en high level valid period, and in the time that data run through, r_empty feedback signal is drawn high.
The parallel-to-serial converter of rear one-level reads bus data and splits into some sections of serial datas and divides clock to give periodically SerDes serializer from buffer queue, data are given deserializer by differential transfer passage after bit serial, write clock, write enable, write in advance the low speed control signal such as full by buffer(buffer) through transmission channel.
At receiving terminal, first the data of deserializer output write an asynchronous first-in first-out buffer queue (FIFO), the clock w_clk that writes of asynchronous FIFO comes from the transmitting terminal clock through the output of buffering transmission single channel, reads the work clock that clock r_clk comes from receiving terminal.The full signal w_full_before of writing of end that writes of asynchronous FIFO is designed to shift to an earlier date some clock cycle generations, feeds back to transmitting terminal, the delay with offseting signal in buffering transmission single channel.Then, the serial-parallel conversion circuit of rear one-level is merged into complete parallel bus data after reading the serial data in asynchronous FIFO, finally writes synchronous first-in first-out buffer queue again, reads for receiving terminal user.
In the present invention, parallel-to-serial converter reads bus data and splits into some sections of serial datas from buffer queue gives SerDes serializer, occur because the read-write operation of data has many situation, so FSM(finite state machine core for) control, state flow chart is as shown in Figure 2.Set forth the operation that hardware configuration carries out under each state below.
(1), when IDLE state is hardware reset, the state that state machine enters, mainly realizes the reset of state.Jump to WR_FIRST state at the synchronization fifo non-NULL of previous stage and rear one-level asynchronous FIFO non-full, otherwise keep IDLE state.
(2) under WR_FIRST state, read first 8 on 32 position datawires, and write in the situation that rear one-level asynchronous FIFO is non-full, otherwise enter HD_FIRST state, if write successfully, redirect WR_SECOND state, under this state, completes reading of data.
(3) under HD_FIRST state, do not do any operation, after waiting for, the asynchronous FIFO of one-level is non-full, if non-full, enters WR_SECOND state, otherwise, keep HD_FIRST state.
(4) under WR_SECOND state, read 23 ~ 16 on 32 position datawires, and write in the situation that rear one-level asynchronous FIFO is non-full, otherwise enter HD_SECOND state, if write successfully, redirect WR_THIRD state.
(5) under HD_SECOND state, do not do any operation, after waiting for, the asynchronous FIFO of one-level is non-full, if non-full, enters WR_THIRD state, otherwise, keep HD_SECOND state.
(6) under WR_THIRD state, read 15 ~ 8 on 32 position datawires, and write in the situation that rear one-level asynchronous FIFO is non-full, otherwise enter HD_THIRD state, if write successfully, redirect WR_FORTH state.
(7) under HD_THIRD state, do not do any operation, after waiting for, the asynchronous FIFO of one-level is non-full, if non-full, enters WR_FORTH state, otherwise, keep HD_THIRD state.
(8) under WR_FORTH state, read last 8 on 32 position datawires, and write the synchronization fifo non-NULL of and previous stage non-full at rear one-level asynchronous FIFO, otherwise enter HD_FORTH state, if write successfully, redirect WR_FIRST state.
(9) under HD_FORTH state, do not do any operation, after waiting for, the synchronization fifo non-NULL of the non-full and previous stage of one-level asynchronous FIFO, if met, enters WR_FIRST state, otherwise, keep HD_FORTH state.
In the present invention, serial-parallel conversion circuit finally writes synchronous first-in first-out buffer queue after reading and being merged into complete parallel bus data after asynchronous FIFO data again, because having many situations, the read-write operation of data occurs, so FSM(finite state machine for core) to control, state flow chart is as shown in Figure 3.Set forth the operation that hardware configuration carries out under each state below.
(1), when IDLE state is hardware reset, the state that state machine enters, mainly realizes the reset of state.Jump to RD_FIRST state at the asynchronous FIFO non-NULL of previous stage and rear one-level synchronization fifo non-full, otherwise keep IDLE state.
(2) 8 bit data on input data line under RD_FIRST state, and the in the situation that of previous stage asynchronous FIFO non-NULL reading out data, otherwise enter HD_FIRST state, if read successfully, redirect RD_SECOND state.
(3) under HD_FIRST state, do not do any operation, wait for that previous stage asynchronous FIFO is non-NULL, if non-NULL enters RD_SECOND state, otherwise, keep HD_FIRST state.
(4) 8 bit data on input data line under RD_SECOND state, and the in the situation that of previous stage asynchronous FIFO non-NULL reading out data, otherwise enter HD_SECOND state, if read successfully, redirect RD_THIRD state.
(5) under HD_SECOND state, do not do any operation, wait for that previous stage asynchronous FIFO is non-NULL, if non-NULL enters RD_THIRD state, otherwise, keep HD_SECOND state.
(6) 8 bit data on input data line under RD_THIRD state, and in the case of the asynchronous FIFO non-NULL of previous stage and rear one-level synchronization fifo non-full reading out data, otherwise enter HD_THIRD state, if satisfied condition, redirect RD_FORTH state.
(7) under HD_THIRD state, do not do any operation, wait for that the asynchronous FIFO non-NULL of previous stage and rear one-level synchronization fifo are non-full, if satisfied condition, enter RD_FORTH state, otherwise, keep HD_THIRD state.
(8) 8 bit data on input data line under RD_FORTH state, and the in the situation that of previous stage asynchronous FIFO non-NULL reading out data, otherwise enter HD_FORTH state, if read successfully, redirect RD_FIRST state, under this state, completes writing of data.
(9) under HD_FORTH state, do not do any operation, wait for that previous stage asynchronous FIFO is non-NULL, if non-NULL enters RD_FIRST state, otherwise, keep HD_FORTH state.
SerDes digital interface circuit of the present invention, its course of work is as follows:
(1), at transmitting terminal, data write a synchronous first-in first-out buffer queue by FIFO agreement.
(2) after, the parallel-to-serial converter of one-level reads bus data and splits into some sections of serial datas and gives SerDes serializer from buffer queue.
(3) data are given deserializer by differential transfer passage after bit serial, write clock, write enable, write in advance the low speed control signal such as full by buffer(buffer) through transmission channel.
(4), at receiving terminal, first the data of deserializer output write an asynchronous first-in first-out buffer queue.
(5) after the serial-parallel conversion circuit of one-level reads serial data from asynchronous FIFO after, be merged into complete parallel bus data.
(6) bus data merging finally writes the synchronous first-in first-out buffer queue of receiving terminal, reads for receiving terminal user.
Claims (5)
1. towards the digital interface circuit based on FIFO agreement in SerDes technology, it is characterized in that being formed by transmitting terminal digital circuit and receiving terminal digital circuit two large divisions; At transmitting terminal, data write a synchronous first-in first-out buffer queue by FIFO agreement, the parallel-to-serial converter of rear one-level reads bus data and splits into some sections of serial datas from buffer queue gives SerDes serializer, data are given deserializer by differential transfer passage after bit serial, write clock, write and enable, write in advance the low speed control signal such as full and pass through transmission channel by buffer; At receiving terminal, first the data of deserializer output write an asynchronous first-in first-out buffer queue, the serial-parallel conversion circuit of rear one-level finally writes synchronous first-in first-out buffer queue after reading and being merged into complete parallel bus data after serial data again, reads for receiving terminal user.
2. digital interface circuit according to claim 1, it is characterized in that: described transmitting terminal synchronization fifo is consistent with receiving terminal synchronization fifo structure, it is consistent with phase place with the frequency of reading clock that synchronization representation is write clock, adopts FIFO read-write protocol to carry out data communication.
3. digital interface circuit according to claim 2, is characterized in that: described receiving terminal asynchronous FIFO, and write clock w_clk and come from the transmitting terminal clock through the output of buffering transmission single channel, read the work clock that clock r_clk comes from receiving terminal; Write the full signal w_full_before of writing of end and shift to an earlier date some clock cycle generations, the delay with offseting signal in buffering transmission single channel.
4. digital interface circuit according to claim 3, is characterized in that: described parallel-to-serial converter reads bus data and splits into some sections of serial datas from buffer queue gives SerDes serializer, and its core is a finite state machine.
5. digital interface circuit according to claim 4, it is characterized in that: described serial-parallel conversion circuit finally writes synchronous first-in first-out buffer queue after reading and being merged into complete parallel bus data after asynchronous FIFO data again, and its core is a finite state machine.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410237883.8A CN104022775A (en) | 2014-06-02 | 2014-06-02 | FIFO protocol based digital interface circuit for SerDes technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410237883.8A CN104022775A (en) | 2014-06-02 | 2014-06-02 | FIFO protocol based digital interface circuit for SerDes technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104022775A true CN104022775A (en) | 2014-09-03 |
Family
ID=51439380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410237883.8A Pending CN104022775A (en) | 2014-06-02 | 2014-06-02 | FIFO protocol based digital interface circuit for SerDes technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104022775A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105680895A (en) * | 2014-12-05 | 2016-06-15 | 吉林克斯公司 | Delay control for transmitter/receiver buffer |
| CN105933406A (en) * | 2016-04-20 | 2016-09-07 | 烽火通信科技股份有限公司 | Equipment processing method and system of Ethernet packet mutual conversion of XGE and GE |
| CN106201945A (en) * | 2016-06-28 | 2016-12-07 | 醴陵恒茂电子科技有限公司 | Bit width conversion device |
| CN107077445A (en) * | 2014-09-15 | 2017-08-18 | 赛灵思公司 | The skew correction of the channel-to-channel of transmitter |
| CN108228516A (en) * | 2016-12-22 | 2018-06-29 | 南京洛菲特数码科技有限公司 | A kind of image plate grade transmission universal serial bus method of external splicer hybrid matrix |
| CN108665922A (en) * | 2018-04-24 | 2018-10-16 | 电子科技大学 | A kind of variable bi-directional digital related method thereof applied to radar simulation |
| CN108681516A (en) * | 2018-03-30 | 2018-10-19 | 东莞市爱协生智能科技有限公司 | The method for promoting MIPI protocol layer transmission speeds, the MIPI interface and computer readable storage medium quickly transmitted |
| WO2020010543A1 (en) * | 2018-07-11 | 2020-01-16 | 华为技术有限公司 | Signal generation device, method, and system |
| CN113572486A (en) * | 2021-06-29 | 2021-10-29 | 中国人民解放军战略支援部队信息工程大学 | Transmitter with low-speed SerDes interface, receiver with low-speed SerDes interface and circuit design method of transmitter |
| CN114967839A (en) * | 2022-08-01 | 2022-08-30 | 井芯微电子技术(天津)有限公司 | Serial cascade system and method based on multiple clocks, and parallel cascade system and method |
| CN115664427A (en) * | 2022-12-09 | 2023-01-31 | 井芯微电子技术(天津)有限公司 | Communication system and method based on serial and deserialized SerDes models |
| CN116886099A (en) * | 2023-09-06 | 2023-10-13 | 成都博宇利华科技有限公司 | Analog-to-digital conversion data transmission method with variable sampling rate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777979B1 (en) * | 2001-12-14 | 2004-08-17 | Lattice Semiconductor Corporation | FIFO memory architecture |
| US7321593B1 (en) * | 2003-07-17 | 2008-01-22 | Marvell International Ltd. | Fibre channel SERDES with elastic transmitter FIFO |
| CN101299647A (en) * | 2008-06-27 | 2008-11-05 | 中兴通讯股份有限公司 | Apparatus and method for implementing nondestructive switch of SDH service |
-
2014
- 2014-06-02 CN CN201410237883.8A patent/CN104022775A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777979B1 (en) * | 2001-12-14 | 2004-08-17 | Lattice Semiconductor Corporation | FIFO memory architecture |
| US7321593B1 (en) * | 2003-07-17 | 2008-01-22 | Marvell International Ltd. | Fibre channel SERDES with elastic transmitter FIFO |
| CN101299647A (en) * | 2008-06-27 | 2008-11-05 | 中兴通讯股份有限公司 | Apparatus and method for implementing nondestructive switch of SDH service |
Non-Patent Citations (1)
| Title |
|---|
| ABHIJIT ATHAVALE AND CARL CHRISTENSEN: "《High-Speed Serial I/O Made Simple – A Designers’ Guide, with FPGA Applications》", 30 April 2005 * |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107077445A (en) * | 2014-09-15 | 2017-08-18 | 赛灵思公司 | The skew correction of the channel-to-channel of transmitter |
| CN107077445B (en) * | 2014-09-15 | 2020-11-24 | 赛灵思公司 | Lane-to-lane deskew for transmitters |
| CN105680895B (en) * | 2014-12-05 | 2019-12-10 | 吉林克斯公司 | Delay control in a buffer of a transmitter/receiver |
| CN105680895A (en) * | 2014-12-05 | 2016-06-15 | 吉林克斯公司 | Delay control for transmitter/receiver buffer |
| CN105933406A (en) * | 2016-04-20 | 2016-09-07 | 烽火通信科技股份有限公司 | Equipment processing method and system of Ethernet packet mutual conversion of XGE and GE |
| CN106201945A (en) * | 2016-06-28 | 2016-12-07 | 醴陵恒茂电子科技有限公司 | Bit width conversion device |
| CN108228516A (en) * | 2016-12-22 | 2018-06-29 | 南京洛菲特数码科技有限公司 | A kind of image plate grade transmission universal serial bus method of external splicer hybrid matrix |
| CN108681516B (en) * | 2018-03-30 | 2021-05-18 | 深圳市爱协生科技有限公司 | Method for improving transmission speed of MIPI protocol layer, MIPI interface for quick transmission and computer readable storage medium |
| CN108681516A (en) * | 2018-03-30 | 2018-10-19 | 东莞市爱协生智能科技有限公司 | The method for promoting MIPI protocol layer transmission speeds, the MIPI interface and computer readable storage medium quickly transmitted |
| CN108665922A (en) * | 2018-04-24 | 2018-10-16 | 电子科技大学 | A kind of variable bi-directional digital related method thereof applied to radar simulation |
| CN108665922B (en) * | 2018-04-24 | 2021-09-24 | 电子科技大学 | Variable bidirectional digital delay method applied to radar simulation |
| CN112368956A (en) * | 2018-07-11 | 2021-02-12 | 华为技术有限公司 | Apparatus, method and system for generating a signal |
| WO2020010543A1 (en) * | 2018-07-11 | 2020-01-16 | 华为技术有限公司 | Signal generation device, method, and system |
| CN112368956B (en) * | 2018-07-11 | 2022-07-22 | 华为技术有限公司 | Apparatus, method and system for generating a signal |
| CN113572486A (en) * | 2021-06-29 | 2021-10-29 | 中国人民解放军战略支援部队信息工程大学 | Transmitter with low-speed SerDes interface, receiver with low-speed SerDes interface and circuit design method of transmitter |
| CN113572486B (en) * | 2021-06-29 | 2022-06-24 | 中国人民解放军战略支援部队信息工程大学 | Transmitter with low-speed SerDes interface, receiver with low-speed SerDes interface and circuit design method of transmitter |
| CN114967839A (en) * | 2022-08-01 | 2022-08-30 | 井芯微电子技术(天津)有限公司 | Serial cascade system and method based on multiple clocks, and parallel cascade system and method |
| CN114967839B (en) * | 2022-08-01 | 2022-09-30 | 井芯微电子技术(天津)有限公司 | Serial cascade system and method based on multiple clocks, and parallel cascade system and method |
| CN115664427A (en) * | 2022-12-09 | 2023-01-31 | 井芯微电子技术(天津)有限公司 | Communication system and method based on serial and deserialized SerDes models |
| CN116886099A (en) * | 2023-09-06 | 2023-10-13 | 成都博宇利华科技有限公司 | Analog-to-digital conversion data transmission method with variable sampling rate |
| CN116886099B (en) * | 2023-09-06 | 2023-11-21 | 成都博宇利华科技有限公司 | Analog-to-digital conversion data transmission method with variable sampling rate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104022775A (en) | FIFO protocol based digital interface circuit for SerDes technology | |
| US8352774B2 (en) | Inter-clock domain data transfer FIFO circuit | |
| EP0826179B1 (en) | Source synchronous clocked data link | |
| JP5027241B2 (en) | High-speed serializer / deserializer transmission architecture | |
| US8867573B2 (en) | Transferring data between asynchronous clock domains | |
| JP2005518018A5 (en) | ||
| CN101692218A (en) | High-speed data transmission method | |
| CN109918332B (en) | SPI slave unit and SPI device | |
| CN102340316A (en) | FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer | |
| JP2004072511A (en) | Data transfer device | |
| CN104915303A (en) | High-speed digital I/O system based on PXIe bus | |
| CN108121679A (en) | A kind of embedded SoC system bus and its protocol conversion bridge-set | |
| CN103592594B (en) | Circuit test system and circuit testing method | |
| CN105786741B (en) | SOC high-speed low-power-consumption bus and conversion method | |
| US20240111706A1 (en) | Frame alignment recovery for a high-speed signaling interconnect | |
| US8675798B1 (en) | Systems, circuits, and methods for phase inversion | |
| US8510485B2 (en) | Low power digital interface | |
| CN111313869B (en) | Clock switching circuit of gigabit Ethernet transceiver | |
| CN204143430U (en) | Elasticity push-up storage | |
| CN102723943B (en) | A kind of CPLD and realize signal level conversion method | |
| CN219227609U (en) | JESD204B data transmission system based on optical fiber medium | |
| Verbitskyv et al. | A four-stage mesochronous synchronizer with back-pressure and buffering for short and long range communications | |
| CN113168205B (en) | Apparatus for transaction-based transmit clock gating for low power designs | |
| JP4463295B2 (en) | Semiconductor device | |
| WO2024086641A1 (en) | Data lane deskew and rate adaptation in a package containing multiple circuit dies |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140903 |