CN111858436B - Switching circuit for high-speed bus read-write low-speed bus and data read-write equipment - Google Patents
Switching circuit for high-speed bus read-write low-speed bus and data read-write equipment Download PDFInfo
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Abstract
The invention provides a switching circuit for reading and writing a low-speed bus by a high-speed bus and data reading and writing equipment, wherein the switching circuit comprises a signal input module, a signal processing module and a signal output module which are sequentially connected; the signal input module is used for acquiring a high-speed bus input signal and inputting the high-speed bus input signal to the signal processing module; the signal processing module is used for outputting a low-speed bus longitudinal signal through the signal output module according to the high-speed bus input signal so as to read and write data of the low-speed bus. Therefore, the invention completes the function of reading and writing data on the low-speed bus by the high-speed bus through the mutual matching of the circuit time sequences in the signal processing module, and solves the problem that the prior art has no standard switching circuit for reading and writing the low-speed bus by the high-speed bus.
Description
Technical Field
The invention relates to the technical field of bus design, in particular to a switching circuit for reading and writing a low-speed bus by a high-speed bus and data reading and writing equipment.
Background
In the data transmission of the bus, because the data transmission speeds of the high-speed bus and the low-speed bus are different and the transmission protocols are different, communication obstacles are caused between the high-speed bus and the low-speed bus during communication, so that the data in the low-speed bus cannot be well read and written by the high-speed bus, and great inconvenience is brought to the data transmission.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a switching circuit for reading and writing data on a low-speed bus via a high-speed bus and a data reading and writing device, so as to alleviate the above problems and achieve the function of reading and writing data on the low-speed bus via the high-speed bus.
In a first aspect, an embodiment of the present invention provides a switching circuit for reading and writing a low-speed bus by a high-speed bus, including a signal input module, a signal processing module, and a signal output module, which are connected in sequence; wherein, signal processing module includes: the device comprises a read signal delay circuit, an address buffer register, a write data buffer register, a write signal control circuit, a write signal synchronous circuit, a write signal rising edge detection circuit, a write back response signal synchronous circuit, a write back response signal falling edge detection circuit, an asynchronous reset synchronous circuit and a bus state register; the read signal delay circuit, the address buffer register and the write data buffer register are directly connected with the signal input module and the signal output module; between the signal input module and the signal output module, a write signal control circuit, a write signal synchronous circuit, a write signal rising edge detection circuit, a write back response signal synchronous circuit, a write back response signal falling edge detection circuit and an asynchronous reset synchronous circuit are connected in sequence, and the output end of the asynchronous reset synchronous circuit is connected with the write signal synchronous circuit, wherein the write signal control circuit, the write back response signal synchronous circuit and the write back response signal falling edge detection circuit are all connected with the signal input module; the write signal control circuit, the asynchronous reset synchronous circuit and the write-back response signal falling edge detection circuit are also connected with the bus state register; the bus state register is also connected with the signal input module; the signal input module is used for acquiring a high-speed bus input signal and inputting the high-speed bus input signal to the signal processing module; the signal processing module is used for outputting a low-speed bus longitudinal signal through the signal output module according to the high-speed bus input signal so as to read and write data of the low-speed bus.
With reference to the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect, where the signal input module includes a first input interface, a second input interface, a third input interface, a fourth input interface, a fifth input interface, and a low-speed bus clock signal interface; the first input interface and the fifth input interface are connected with the input end of the read signal delay circuit, the second input interface and the fifth input interface are connected with the input end of the address buffer register, the third input interface and the fifth input interface are connected with the write data buffer register, and the fourth input interface and the fifth input interface are respectively connected with the write signal control circuit and the bus state register; the low-speed bus clock signal interface is respectively connected with the write signal synchronous circuit, the write signal rising edge detection circuit and the asynchronous reset synchronous circuit.
With reference to the first possible implementation manner of the first aspect, an embodiment of the present invention provides a second possible implementation manner of the first aspect, where a signal input by the first input interface is a high-speed bus read valid signal; the signal input by the second input interface is a high-speed bus address signal; the signal input by the third input interface is a high-speed bus write data signal; the signal input by the fourth input interface is a high-speed bus write valid signal; the signal input by the fifth input interface is a high-speed bus clock signal; the signal input by the low-speed bus clock signal interface is a low-speed bus clock signal.
With reference to the first aspect, an embodiment of the present invention provides a third possible implementation manner of the first aspect, where the signal output module includes a first output interface, a second output interface, a third output interface, and a fourth output interface; the first output interface is connected with the output end of the read signal delay circuit; the second output interface is connected with the output end of the address cache register; the third output interface is connected with the output end of the write data cache register; the fourth output interface is connected with the output end of the write signal rising edge detection circuit.
With reference to the third possible implementation manner of the first aspect, an embodiment of the present invention provides a fourth possible implementation manner of the first aspect, where the signal output by the first output interface is a low-speed bus read valid signal; the signal output by the second output interface is a low-speed bus address signal; the signal output by the third output interface is a low-speed bus write data signal; the signal output by the fourth output interface is a low-speed bus write valid signal.
With reference to the first aspect, an embodiment of the present invention provides a fifth possible implementation manner of the first aspect, where the signal input module is disposed at a high-speed bus end, and the signal output module is disposed at a low-speed bus end; the signal input module further comprises a first port, and the signal output module further comprises a second port; the second port is connected with the first port and used for transmitting the bus reading data signals from the low-speed bus end to the high-speed bus end.
With reference to the second possible implementation manner of the first aspect, an embodiment of the present invention provides a sixth possible implementation manner of the first aspect, where the circuit that operates with a high-speed bus clock signal as a driving clock includes: the write-back circuit comprises a read signal delay circuit, an address buffer register, a write data buffer register, a write signal control circuit, a write-back response signal synchronization circuit, a write-back response signal falling edge detection circuit and a bus state register.
With reference to the second possible implementation manner of the first aspect, an embodiment of the present invention provides a seventh possible implementation manner of the first aspect, where the circuit that operates with the low-speed bus clock signal as the driving clock includes: a write signal synchronization circuit, a write signal rising edge detection circuit, and an asynchronous reset synchronization circuit.
With reference to the second possible implementation manner of the first aspect, an embodiment of the present invention provides an eighth possible implementation manner of the first aspect, where the through circuit further includes a first signal generating unit connected to the first input interface, and configured to generate a high-speed bus read valid signal; the second signal generating unit is connected with the fourth input interface and used for generating a high-speed bus write effective signal; the first signal generating unit is a unit formed by logical negation and logical AND, and the second signal generating unit is a unit formed by logical AND.
In a second aspect, an embodiment of the present invention further provides a data reading and writing device, where the data reading and writing device is configured with the switching circuit for reading and writing the low-speed bus by the high-speed bus in the first aspect.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a switching circuit for reading and writing a low-speed bus by a high-speed bus and data reading and writing equipment, wherein the switching circuit comprises a signal input module, a signal processing module and a signal output module which are sequentially connected; the signal input module is used for acquiring a high-speed bus input signal and inputting the high-speed bus input signal to the signal processing module; the signal processing module is used for outputting a low-speed bus longitudinal signal through the signal output module according to the high-speed bus input signal so as to read and write data of the low-speed bus. Therefore, the invention completes the function of reading and writing data on the low-speed bus by the high-speed bus through the mutual matching of the circuit time sequences in the signal processing module, and solves the problem that the prior art has no standard switching circuit for reading and writing the low-speed bus by the high-speed bus.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of a switching circuit for reading from and writing to a low-speed bus by a high-speed bus according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another embodiment of a switching circuit for reading from and writing to a low-speed bus via a high-speed bus;
FIG. 3 is a schematic diagram illustrating a read timing of a high speed bus according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a write timing of a high-speed bus according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a read sequence of a low-speed bus according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating a write timing of a low speed bus according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating a read operation from a high speed bus to a low speed bus according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating a write operation from a high speed bus to a low speed bus according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating a circuit for obtaining a high-speed bus read valid signal according to an embodiment of the present invention;
FIG. 10 is a diagram illustrating a circuit for obtaining a high-speed bus write valid signal according to an embodiment of the present invention.
Icon:
1-a signal input module; 11-a first input interface; 12-a second input interface; 13-a third input interface; 14-a fourth input interface; 15-a fifth input interface; 16-low speed bus clock signal interface; 2-a signal processing module; 201-read signal delay circuit; 202-address cache register; 203-write data cache register; 204-write signal control circuit; 205-write signal synchronizing circuit; 206-write signal rising edge detection circuit; 207-write back response signal synchronizing circuit; 208-write back responsive signal falling edge detection circuitry; 209-asynchronous reset synchronous circuit; 210-bus status register; 3-a signal output module; 31-a first output interface; 32-a second output interface; 33-a third output interface; 34-fourth output interface.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Aiming at the problem that a standard switching circuit for reading and writing the low-speed bus by the high-speed bus does not exist at present, the embodiment of the invention provides the switching circuit for reading and writing the low-speed bus by the high-speed bus and the data reading and writing equipment.
To facilitate understanding of the present embodiment, first, a detailed description is given below of a switching circuit for reading from and writing to a low-speed bus through a high-speed bus according to an embodiment of the present invention.
The first embodiment is as follows:
the embodiment of the invention provides a switching circuit for reading and writing a low-speed bus by a high-speed bus, which comprises a signal input module 1, a signal processing module 2 and a signal output module 3 which are connected in sequence as shown in figure 1; wherein, the signal processing module 2 includes: a read signal delay circuit 201, an address buffer register 202, a write data buffer register 203, a write signal control circuit 204, a write signal synchronization circuit 205, a write signal rising edge detection circuit 206, a write back response signal synchronization circuit 207, a write back response signal falling edge detection circuit 208, an asynchronous reset synchronization circuit 209, and a bus state register 210.
The read signal delay circuit 201, the address buffer register 202 and the write data buffer register 203 are directly connected with the signal input module 1 and the signal output module 3; between the signal input module 1 and the signal output module 3, a write signal control circuit 204, a write signal synchronization circuit 205, a write signal rising edge detection circuit 206, a write back response signal synchronization circuit 207, a write back response signal falling edge detection circuit 208, and an asynchronous reset synchronization circuit 209 are connected in sequence, and an output end of the asynchronous reset synchronization circuit 209 is connected with the write signal synchronization circuit 205, wherein the write signal control circuit 204, the write back response signal synchronization circuit 207, and the write back response signal falling edge detection circuit 208 are all connected with the signal input module 1; the write signal control circuit 204, the asynchronous reset synchronous circuit 209 and the write-back response signal falling edge detection circuit 208 are also all connected with a bus state register 210; the bus state register 210 is also connected to the signal input module 1.
Specifically, the signal input module 1 is configured to obtain a high-speed bus input signal, and input the high-speed bus input signal to the signal processing module 2; at this time, the signal processing module 2 is configured to output a low-speed bus longitudinal signal through the signal output module 3 according to the high-speed bus input signal, so as to implement reading and writing of data of the low-speed bus. In practical application, the function of reading and writing data on the low-speed bus by the high-speed bus is realized by configuring a conventional high-speed bus reading and writing time sequence and a self-defined low-speed bus reading and writing time sequence for each circuit in the signal processing module 2.
The embodiment of the invention provides a switching circuit for reading and writing a low-speed bus by a high-speed bus, wherein the switching circuit comprises a signal input module, a signal processing module and a signal output module which are sequentially connected; the signal input module is used for acquiring a high-speed bus input signal and inputting the high-speed bus input signal to the signal processing module; the signal processing module is used for outputting a low-speed bus longitudinal signal through the signal output module according to the high-speed bus input signal so as to read and write data of the low-speed bus. Therefore, the invention completes the function of reading and writing data on the low-speed bus by the high-speed bus through the mutual matching of the circuit time sequences in the signal processing module, and solves the problem that the prior art has no standard switching circuit for reading and writing the low-speed bus by the high-speed bus.
In one possible embodiment, as shown in fig. 2, the signal input module 1 includes a first input interface 11, a second input interface 12, a third input interface 13, a fourth input interface 14, a fifth input interface 15, and a low-speed bus clock signal interface 16; the first input interface 11 and the fifth input interface 15 are connected with the input end of the read signal delay circuit 201, the second input interface 12 and the fifth input interface 15 are connected with the input end of the address buffer register 202, the third input interface 13 and the fifth input interface 15 are connected with the write data buffer register 203, and the fourth input interface 14 and the fifth input interface 15 are respectively connected with the write signal control circuit 204 and the bus state register 210; the low-speed bus clock signal interface 16 is connected to a write signal synchronization circuit 205, a write signal rising edge detection circuit 206, and an asynchronous reset synchronization circuit 209, respectively.
The signal input by the first input interface 11 is a high-speed bus read valid signal; the signal input by the second input interface 12 is a high-speed bus address signal; the signal input by the third input interface 13 is a high-speed bus write data signal; the signal input by the fourth input interface 14 is a high-speed bus write valid signal; the signal input by the fifth input interface 15 is a high-speed bus clock signal; the signal input by the low-speed bus clock signal interface 16 is a low-speed bus clock signal.
In another possible embodiment, as shown in fig. 2, the signal output module 3 comprises a first output interface 31, a second output interface 32, a third output interface 33 and a fourth output interface 34; wherein, the first output interface 31 is connected with the output end of the read signal delay circuit 201; the second output interface 32 is connected to the output end of the address cache register 202; the third output interface 33 is connected with the output end of the write data cache register 203; the fourth output interface 34 is connected to an output of the write signal rising edge detection circuit 206.
Wherein, the signal output by the first output interface 31 is a low-speed bus read valid signal; the signal output by the second output interface 32 is a low-speed bus address signal; the signal output by the third output interface 33 is a low-speed bus write data signal; the signal output by the fourth output interface 34 is a low speed bus write valid signal.
In practical applications, as shown in fig. 2, the circuit operating with a high-speed bus clock signal as a driving clock includes: a read signal delay circuit 201, an address buffer register 202, a write data buffer register 203, a write signal control circuit 204, a write back response signal synchronizing circuit 207, a write back response signal falling edge detection circuit 208, and a bus state register 210. The circuit which takes the low-speed bus clock signal as the driving clock comprises: a write signal synchronization circuit 205, a write signal rising edge detection circuit 206, and an asynchronous reset synchronization circuit 209.
Further, as shown in fig. 2, in addition to the above signals, the relay circuit includes a signal 1, a signal 2, a signal 3, a signal 4, a signal 5, and a signal 6; the signal 1 is a high-speed bus write valid cache signal, the signal 2 is a high-speed bus write valid synchronization signal, the signal 3 is a low-speed bus clock signal, the signal 4 is a low-speed bus write response signal, the signal 5 is a low-speed bus write synchronous reset signal, and the signal 6 is a bus read data signal.
In another possible embodiment, the signal input module 1 is arranged at the high-speed bus end, and the signal output module 3 is arranged at the low-speed bus end; the signal input module 1 further comprises a first port (not shown), the signal output module 3 further comprises a second port (not shown); the second port is connected to the first port and is used for transmitting a bus read data signal, i.e., a signal 6, from the low speed bus to the high speed bus.
In another possible embodiment, the read operation and the write operation of the high-speed bus are both composed of two cycles, the first cycle is called a control cycle, and the second cycle is called a data cycle; wherein, the control cycle and the data cycle can be pipelined, that is, the data cycle of the 1 st operation can be simultaneously used as the control cycle of the 2 nd operation. In practical application, for read operation, the high-speed bus can obtain data corresponding to a bus address on the low-speed bus in a data cycle by the switching circuit; for the write operation, the high-speed bus needs to read the bus status register 210 first, the bus status register 210 includes two states of a low-speed bus busy state and a low-speed bus idle state, when the low-speed bus is idle, the high-speed bus can write data on the low-speed bus, in the write process, the bus status register 210 can display the state of the low-speed bus busy, and when the state of the bus status register 210 changes to the low-speed bus idle state, the write operation is completed, so that the switching circuit can realize the function of reading and writing data on the low-speed bus by the high-speed bus.
This is illustrated here for ease of understanding. As shown in fig. 3, a schematic diagram of the read timing of the high speed bus is shown, where hren is a high speed bus read valid signal, high level indicates valid, haddr is a high speed bus address signal, hrdata is a high speed bus read data signal, hclk is a high speed bus clock signal, intervals marked with a and b are control cycles, and intervals marked with b and c are data cycles. As shown in fig. 4, the write timing diagram of the high-speed bus is shown, where hwen is a high-speed bus write valid signal, high indicates valid, haddr is a high-speed bus address signal, hwdata is a high-speed bus write data signal, hclk is a high-speed bus clock signal, the intervals marked with a and b are control periods, and the intervals marked with b and c are data periods. Fig. 5 is a schematic diagram of a read timing sequence of the low speed bus, where lren is a low speed bus read valid signal, high level indicates valid, laddr is a low speed bus address signal, lrdata is a low speed bus read data signal, lclk is a low speed bus clock signal, and the interval marked by a and b is a read operation cycle. As shown in fig. 6, it is a schematic diagram of the write timing sequence of the low speed bus, where lwen is a low speed bus write valid signal, high level indicates valid, laddr is a low speed bus address signal, lwdata is a low speed bus write data signal, lclk is a low speed bus clock signal, and the intervals marked by a and b are write operation cycles.
The process of the read operation of the high-speed bus to the low-speed bus is shown in fig. 7, where s1 represents a high-speed bus read valid signal, i.e., hren, s2 represents a high-speed bus address signal, i.e., haddr, s5 represents a high-speed bus clock signal, i.e., hclk, s6 represents a low-speed bus read valid signal, i.e., lren, s7 represents a low-speed bus address signal, i.e., laddr, s16 represents a bus read data signal, the intervals marked with a and b are control cycles, and the intervals marked with b and c are data cycles. The specific read operation process of the high-speed bus is as follows: in a control period, the read signal delay circuit delays the high-speed bus read effective signal by one high-speed bus clock period, and the delayed signal is output as a low-speed bus read effective signal; in a control period, the address cache register samples and caches a high-speed bus address signal at the rising edge of a high-speed bus clock, and the cached signal is output as a low-speed bus address signal; in the data period, the high-speed bus reads the data reading signal to obtain the data reading, so that the high-speed bus reads the data of the low-speed bus.
The process of the write operation of the high-speed bus to the low-speed bus is shown in fig. 8, where s2 represents a high-speed bus address signal, i.e., haddr, s3 represents a high-speed bus write data signal, i.e., hwata, s4 represents a high-speed bus write valid signal, i.e., hwen, s5 represents a high-speed bus clock signal, i.e., hclk, s7 represents a low-speed bus address signal, i.e., laddr, s8 represents a low-speed bus write data signal, s9 represents a low-speed bus write valid signal, i.e., lwen, s10 represents a low-speed bus clock signal, i.e., lclk, s11 represents a high-speed bus write valid cache signal, s12 represents a high-speed bus write valid synchronization signal, s13 represents a low-speed bus write synchronization signal, s14 represents a low-speed bus write-back response signal, s15 represents a low-speed bus write synchronization reset, low represents a reset, s17 represents a state of the bus state register, where high level represents a low-speed bus idle.
The specific process of the write operation of the high-speed bus to the low-speed bus is as follows:
(1) in the control period: the address cache register samples and caches a high-speed bus address signal at the rising edge of a high-speed bus clock, and the cached signal is output as a low-speed bus address signal;
(2) in a data period: the write data cache register samples and caches a high-speed bus write data signal at the rising edge of a high-speed bus clock, and the cached signal is output as a low-speed bus write data signal;
(3) the write signal control circuit samples the high-speed bus write effective signal at the rising edge of the high-speed bus clock in the high-speed bus control period, if the effective high-speed bus write effective signal is sampled, the output high-speed bus write effective cache signal is set to be effective and kept until the low-speed bus write-back response signal is effective, and then the high-speed bus write effective cache signal is set to be invalid;
(4) the write signal synchronization circuit synchronously samples an input high-speed bus write effective cache signal by using a low-speed bus clock signal and then provides a high-speed bus write effective synchronization signal, the low-speed bus write synchronous reset signal can asynchronously reset the circuit, and the high-speed bus write effective synchronization signal is at a low level after the reset;
(5) the write signal rising edge detection circuit detects a high-speed bus write effective synchronous signal, and when the signal generates rising edge jumping, a low-speed bus write effective signal with a wide low-speed bus clock period is generated;
(6) the write-back response signal synchronization circuit synchronously samples the input low-speed bus write effective signal by using a high-speed bus clock signal and then provides a low-speed bus write synchronization signal;
(7) the write response signal falling edge detection circuit detects a low-speed bus write synchronization signal, and when the signal generates falling edge jumping, a low-speed bus write-back response signal with a high-speed bus clock period width is generated;
(8) the asynchronous reset synchronous circuit takes a low-speed bus write-back response signal as asynchronous reset, the low-speed bus write-synchronous reset signal output by the asynchronous reset synchronous circuit is immediately valid once the low-speed bus write-back response signal is valid, and when the low-speed bus write-back response signal is invalid, the asynchronous reset synchronous circuit uses a low-speed bus clock signal to sample a fixed level mode to set the output low-speed bus write-synchronous reset signal as invalid, so that the asynchronous reset synchronous release function is completed;
(9) the bus state register is set to be in a state of low-speed bus busy by a write effective signal in a high-speed bus control period, and is kept in the state until the write-back response signal of the low-speed bus is effective, and then the state of the bus state register is changed to be in the state of low-speed bus idle.
According to the steps, the write operation of the high-speed bus to the low-speed bus is realized, so that the switching circuit provided by the embodiment of the invention can realize the function of reading and writing data on the low-speed bus by the high-speed bus, and the problem that the switching circuit for reading and writing the low-speed bus by the high-speed bus is not standardized in the prior art is solved.
In another possible embodiment, the present application provides a switching circuit further including a first signal generating unit connected to the first input interface, for generating a high-speed bus read valid signal; the second signal generating unit is connected with the fourth input interface and used for generating a high-speed bus write effective signal; the first signal generating unit is a unit formed by logical negation and logical AND, and the second signal generating unit is a unit formed by logical AND.
Specifically, for the common AHB (Advanced High Performance Bus) High-speed Bus protocol, the above-mentioned High-speed Bus read valid signal can be generated by a circuit as shown in fig. 9, wherein HSELx is the AHB Bus definition HSELx, i.e. the operation address valid signal of the module on the low-speed Bus, which is generally composed of HSEL and HADDR on the AHB Bus, and is High when HSEL is High and the address range of the HADDR is within the address range of the module (for the present invention, the address range of the module on the low-speed Bus); the HWRITE is the HWRITE defined by the AHB bus, and Hren is a high-speed bus read valid signal, so that the high-speed bus read valid signal is obtained through a hostile signal generation unit consisting of logical negation and logical AND. In addition, as shown in fig. 10, a high-speed bus write valid signal can also be obtained by the second signal generating unit that generates a logical and. Where Hwen is the high speed bus write valid signal. The high-speed bus address signal can be directly connected with the HADDR defined by the AHB bus; the high-speed bus write data signal may be directly connected to the HWDATA defined by the AHB bus; the high-speed bus clock signal can be directly connected with the HCLK defined by the AHB bus, thereby realizing the function of reading and writing data on the low-speed bus by the high-speed bus.
On the basis of the above embodiment, an embodiment of the present invention further provides a data read/write device, where the data read/write device is configured with a through circuit for reading and writing the low-speed bus by the high-speed bus.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the system and the apparatus described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In addition, in the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A switching circuit for reading and writing a low-speed bus by a high-speed bus is characterized by comprising a signal input module, a signal processing module and a signal output module which are sequentially connected;
wherein, the signal processing module comprises: the device comprises a read signal delay circuit, an address buffer register, a write data buffer register, a write signal control circuit, a write signal synchronous circuit, a write signal rising edge detection circuit, a write back response signal synchronous circuit, a write back response signal falling edge detection circuit, an asynchronous reset synchronous circuit and a bus state register;
the read signal delay circuit, the address buffer register and the write data buffer register are directly connected with the signal input module and the signal output module;
between the signal input module and the signal output module, the write signal control circuit, the write signal synchronous circuit, the write signal rising edge detection circuit, the write back response signal synchronous circuit, the write response signal falling edge detection circuit and the asynchronous reset synchronous circuit are connected in sequence, and the output end of the asynchronous reset synchronous circuit is connected with the write signal synchronous circuit, wherein the write signal control circuit, the write response signal synchronous circuit and the write response signal falling edge detection circuit are all connected with the signal input module;
the write signal control circuit, the asynchronous reset synchronous circuit and the write-back response signal falling edge detection circuit are also connected with the bus state register;
the bus state register is also connected with the signal input module;
the signal input module is used for acquiring a high-speed bus input signal and inputting the high-speed bus input signal to the signal processing module; the signal processing module is used for outputting a low-speed bus longitudinal signal through the signal output module according to the high-speed bus input signal so as to read and write data of the low-speed bus.
2. The switching circuit for reading from and writing to a low-speed bus according to claim 1, wherein the signal input module comprises a first input interface, a second input interface, a third input interface, a fourth input interface, a fifth input interface, and a low-speed bus clock signal interface;
the first input interface and the fifth input interface are connected with an input end of the read signal delay circuit, the second input interface and the fifth input interface are connected with an input end of the address buffer register, the third input interface and the fifth input interface are connected with the write data buffer register, and the fourth input interface and the fifth input interface are respectively connected with the write signal control circuit and the bus state register;
the low-speed bus clock signal interface is respectively connected with the write signal synchronous circuit, the write signal rising edge detection circuit and the asynchronous reset synchronous circuit.
3. The switching circuit for high-speed bus read/write low-speed bus according to claim 2, wherein the signal inputted by the first input interface is a high-speed bus read valid signal; the signal input by the second input interface is a high-speed bus address signal; the signal input by the third input interface is a high-speed bus write data signal; the signal input by the fourth input interface is a high-speed bus write valid signal; the signal input by the fifth input interface is a high-speed bus clock signal;
the signal input by the low-speed bus clock signal interface is a low-speed bus clock signal.
4. The switching circuit for high-speed bus read-write low-speed bus according to claim 1, wherein the signal output module comprises a first output interface, a second output interface, a third output interface and a fourth output interface;
the first output interface is connected with the output end of the read signal delay circuit;
the second output interface is connected with the output end of the address cache register;
the third output interface is connected with the output end of the write data cache register;
the fourth output interface is connected with the output end of the write signal rising edge detection circuit.
5. The switching circuit for high-speed bus read/write low-speed bus according to claim 4, wherein the signal outputted from the first output interface is a low-speed bus read valid signal; the signal output by the second output interface is a low-speed bus address signal; the signal output by the third output interface is a low-speed bus write data signal; and the signal output by the fourth output interface is a low-speed bus write valid signal.
6. The switching circuit for high-speed bus reading and writing low-speed bus according to claim 1, wherein the signal input module is disposed at the high-speed bus end, and the signal output module is disposed at the low-speed bus end;
the signal input module further comprises a first port, and the signal output module further comprises a second port;
the second port is connected with the first port and used for transmitting bus reading data signals from the low-speed bus end to the high-speed bus end.
7. The switching circuit for high-speed bus read/write low-speed bus according to claim 3, wherein the circuit operating with the high-speed bus clock signal as the driving clock comprises: the read signal delay circuit, the address buffer register, the write data buffer register, the write signal control circuit, the write response signal synchronization circuit, the write response signal falling edge detection circuit, and the bus state register.
8. The switching circuit for high-speed bus read/write low-speed bus according to claim 3, wherein the circuit operating with the low-speed bus clock signal as the driving clock comprises: the write signal synchronization circuit, the write signal rising edge detection circuit and the asynchronous reset synchronization circuit.
9. The switching circuit for reading from and writing to a low speed bus via a high speed bus according to claim 3, further comprising a first signal generating unit connected to the first input interface for generating a read valid signal via the high speed bus; the second signal generating unit is connected with the fourth input interface and used for generating the high-speed bus write effective signal;
the first signal generating unit is a unit formed by logical negation and logical AND, and the second signal generating unit is a unit formed by logical AND.
10. A data read/write device, characterized in that the data read/write device is provided with a switching circuit for reading/writing a low-speed bus from/to a high-speed bus according to any one of claims 1 to 9.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510185A (en) * | 2009-04-01 | 2009-08-19 | 北京中星微电子有限公司 | Method and apparatus for writing-in and reading data to low speed bus from high speed bus |
| CN102023956A (en) * | 2009-09-23 | 2011-04-20 | 上海摩波彼克半导体有限公司 | Serial peripheral slave device interface structure in integrated circuit chip and data reading and writing method |
| CN102750254A (en) * | 2012-06-20 | 2012-10-24 | 中国电子科技集团公司第五十八研究所 | Bidirectional conversion bridge from high-speed and high-bandwidth AHB (Advanced High Performance Bus) to low-speed and low-bandwidth AHB |
| CN102999467A (en) * | 2012-12-24 | 2013-03-27 | 中国科学院半导体研究所 | High-speed interface and low-speed interface switching circuit and method based on FPGA (Field Programmable Gate Array) |
| CN103198043A (en) * | 2013-01-24 | 2013-07-10 | 杭州中科微电子有限公司 | Improved AHB-to-APB bus bridge and control method thereof |
| CN103294411A (en) * | 2013-04-28 | 2013-09-11 | 哈尔滨工业大学 | Low-speed load data loading module with mass memory function |
| CN104572558A (en) * | 2015-01-08 | 2015-04-29 | 江苏杰瑞科技集团有限责任公司 | ISA bus-to-Multibus bus read-write operation switching circuit |
| CN105007151A (en) * | 2015-07-23 | 2015-10-28 | 株洲南车时代电气股份有限公司 | High/low-speed bus communication method and device |
| CN105512070A (en) * | 2015-12-02 | 2016-04-20 | 中国电子科技集团公司第四十一研究所 | Control system based on serial bus |
| CN105635003A (en) * | 2016-01-12 | 2016-06-01 | 陈玉平 | DMA based baseband signal processing system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4874065B2 (en) * | 2006-11-22 | 2012-02-08 | ルネサスエレクトロニクス株式会社 | Bus relay apparatus and system |
| US9495308B2 (en) * | 2012-05-22 | 2016-11-15 | Xockets, Inc. | Offloading of computation for rack level servers and corresponding methods and systems |
-
2020
- 2020-07-30 CN CN202010756421.2A patent/CN111858436B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101510185A (en) * | 2009-04-01 | 2009-08-19 | 北京中星微电子有限公司 | Method and apparatus for writing-in and reading data to low speed bus from high speed bus |
| CN102023956A (en) * | 2009-09-23 | 2011-04-20 | 上海摩波彼克半导体有限公司 | Serial peripheral slave device interface structure in integrated circuit chip and data reading and writing method |
| CN102750254A (en) * | 2012-06-20 | 2012-10-24 | 中国电子科技集团公司第五十八研究所 | Bidirectional conversion bridge from high-speed and high-bandwidth AHB (Advanced High Performance Bus) to low-speed and low-bandwidth AHB |
| CN102999467A (en) * | 2012-12-24 | 2013-03-27 | 中国科学院半导体研究所 | High-speed interface and low-speed interface switching circuit and method based on FPGA (Field Programmable Gate Array) |
| CN103198043A (en) * | 2013-01-24 | 2013-07-10 | 杭州中科微电子有限公司 | Improved AHB-to-APB bus bridge and control method thereof |
| CN103294411A (en) * | 2013-04-28 | 2013-09-11 | 哈尔滨工业大学 | Low-speed load data loading module with mass memory function |
| CN104572558A (en) * | 2015-01-08 | 2015-04-29 | 江苏杰瑞科技集团有限责任公司 | ISA bus-to-Multibus bus read-write operation switching circuit |
| CN105007151A (en) * | 2015-07-23 | 2015-10-28 | 株洲南车时代电气股份有限公司 | High/low-speed bus communication method and device |
| CN105512070A (en) * | 2015-12-02 | 2016-04-20 | 中国电子科技集团公司第四十一研究所 | Control system based on serial bus |
| CN105635003A (en) * | 2016-01-12 | 2016-06-01 | 陈玉平 | DMA based baseband signal processing system |
Non-Patent Citations (1)
| Title |
|---|
| "一种信号发生器高速内部总线实现方法";宋志强;《电子质量》;20200620(第399期);第17-20页 * |
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Denomination of invention: The Switching Circuit and Data Reading and Writing Equipment for High Speed Bus Reading and Writing Low Speed Bus Effective date of registration: 20230612 Granted publication date: 20211026 Pledgee: Silicon Valley Bank Co.,Ltd. Pledgor: Nanjing yingruichuang Electronic Technology Co.,Ltd. Registration number: Y2023310000240 |