WO2017173608A1 - Device for data transmission mode conversions - Google Patents

Device for data transmission mode conversions Download PDF

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Publication number
WO2017173608A1
WO2017173608A1 PCT/CN2016/078628 CN2016078628W WO2017173608A1 WO 2017173608 A1 WO2017173608 A1 WO 2017173608A1 CN 2016078628 W CN2016078628 W CN 2016078628W WO 2017173608 A1 WO2017173608 A1 WO 2017173608A1
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WIPO (PCT)
Prior art keywords
pin
data
fifo memory
serial
parallel
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PCT/CN2016/078628
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French (fr)
Chinese (zh)
Inventor
张科峰
彭习武
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武汉芯泰科技有限公司
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Application filed by 武汉芯泰科技有限公司 filed Critical 武汉芯泰科技有限公司
Priority to PCT/CN2016/078628 priority Critical patent/WO2017173608A1/en
Publication of WO2017173608A1 publication Critical patent/WO2017173608A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Definitions

  • the present invention relates to the field of data conversion technologies, and in particular, to a parallel and serial to parallel conversion apparatus for serial transmission of data.
  • serial transmission adopts differential signal transmission technology, which effectively overcomes the interference caused by the antenna effect on the signal transmission line and the crosstalk between the transmission lines, so that the serial transmission can obtain a high data transmission rate. And it is widely used.
  • control signal is complicated.
  • the control signal not only controls the switching of the chirp clock frequency but also the shift of the data shift register, the buffering of the data, the counting control of the output, etc., which increases the complexity of the control signal.
  • the control signals in the FPGA are composed of combined circuits, and the control signals may be glitched and mishandled in the high-frequency chirp system.
  • the cymbal clock is small in adjustability.
  • the input chirp and output clock ratios in serial-to-parallel conversion and parallel-to-serial conversion are fixed, and the design of the control signal is more complicated in the case of data delay.
  • the presence of a clock offset in the output ⁇ clock will cause an error in data conversion.
  • an embodiment of the present invention provides a parallel and serial-to-parallel conversion device for serial transmission of data
  • Embodiments of the present invention provide a parallel and serial to parallel conversion apparatus for data serial transmission, including: a parallel-to-serial conversion unit that receives parallel data and converts parallel data into serial data output, and a receiving string Row data and convert serial data into a serial-to-parallel conversion unit for parallel data output,
  • the parallel-to-serial conversion unit includes:
  • a first holding register configured to buffer parallel data transmitted by an external circuit
  • a first shift register configured to convert parallel data buffered in the first holding register into serial data
  • a first FIFO memory for buffering serial data generated by the first shift register, and controlling a buffer data output by using a read clock different from a write clock;
  • the serial to parallel conversion unit includes:
  • a second FIFO memory for buffering serial data transmitted by the external circuit, and controlling the output of the buffer data by using a read clock different from the write clock;
  • a second shift register configured to convert serial data buffered in the second FIFO memory into parallel data
  • a second holding register configured to buffer parallel data generated in the second shift register.
  • a DatalnValid pin of an external circuit is electrically connected to a Valid pin of the first holding register to control parallel data writing in an external circuit.
  • the Valid bow of the first shift register is electrically connected to the WCt I pin of the first FIFO memory, and the first shift register converts parallel data into a string Row data, its Valid pin generates a write control signal to control the first FIFO memory to write serial data; when the serial data is written in the first FIFO memory, its REmpty
  • the pin and the Usage pin respectively generate a non-empty signal and a Usage signal, the Usage signal indicating the number of Bits of the serial data stored in the first FIFO memory, and the external circuit controls the non-empty signal and the Usage signal
  • the first FIFO memory operates in a synchronous mode or an asynchronous mode, and the ek bow of the first holding register communicates with the external circuit to connect the chopping clock data of the parallel data.
  • foot and the first FIFO memory Wclk bow I pin are connected with the external circuit to write the ⁇ clock signal of the DataWClk bow
  • the data of the parallel data of the external circuit of the DatalnClk pin is connected to the clock signal frequency fDataInClk , the parallel data bit width N,
  • fDataInClk the clock signal frequency
  • N the parallel data bit width
  • the Wfull bow of the first FIFO memory is respectively connected to the Full bow of the first holding register and the Full bow of the first shift register, when the first advanced
  • the Wfull bow of the first-out memory generates a full flag, which controls the first holding register and the first shift register to suspend the input of serial data.
  • the Wfull bow of the first FIFO memory is respectively connected to the Full Bow
  • the Wfull bow of the first out memory generates a full flag, which controls the first holding register and the first shift register to suspend the input of the serial data, and identifies the first shift register and the serial string occurs. error.
  • a DATAInValid pin of an external circuit is electrically connected to a wa I pin of the second FIFO memory to control serialization in an external circuit
  • Data is written into the second FIFO memory
  • the RData bow of the second FIFO is electrically connected to the Data pin of the second shift register, and the second shift register is Ready bow
  • the RCtr pin of the second FIFO memory is electrically connected to control the serial data in the second FIFO memory to be written into the second shift register
  • foot and an Using bow I pin are respectively electrically connected to the Empty Bow
  • pins are respectively connected to the DataOutActive Bow
  • the second FIFO memory operates in a synchronous mode or an asynchronous mode
  • the Wclk pin of the second FIFO memory and the external circuit are connected to the DA of the write ⁇ clock signal.
  • the TAWClk pin is electrically connected
  • the elk bow of the second shift register and the Rclk pin of the second FIFO are connected to the DataRClk bow of the read circuit signal in the external circuit.
  • the elk pin of the second holding register is electrically connected to a DataOutClk pin of the chopping clock signal of the parallel circuit that communicates parallel data in the external circuit.
  • a FIFO memory constitutes a data buffer, which can effectively simplify the first shift register control signal
  • the composition of the number, and, the first FIFO memory can control the output of the buffer data by using a read clock different from the write gong, so that the input chord and the output gong of the parallel conversion unit can be in different clock domains. In turn, the data conversion error caused by the presence of the clock offset in the input clock and the output clock can be overcome.
  • the second FIFO memory, the second shift register, and the second holding register form a serial-to-parallel conversion.
  • a unit for converting serial data into parallel data, and performing data conversion in the second shift register, using a second FIFO memory to form a data buffer which can effectively simplify the composition of the second shift register control signal
  • the second FIFO memory can control the output of the buffer data by using a read clock different from the write ⁇ clock, so that the input ⁇ clock and the output ⁇ clock of the parallel-to-serial conversion unit can be in different clock domains, thereby being able to overcome the input ⁇ There is a data conversion error caused by the presence of a clock offset in the clock and the output chirp.
  • FIG. 1 is a schematic structural diagram of a parallel and serial to parallel conversion apparatus for serial transmission of data according to an embodiment of the present invention
  • FIG. 2 is a circuit diagram of a parallel-to-serial conversion unit according to an embodiment of the present invention
  • FIG. 3 is a circuit diagram of a serial to parallel conversion unit according to an embodiment of the present invention.
  • Embodiments of the present invention provide a parallel and serial to parallel conversion apparatus for data serial transmission.
  • the apparatus includes:
  • a parallel-to-serial conversion unit 1 that receives parallel data and converts parallel data into serial data output, and a receive string The row data is converted into serial to parallel conversion unit 2 of the parallel data output.
  • the parallel-serial conversion unit 1 includes:
  • the first holding register 11 is used to buffer parallel data transmitted by an external circuit.
  • the first shift register 12 is configured to convert the parallel data buffered in the first holding register 11 into serial data.
  • the first FIFO memory 13 is configured to buffer the serial data generated by the first shift register 12, and controls the output of the buffer data by using a read clock different from the write clock.
  • the serial to parallel conversion unit 2 includes:
  • the second FIFO memory 21 is configured to buffer serial data transmitted by the external circuit, and controls the output of the buffer data by using a read clock different from the write clock.
  • the second shift register 22 is configured to convert the serial data buffered in the second FIFO memory 21 into parallel data.
  • the second holding register 23 is configured to buffer the parallel data generated in the second shift register 22.
  • the data buffer is set in the conversion of serial data into parallel data and parallel data into serial data (ie, the first FIFO memory 13 and the second FIFO memory 21 are employed). ), this buffer can simplify the control signal and eliminate the delay that occurs after data transmission.
  • the first FIFO memory 13 and the second FIFO memory 21 may function as a data buffer, and on the other hand, a read clock different from the write cesium clock is used to control the output of the buffer data so that the The cesium clock of the parallel and serial conversion device is adjustable.
  • the converted serial data is buffered in the first FIFO memory 13 and transmitted by the first FIFO memory 13 to a line in the external circuit for transmitting serial data.
  • the device After the parallel data is converted into serial data for transmission by the above process, the device also receives the serial data and converts it into the original parallel data, as follows:
  • the converted parallel data is buffered in the second holding register 23 and transmitted to the external circuit by the second holding register 23.
  • the DatalnValid pin of the external circuit is electrically connected to the Valid bow I of the first holding register 11 to control parallel data writing in the external circuit.
  • the holding register 11 (where the data transmission line implied by the external circuit is electrically connected to the data pin D at pin of the first holding register 11); the Valid pin of the first shift register 12 and the first FIFO memory 13
  • the W Ctr pin is electrically connected.
  • the parallel data pin Data[N1,0] of the external circuit (where the width of the parallel data is N, N is a positive integer greater than 1) and the Data pin of the first holding register 11 a connection for transmitting parallel data
  • the Data In Valid pin of the circuit is electrically connected to the Valid pin of the first holding register 11 for generating a Data In Valid signal to control parallel data writing into the first holding register 11 Cache.
  • the Valid pin of the first shift register 12 is electrically connected to the WCtr pin of the first FIFO memory 13, and the Data pin of the first shift register 12 is electrically connected to the WData pin of the first FIFO memory 13,
  • the first shift register 12 converts the parallel data into serial data, and generates a write control signal, that is, a control signal for controlling the first FIFO memory 13 to write the serial data. In practical applications, it is only necessary to calibrate the parallel data to be a write control signal, which greatly simplifies the control signal of the first shift register 12.
  • First FIFO memory 13 REmpty bow
  • foot electrical connection first The TCtr pin of the FIFO memory 13 is electrically connected to the DATA Out Ready pin of the external circuit, so that the external circuit controls the first FIFO memory 13 by the non-empty signal and the Usage signal generated by the first FIFO memory 13. The output of the buffered serial data.
  • the first FIFO The WRst pin of the memory 13 (ie, the write reset pin), the Rst pin of the first shift register 12 (ie, the reset pin), and the Rst pin of the first holding register 11 (ie, the reset pin) are external to the external circuit.
  • the DataWRst pin is electrically connected; the RRst pin of the first FIFO memory 13 (ie, the read reset pin) is electrically coupled to the DataR Rst pin of the external circuit.
  • the depth of the first FIFO memory 13 can be set according to actual needs, and is not limited herein.
  • the first FIFO memory 13 may operate in a synchronous mode or an asynchronous mode, and the elk pin of the first holding register 11 (ie, the ⁇ clock pin) communicates with the ⁇ clock signal of the parallel data in the external circuit.
  • the Data In Clk pin is electrically connected, and the elk pin of the first shift register 12 (ie, the chirp clock pin) and the Wclk pin of the first FIFO memory 13 (ie, the write clock pin) are in the external circuit.
  • the DataWClk pin (that is, the data write clock pin) connected to the write ⁇ clock signal is electrically connected, and the Rclk pin of the first FIFO memory 13 (ie, the read ⁇ clock pin) is connected to the external circuit to read the ⁇ ⁇ signal.
  • the DATARClk pin is electrically connected.
  • the write clock signal connected to the first FIFO memory 13 is different from the read chord signal, and when the first FIFO memory 13 is in the synchronous mode, the ⁇ clock signal and the read ⁇ clock are written. There is an association between the signals. When the first FIFO memory 13 is in the asynchronous mode, there is no correlation between the write ⁇ clock signal and the read ⁇ clock signal.
  • the clock signal frequency f DataInak of the parallel data connected by the DatalnClk pin of the external circuit, the parallel data bit width N, and the first FIFO memory 13 The following relationship exists between the write clock signal frequency f wdk received by the Wclk pin and the read chirp signal frequency f Rdk received by the Rclk pin of the first FIFO memory 13:
  • the connection when the Wfull pin of the first FIFO memory 13 generates a full flag, controls the first holding register 11 and the first shift register 12 to suspend the input of the serial data.
  • the clock signal frequency f DataInak of the parallel data connected by the DatalnClk pin of the external circuit, the parallel data bit width N, and the first FIFO memory 13 The following relationship exists between the write cuckoo clock signal frequency f wdk received by the Wclk pin:
  • f DatalnClk/f Wclk N; [0066]
  • the Wfull bow of the first FIFO memory 13 is respectively connected to the Full Bow
  • the DATAInValid pin of the external circuit is electrically connected to the WCtr pin of the second FIFO memory 21 to control serial data writing in the external circuit.
  • the DATAIn pin of the external circuit is electrically connected to the Wdata pin of the second FIFO memory 21
  • foot electrical connection so the second FIFO memory 21 through the WCtr bow
  • the RData pin of the second FIFO memory 21 is electrically coupled to the Data bow of the second shift register 22, the Ready bow of the second shift register 22, and the RCtr of the second FIFO memory 2
  • the foot is electrically connected to control the serial data in the second FIFO memory 21 to be written in the second shift register 22.
  • foot are respectively connected with the second shift register 22's Emptyy
  • Foot is separated from the external circuit DataOutActive Bow
  • the RRst pin of the second FIFO memory 21 ie, the read reset pin
  • the Rst pin of the second shift register 22 ie, the reset pin
  • the Rst pin of the second holding register 23 ie, reset
  • the pins are electrically connected to the DataRRst pin of the external circuit
  • the WRst pin of the second FIFO 21 ie, the write reset pin
  • the depth of the second FIFO memory 21 can be set according to actual requirements, and is not limited herein.
  • the second FIFO memory 21 can operate in a synchronous mode or an asynchronous mode, and the Wclk bow of the second FIFO memory 21 is electrically connected to the DATAWClk bow of the external circuit in writing the sigma clock signal.
  • the elk bow I of the second shift register 22 and the Rclk pin I of the second FIFO memory 21 are electrically connected to the DataRClk bow of the read clock signal in the external circuit, and the elk of the second hold register 23 Bow
  • the foot and the external circuit are connected to the DataOutClk bow of the parallel data and the foot is electrically connected.
  • the write ⁇ clock signal communicated by the second FIFO memory 21 is different from the read ⁇ clock signal, and when the second FIFO memory 21 is in the synchronous mode ⁇ , the write ⁇ clock signal and the read ⁇ clock There is an association between the signals.
  • the second FIFO memory 21 is in the asynchronous mode, there is no correlation between the write chirp signal and the read chirp signal.
  • the data of the parallel circuit of the external circuit is connected to the clock signal frequency f Data of the parallel data.
  • utClk parallel data bit width N
  • read chirp signal frequency f received by Rclk pin of second FIFO memory 21 The following relationships exist between Rdk :
  • the second FIFO memory 21 adopts the asynchronous mode ⁇
  • the data of the parallel circuit of the external circuit is connected to the clock signal frequency f Data of the parallel data.
  • f Data the clock signal frequency
  • Embodiments of the present invention form a parallel-to-serial conversion unit by using a first holding register, a first shift register, and a first FIFO memory to convert parallel data into serial data, and perform data conversion in the first shift register.
  • the first FIFO memory is used to form a data buffer, which can effectively simplify the composition of the first shift register control signal, and the first FIFO memory can control the cache data by using a different read clock from the write clock.
  • the output makes the input chirp and output chirp of the parallel-to-serial conversion unit in different clock domains, which can overcome the data conversion error caused by the presence of the clock offset in the input chirp and the output chirp;
  • the second FIFO memory, the second shift register, and the second holding register form a serial-to-parallel conversion unit to convert serial data into parallel data, and perform data conversion in the second shift register, using the second advanced
  • the first-out memory constitutes a data buffer, which can effectively simplify the control signal of the second shift register.
  • the second FIFO memory can control the output of the buffer data by using a read clock different from the write clock, so that the input clock and the output clock of the parallel-to-serial conversion unit can be in different clock domains, and thus Overcome data conversion errors caused by the presence of a clock offset in the input cesium and output cesium.

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  • Theoretical Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Disclosed in the present invention is a device for performing parallel-serial and serial-parallel conversions for serial data transmission , comprising: a parallel-serial conversion unit which receives parallel data, converts the parallel data into serial data and outputs it, and a serial-parallel conversion unit which receives serial data, converts the serial data into parallel data and outputs it. The present invention implements the conversion of parallel data into serial data by means of the parallel-serial conversion unit which consists of a first holding register, a first shift register and a first first-in first-out memory, and implements the conversion of serial data into parallel data by means of the serial-parallel conversion unit which consists of a second first-in first-out memory, a second shift register and a second holding register. For performing the data conversion, the device is provided with a data buffer, which can effectively simplify a data conversion control signal; moreover, the input clock and the output clock of the device can be in different clock domains, thereby data conversion errors caused by clock shifts existing in the input clock and output clock can be overcome.

Description

说明书 发明名称:数据传输方式转换装置 技术领域  Specification Name of Invention: Data Transmission Mode Conversion Device Technical Field
[0001] 本发明涉及数据转化技术领域， 特别涉及一种用于数据串行传输的并串、 串并 转换装置。  [0001] The present invention relates to the field of data conversion technologies, and in particular, to a parallel and serial to parallel conversion apparatus for serial transmission of data.
背景技术  Background technique
[0002] 随着现代科技的发展， 数据传输技术也得到了长足的发展， 在数据传输的过程 中， 随着吋钟频率越来越高， 并行传输吋， 并行导线之间的相互干扰越来越严 重， 并行传输方式发展到了瓶颈。 而串行传输采用差分信号 (differential signal)传 输技术， 有效地克服了因天线效应对信号传输线路形成的干扰， 以及传输线路 之间的串扰， 使得串行传输能够获得很高的数据传输率， 而受到广泛应用。  [0002] With the development of modern technology, data transmission technology has also been greatly developed. In the process of data transmission, as the frequency of the chirp clock is getting higher and higher, parallel transmission is performed, and mutual interference between parallel wires is coming. The more serious, the parallel transmission method has developed into a bottleneck. The serial transmission adopts differential signal transmission technology, which effectively overcomes the interference caused by the antenna effect on the signal transmission line and the crosstalk between the transmission lines, so that the serial transmission can obtain a high data transmission rate. And it is widely used.
[0003] 现有的现场可编程门阵列 （Field Programmable Gate Array , 简称" FPGA") 技 术中， 为了实现数据的串行传输， 往往会先将电路中的并行数据转化成串行数 据进行传输， 再在传输结束吋将串行数据重新转化为并行数据。 其中， 为了实 现并串、 串并转换， 需要先将数据先放入保持寄存器， 然后通过控制信号在放 进移位寄存器中进行缓存， 最后通过计数器产生来输出信号来将数据进行输出  [0003] In the existing Field Programmable Gate Array ("FPGA") technology, in order to realize serial transmission of data, parallel data in the circuit is first converted into serial data for transmission. The serial data is then reconverted to parallel data at the end of the transfer. In order to realize parallel and serial-to-serial conversion, the data needs to be first put into the holding register, then buffered by the control signal in the shift register, and finally outputted by the counter to output the signal to output the data.
[0004] 但是依靠移位寄存器来缓存数据， 存在以下问题： [0004] However, relying on a shift register to buffer data has the following problems:
[0005] 控制信号复杂。 在 FPGA设计中， 控制信号不仅控制吋钟频率的切换还要负责 数据移位寄存器的移位、 数据的缓冲、 输出的计数控制等， 这样会增加控制信 号的复杂度。 FPGA中控制信号是由组合电路构成， 在高频吋钟***中控制信号 会出现毛刺和误操作。  [0005] The control signal is complicated. In the FPGA design, the control signal not only controls the switching of the chirp clock frequency but also the shift of the data shift register, the buffering of the data, the counting control of the output, etc., which increases the complexity of the control signal. The control signals in the FPGA are composed of combined circuits, and the control signals may be glitched and mishandled in the high-frequency chirp system.
[0006] 吋钟可调性小。 现有的 FPGA设计中串并转换和并串转换中的输入吋钟和输出 吋钟比是固定不变的， 在遇到数据延吋吋其控制信号的设计会更加的复杂， 在 输入吋钟和输出吋钟中存在吋钟偏移吋都会导致数据转换的错误。  [0006] The cymbal clock is small in adjustability. In the existing FPGA design, the input chirp and output clock ratios in serial-to-parallel conversion and parallel-to-serial conversion are fixed, and the design of the control signal is more complicated in the case of data delay. And the presence of a clock offset in the output 吋 clock will cause an error in data conversion.
技术问题  technical problem
[0007] 为了解决现有技术中依靠移位寄存器来缓存数据存在的信号复杂、 吋钟可调性 小的问题， 本发明实施例提供了一种用于数据串行传输的并串、 串并转换装置 [0007] In order to solve the problem in the prior art that relying on a shift register to buffer data, the signal is complicated and the clock is adjustable. Small problem, an embodiment of the present invention provides a parallel and serial-to-parallel conversion device for serial transmission of data
问题的解决方案 Problem solution
技术解决方案  Technical solution
[0008] 本发明实施例提供了一种用于数据串行传输的并串、 串并转换装置， 包括： 接 收并行数据并将并行数据转换为串行数据输出的并串转换单元， 和接收串行数 据并将串行数据转化为并行数据输出的串并转换单元，  [0008] Embodiments of the present invention provide a parallel and serial to parallel conversion apparatus for data serial transmission, including: a parallel-to-serial conversion unit that receives parallel data and converts parallel data into serial data output, and a receiving string Row data and convert serial data into a serial-to-parallel conversion unit for parallel data output,
[0009] 所述并串转换单元包括：  [0009] The parallel-to-serial conversion unit includes:
[0010] 第一保持寄存器， 用于缓存外部电路传输的并行数据；  [0010] a first holding register, configured to buffer parallel data transmitted by an external circuit;
[0011] 第一移位寄存器， 用于将所述第一保持寄存器中缓存的并行数据转换成串行数 据；  [0011] a first shift register, configured to convert parallel data buffered in the first holding register into serial data;
[0012] 第一先进先出存储器， 用于缓存所述第一移位寄存器生成的串行数据， 并采用 与写吋钟不同的读吋钟来控制缓存数据的输出；  [0012] a first FIFO memory for buffering serial data generated by the first shift register, and controlling a buffer data output by using a read clock different from a write clock;
[0013] 所述串并转换单元包括： [0013] The serial to parallel conversion unit includes:
[0014] 第二先进先出存储器， 用于缓存外部电路传输的串行数据， 并采用与写吋钟不 同的读吋钟来控制缓存数据的输出；  [0014] a second FIFO memory for buffering serial data transmitted by the external circuit, and controlling the output of the buffer data by using a read clock different from the write clock;
[0015] 第二移位寄存器， 用于将所述第二先进先出存储器中缓存的串行数据转换成并 行数据； [0015] a second shift register, configured to convert serial data buffered in the second FIFO memory into parallel data;
[0016] 第二保持寄存器， 用于缓存所述第二移位寄存器中生成的并行数据。  [0016] a second holding register, configured to buffer parallel data generated in the second shift register.
[0017] 在本发明上述的装置中， 在所述并串转换单元中， 外部电路的 DatalnValid引脚 与所述第一保持寄存器的 Valid引脚电连接， 来控制外部电路中的并行数据写入 所述第一保持寄存器中； 所述第一移位寄存器的 Valid弓 I脚与所述第一先进先出 存储器的 WCt I脚电连接， 当所述第一移位寄存器将并行数据转换成串行数据 吋， 其 Valid引脚会产生写入控制信号， 以控制所述第一先进先出存储器写入串 行数据； 当所述第一先进先出存储器中写入串行数据吋， 其 REmpty引脚和 Usage ing引脚分别产生非空信号和 Usageing信号， 所述 Usageing信号表示所述第一先进 先出存储器中储存串行数据的 Bit数， 外部电路通过非空信号和 Usageing信号来 控制所述第一先进先出存储器中缓存的串行数据的输出。 [0018] 在本发明上述的装置中， 所述第一先进先出存储器采用同步模式或者异步模式 工作， 所述第一保持寄存器的 elk弓 I脚与外部电路中连通并行数据的吋钟信号的 D atalnClk弓 |脚电连接， 所述第一移位寄存器的 elk弓 |脚和所述第一先进先出存储器 的 Wclk弓 I脚均与外部电路中连通写吋钟信号的 DataWClk弓 |脚电连接， 所述第一 先进先出存储器的 Rclk弓 I脚与外部电路中连通读吋钟信号的 DATARClk弓 |脚电连 接。 [0017] In the above apparatus of the present invention, in the parallel-to-serial conversion unit, a DatalnValid pin of an external circuit is electrically connected to a Valid pin of the first holding register to control parallel data writing in an external circuit. In the first holding register; the Valid bow of the first shift register is electrically connected to the WCt I pin of the first FIFO memory, and the first shift register converts parallel data into a string Row data, its Valid pin generates a write control signal to control the first FIFO memory to write serial data; when the serial data is written in the first FIFO memory, its REmpty The pin and the Usage pin respectively generate a non-empty signal and a Usage signal, the Usage signal indicating the number of Bits of the serial data stored in the first FIFO memory, and the external circuit controls the non-empty signal and the Usage signal The output of the serial data buffered in the first FIFO memory. [0018] In the above apparatus of the present invention, the first FIFO memory operates in a synchronous mode or an asynchronous mode, and the ek bow of the first holding register communicates with the external circuit to connect the chopping clock data of the parallel data. D atalnClk bow | foot electrical connection, the first shift register elk bow | foot and the first FIFO memory Wclk bow I pin are connected with the external circuit to write the 吋 clock signal of the DataWClk bow | Connected, the Rclk pin 1 of the first FIFO memory is electrically connected to the DATARClk bow|foot of the external circuit that is connected to the read chirp signal.
[0019] 在本发明上述的装置中， 当所述第一先进先出存储器采用同步模式吋， 外部电 路的 DatalnClk引脚连通的并行数据的吋钟信号频率 f DataInClk、 并行数据位宽 N、 所 述第一先进先出存储器的 Wclk引脚接收的写吋钟信号频率 f wdk、 以及所述第一 先进先出存储器的 Rclk引脚接收的读吋钟信号频率 f Rdk之间存在如下关系： [0019] In the above apparatus of the present invention, when the first FIFO memory adopts a synchronous mode, the data of the parallel data of the external circuit of the DatalnClk pin is connected to the clock signal frequency fDataInClk , the parallel data bit width N, The following relationship exists between the write chirp signal frequency f wdk received by the Wclk pin of the first FIFO memory and the read chirp signal frequency f Rdk received by the Rclk pin of the first FIFO memory:
[0020] f DatalnClk/f Wclk" f DatalnClk/f Rclk" ；  [0020] f DatalnClk/f Wclk" f DatalnClk/f Rclk";
[0021] 所述第一先进先出存储器的 Wfull弓 I脚分别与所述第一保持寄存器的 Full弓 I脚和 所述第一移位寄存器的 Full弓 I脚连接， 当所述第一先进先出存储器的 Wfull弓 I脚产 生满标识吋， 会控制所述第一保持寄存器和所述第一移位寄存器暂停串行数据 的输入。  [0021] The Wfull bow of the first FIFO memory is respectively connected to the Full bow of the first holding register and the Full bow of the first shift register, when the first advanced The Wfull bow of the first-out memory generates a full flag, which controls the first holding register and the first shift register to suspend the input of serial data.
[0022] 在本发明上述的装置中， 当所述第一先进先出存储器采用异步模式吋， 外部电 路的 DatalnClk引脚连通的并行数据的吋钟信号频率 f DataInClk、 并行数据位宽 N、 所 述第一先进先出存储器的 Wclk引脚接收的写吋钟信号频率 f wdk之间存在如下关 系： [0022] In the above apparatus of the present invention, when the first FIFO memory adopts an asynchronous mode, the data of the parallel data of the external circuit of the DatalnClk pin is connected to the clock signal frequency fDataInClk , the parallel data bit width N, The following relationship exists between the write clock signal frequency f wdk received by the Wclk pin of the first FIFO memory:
[0023] f DatalnClk/f Wclk =N;  [0023] f DatalnClk / f Wclk = N;
[0024] 所述第一先进先出存储器的 Wfull弓 I脚分别与所述第一保持寄存器的 Full弓 |脚和 所述第一移位寄存器的 Full弓 I脚连接， 当所述第一先进先出存储器的 Wfull弓 I脚产 生满标识吋， 会控制所述第一保持寄存器和所述第一移位寄存器暂停串行数据 的输入， 并标识所述第一移位寄存器中并转串发生错误。  [0024] the Wfull bow of the first FIFO memory is respectively connected to the Full Bow|foot of the first holding register and the Full bow of the first shift register, when the first advanced The Wfull bow of the first out memory generates a full flag, which controls the first holding register and the first shift register to suspend the input of the serial data, and identifies the first shift register and the serial string occurs. error.
[0025] 在本发明上述的装置中， 在所述串并转换单元中， 外部电路的 DATAInValid引 脚与所述第二先进先出存储器的 wa I脚电连接， 来控制外部电路中的串行数 据写入所述第二先进先出存储器中； 所述第二先进先出存储器的 RData弓 |脚与所 述第二移位寄存器的 Data弓 I脚电连接， 所述第二移位寄存器的 Ready弓 |脚与所述 第二先进先出存储器的 RCtr弓 I脚电连接， 以控制所述第二先进先出存储器中的串 行数据写入所述第二移位寄存器中； 所述第二先进先出存储器的 REmpty弓 |脚和 Usaging弓 I脚分别与所述第二移位寄存器的 Empty弓 |脚和 Use弓 |脚电连接， 以控制 所述第二移位寄存器将串行数据转化为并行数据； 所述第二保持寄存器的 Active 弓 I脚和 Ready弓 |脚分别与外部电路的 DataOutActive弓 |脚和 DataOutReady弓 |脚电连 接， 用于控制外部电路读取所述第二保持寄存器中缓存的并行数据。 [0025] In the above apparatus of the present invention, in the serial to parallel conversion unit, a DATAInValid pin of an external circuit is electrically connected to a wa I pin of the second FIFO memory to control serialization in an external circuit Data is written into the second FIFO memory; the RData bow of the second FIFO is electrically connected to the Data pin of the second shift register, and the second shift register is Ready bow | foot with the stated The RCtr pin of the second FIFO memory is electrically connected to control the serial data in the second FIFO memory to be written into the second shift register; the REmpty of the second FIFO memory a bow|foot and an Using bow I pin are respectively electrically connected to the Empty Bow|Foot and Use Bow|foot of the second shift register to control the second shift register to convert serial data into parallel data; The second holding register's Active Bow I and Ready Bow | pins are respectively connected to the DataOutActive Bow | Foot and DataOutReady Bow | Foot of the external circuit, and are used to control the external circuit to read the parallel data buffered in the second holding register.
[0026] 在本发明上述的装置中， 所述第二先进先出存储器采用同步模式或者异步模式 工作， 所述第二先进先出存储器的 Wclk引脚与外部电路中连通写吋钟信号的 DA TAWClk弓 I脚电连接， 所述第二移位寄存器的 elk弓 I脚和所述第二先进先出存储器 的 Rclk弓 I脚均与外部电路中连通读吋钟信号的 DataRClk弓 |脚电连接， 所述第二保 持寄存器的 elk引脚与外部电路中连通并行数据的吋钟信号的 DataOutClk引脚电 连接。 In the above apparatus of the present invention, the second FIFO memory operates in a synchronous mode or an asynchronous mode, and the Wclk pin of the second FIFO memory and the external circuit are connected to the DA of the write 吋 clock signal. The TAWClk pin is electrically connected, the elk bow of the second shift register and the Rclk pin of the second FIFO are connected to the DataRClk bow of the read circuit signal in the external circuit. The elk pin of the second holding register is electrically connected to a DataOutClk pin of the chopping clock signal of the parallel circuit that communicates parallel data in the external circuit.
[0027] 在本发明上述的装置中， 当所述第二先进先出存储器采用同步模式吋， 外部电 路的 DataOutClk引脚连通的并行数据的吋钟信号频率 f Data。utClk、 并行数据位宽 N、 所述第二先进先出存储器的 Wclk引脚接收的写吋钟信号频率 f wdk、 以及所述第 二先进先出存储器的 Rclk引脚接收的读吋钟信号频率 f Rdk之间存在如下关系：[0027] In the above apparatus of the present invention, when the second FIFO memory adopts the synchronous mode 吋, the data of the parallel circuit of the external circuit is connected to the clock signal frequency f Data of the parallel data. utClk , parallel data bit width N, write clock signal frequency f wdk received by the Wclk pin of the second FIFO memory, and read chirp signal frequency received by the Rclk pin of the second FIFO memory The following relationship exists between f Rdk :
[0028] f DataOutClk/f Wclk" f DataOutClk/f Rclk=N。 [0028] f DataOutClk/f Wclk" f DataOutClk/f Rclk=N.
[0029] 在本发明上述的装置中， 当所述第二先进先出存储器采用异步模式吋， 外部电 路的 DataOutClk引脚连通的并行数据的吋钟信号频率 f Data。utClk、 并行数据位宽 N、 以及所述第二先进先出存储器的 Rclk引脚接收的读吋钟信号频率 f wdk之间存在如 下关系： [0029] In the above apparatus of the present invention, when the second FIFO memory adopts an asynchronous mode 吋, the data of the parallel circuit of the external circuit is connected to the clock signal frequency f Data of the parallel data. The following relationship exists between utClk , the parallel data bit width N, and the read chirp signal frequency f wdk received by the Rclk pin of the second FIFO memory:
[0030] f DataOutClk/f Rclk=N。  [0030] f DataOutClk/f Rclk=N.
发明的有益效果  Advantageous effects of the invention
有益效果  Beneficial effect
[0031] 本发明实施例提供的技术方案带来的有益效果是：  [0031] The beneficial effects brought by the technical solutions provided by the embodiments of the present invention are:
[0032] 通过第一保持寄存器、 第一移位寄存器、 第一先进先出存储器构成并串转换单 元， 以实现并行数据转化为串行数据， 在第一移位寄存器进行数据转化吋， 采 用第一先进先出存储器构成数据缓冲区， 可以有效简化第一移位寄存器控制信 号的组成， 而且， 第一先进先出存储器可以采用与写吋钟不同的读吋钟来控制 缓存数据的输出， 使得并串转换单元的输入吋钟和输出吋钟可以处于不同吋钟 域， 进而可以克服由于输入吋钟和输出吋钟中存在吋钟偏移吋都会导致的数据 转换错误； 同理， 通过第二先进先出存储器、 第二移位寄存器、 第二保持寄存 器构成串并转换单元， 以实现串行数据转化为并行数据， 在第二移位寄存器进 行数据转化吋， 采用第二先进先出存储器构成数据缓冲区， 可以有效简化第二 移位寄存器控制信号的组成， 而且， 第二先进先出存储器可以采用与写吋钟不 同的读吋钟来控制缓存数据的输出， 使得并串转换单元的输入吋钟和输出吋钟 可以处于不同吋钟域， 进而可以克服由于输入吋钟和输出吋钟中存在吋钟偏移 吋都会导致的数据转换错误。 [0032] forming a parallel-to-serial conversion unit by using a first holding register, a first shift register, and a first FIFO memory to convert parallel data into serial data, and performing data conversion in the first shift register, A FIFO memory constitutes a data buffer, which can effectively simplify the first shift register control signal The composition of the number, and, the first FIFO memory can control the output of the buffer data by using a read clock different from the write gong, so that the input chord and the output gong of the parallel conversion unit can be in different clock domains. In turn, the data conversion error caused by the presence of the clock offset in the input clock and the output clock can be overcome. Similarly, the second FIFO memory, the second shift register, and the second holding register form a serial-to-parallel conversion. a unit for converting serial data into parallel data, and performing data conversion in the second shift register, using a second FIFO memory to form a data buffer, which can effectively simplify the composition of the second shift register control signal, and The second FIFO memory can control the output of the buffer data by using a read clock different from the write 吋 clock, so that the input 吋 clock and the output 吋 clock of the parallel-to-serial conversion unit can be in different clock domains, thereby being able to overcome the input 吋There is a data conversion error caused by the presence of a clock offset in the clock and the output chirp.
对附图的简要说明  Brief description of the drawing
附图说明  DRAWINGS
[0033] 为了更清楚地说明本发明实施例中的技术方案， 下面将对实施例描述中所需要 使用的附图作简单地介绍， 显而易见地， 下面描述中的附图仅仅是本发明的一 些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还 可以根据这些附图获得其他的附图。  [0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. Obviously, the drawings in the following description are only some of the present invention. For the embodiments, those skilled in the art can obtain other drawings according to the drawings without any creative work.
[0034] 图 1是本发明实施例提供的一种用于数据串行传输的并串、 串并转换装置的结 构示意图；  1 is a schematic structural diagram of a parallel and serial to parallel conversion apparatus for serial transmission of data according to an embodiment of the present invention;
[0035] 图 2是本发明实施例提供的一种并串转换单元的电路图；  2 is a circuit diagram of a parallel-to-serial conversion unit according to an embodiment of the present invention;
[0036] 图 3是本发明实施例提供的一种串并转换单元的电路图。 3 is a circuit diagram of a serial to parallel conversion unit according to an embodiment of the present invention.
本发明的实施方式 Embodiments of the invention
[0037] 为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本发明实施 方式作进一步地详细描述。  The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.
实施例  Example
[0038] 本发明实施例提供了一种用于数据串行传输的并串、 串并转换装置， 参见图 1 ， 该装置包括：  [0038] Embodiments of the present invention provide a parallel and serial to parallel conversion apparatus for data serial transmission. Referring to FIG. 1, the apparatus includes:
[0039] 接收并行数据并将并行数据转换为串行数据输出的并串转换单元 1， 和接收串 行数据并将串行数据转化为并行数据输出的串并转换单元 2。 [0039] a parallel-to-serial conversion unit 1 that receives parallel data and converts parallel data into serial data output, and a receive string The row data is converted into serial to parallel conversion unit 2 of the parallel data output.
[0040] 参见图 2， 该并串转换单元 1包括： [0040] Referring to FIG. 2, the parallel-serial conversion unit 1 includes:
[0041] 第一保持寄存器 11， 用于缓存外部电路传输的并行数据。  [0041] The first holding register 11 is used to buffer parallel data transmitted by an external circuit.
[0042] 第一移位寄存器 12， 用于将第一保持寄存器 11中缓存的并行数据转换成串行数 据。  [0042] The first shift register 12 is configured to convert the parallel data buffered in the first holding register 11 into serial data.
[0043] 第一先进先出存储器 13， 用于缓存第一移位寄存器 12生成的串行数据， 并采用 与写吋钟不同的读吋钟来控制缓存数据的输出。  The first FIFO memory 13 is configured to buffer the serial data generated by the first shift register 12, and controls the output of the buffer data by using a read clock different from the write clock.
[0044] 参见图 3， 该串并转换单元 2包括： [0044] Referring to FIG. 3, the serial to parallel conversion unit 2 includes:
[0045] 第二先进先出存储器 21， 用于缓存外部电路传输的串行数据， 并采用与写吋钟 不同的读吋钟来控制缓存数据的输出。  [0045] The second FIFO memory 21 is configured to buffer serial data transmitted by the external circuit, and controls the output of the buffer data by using a read clock different from the write clock.
[0046] 第二移位寄存器 22， 用于将第二先进先出存储器 21中缓存的串行数据转换成并 行数据。 [0046] The second shift register 22 is configured to convert the serial data buffered in the second FIFO memory 21 into parallel data.
[0047] 第二保持寄存器 23， 用于缓存第二移位寄存器 22中生成的并行数据。  [0047] The second holding register 23 is configured to buffer the parallel data generated in the second shift register 22.
[0048] 在本实施例中， 在串行数据转化成并行数据和并行数据转换成串行数据吋均设 置数据缓冲区 （即采用了第一先进先出存储器 13和第二先进先出存储器 21) ， 这个缓冲区可以简化控制信号、 消除数据传输吋出现的延吋。 第一先进先出存 储器 13和第二先进先出存储器 21—方面可以作为数据缓冲区来起作用， 另一方 面， 又采用与写吋钟不同的读吋钟来控制缓存数据的输出， 使得该并串、 串并 转换装置的吋钟可调。  [0048] In the present embodiment, the data buffer is set in the conversion of serial data into parallel data and parallel data into serial data (ie, the first FIFO memory 13 and the second FIFO memory 21 are employed). ), this buffer can simplify the control signal and eliminate the delay that occurs after data transmission. The first FIFO memory 13 and the second FIFO memory 21 may function as a data buffer, and on the other hand, a read clock different from the write cesium clock is used to control the output of the buffer data so that the The cesium clock of the parallel and serial conversion device is adjustable.
[0049] 在本实施例中， 上述装置的数据转化过程如下：  [0049] In this embodiment, the data conversion process of the above device is as follows:
[0050] 先将外部电路中的并行数据缓存在第一保持寄存器 11中；  [0050] first buffering parallel data in the external circuit in the first holding register 11;
[0051 ] 然后将第一保持寄存器 11中缓存的并行数据通过第一移位寄存器 12转化成串行 数据；  [0051] then parallel data buffered in the first holding register 11 is converted into serial data by the first shift register 12;
[0052] 最后将转化好的串行数据缓存在第一先进先出存储器 13中， 并由第一先进先出 存储器 13传输至外部电路中用于传输串行数据的线路中。  Finally, the converted serial data is buffered in the first FIFO memory 13 and transmitted by the first FIFO memory 13 to a line in the external circuit for transmitting serial data.
[0053] 通过上述过程将并行数据转化成串行数据进行传输后， 该装置还会接收串行数 据并将其转化成原本的并行数据， 具体过程如下： [0053] After the parallel data is converted into serial data for transmission by the above process, the device also receives the serial data and converts it into the original parallel data, as follows:
[0054] 先将外部电路中的串行数据缓存在第二先进先出存储器 21中； [0055] 然后将串行数据通过第二移位寄存器 22转化成并行数据； [0054] first buffering serial data in the external circuit in the second FIFO memory 21; [0055] then serial data is converted into parallel data by the second shift register 22;
[0056] 最后将转化好的并行数据缓存在第二保持寄存器 23中， 并由第二保持寄存器 23 传输至外部电路中。  [0056] Finally, the converted parallel data is buffered in the second holding register 23 and transmitted to the external circuit by the second holding register 23.
[0057] 具体地， 参见图 2， 在并串转换单元 1中， 外部电路的 DatalnValid引脚与第一保 持寄存器 11的 Valid弓 I脚电连接， 来控制外部电路中的并行数据写入第一保持寄 存器 11中 （其中隐含了外部电路的数据传输线与第一保持寄存器 11的数据引脚 D ata引脚电连接） ； 第一移位寄存器 12的 Valid引脚与第一先进先出存储器 13的 W Ctr引脚电连接， 当第一移位寄存器 12将并行数据转换成串行数据吋， 其 Valid引 脚会产生写入控制信号， 以控制第一先进先出存储器 13写入串行数据 （其中隐 含了第一移位寄存器 12的数据引脚 Data引脚与第一先进先出存储器 13的 WData引 脚电连接） ； 当第一先进先出存储器 13中写入串行数据吋， 其 REmpty引脚和 Usa geing引脚分别产生非空信号和 Usageing信号， 该 Usageing信号表示第一先进先出 存储器 13中储存串行数据的 Bit数， 外部电路通过非空信号和 Usageing信号来控 制第一先进先出存储器 13中缓存的串行数据的输出。  [0057] Specifically, referring to FIG. 2, in the parallel-serial conversion unit 1, the DatalnValid pin of the external circuit is electrically connected to the Valid bow I of the first holding register 11 to control parallel data writing in the external circuit. The holding register 11 (where the data transmission line implied by the external circuit is electrically connected to the data pin D at pin of the first holding register 11); the Valid pin of the first shift register 12 and the first FIFO memory 13 The W Ctr pin is electrically connected. When the first shift register 12 converts parallel data into serial data, its Valid pin generates a write control signal to control the first FIFO memory 13 to write serial data. (It implies that the data pin Data pin of the first shift register 12 is electrically connected to the WData pin of the first FIFO memory 13); when the serial data is written in the first FIFO memory 13, The REmpty pin and the Usa geing pin respectively generate a non-empty signal and a Usage signal, and the Usage signal indicates the number of bits of the serial data stored in the first FIFO memory 13, and the external power The path controls the output of the serial data buffered in the first FIFO memory 13 by the non-empty signal and the Usageing signal.
[0058] 在本实施例中， 外部电路的并行数据引脚 Data[N-l,0] (其中并行数据的宽度为 N， N为大于 1的正整数） 与第一保持寄存器 11的 Data引脚电连接， 用于传输并行 数据， 夕卜部电路的 Data In Valid引脚与第一保持寄存器 11的 Valid引脚电连接， 用 于产生 Data In Valid信号来控制并行数据写入第一保持寄存器 11中进行缓存。 第 一移位寄存器 12的 Valid引脚与第一先进先出存储器 13的 WCtr引脚电连接， 第一 移位寄存器 12的 Data引脚与第一先进先出存储器 13的 WData引脚电连接， 第一移 位寄存器 12在进行并行数据转化为串行数据吋， 会产生写入控制信号， 即控制 第一先进先出存储器 13写入串行数据的控制信号。 在实际应用中， 只需要标定 并行数据有效为写入控制信号， 就可以大大简化第一移位寄存器 12的控制信号 。 第一先进先出存储器 13的 REmpty弓 |脚与外部电路的 DATA Out Valid弓 |脚电连 接， 第一先进先出存储器 13的 Usageing弓 |脚与外部电路的 DataUsageing弓 |脚电连 接， 第一先进先出存储器 13的 TCtr引脚与外部电路的 DATA Out Ready引脚电连 接， 这样， 外部电路通过第一先进先出存储器 13产生的非空信号和 Usageing信号 来控制第一先进先出存储器 13中缓存的串行数据的输出。 此外， 第一先进先出 存储器 13的 WRst引脚 （即写复位引脚） 、 第一移位寄存器 12的 Rst引脚 （即复位 引脚） 、 第一保持寄存器 11的 Rst引脚 （即复位引脚） 均与外部电路的 DataWRst 引脚电连接； 第一先进先出存储器 13的 RRst引脚 （即读复位引脚） 与外部电路 的 DataR Rst引脚电连接。 此外， 第一先进先出存储器 13的深度可以根据实际需 求设定， 这里不做限制。 [0058] In this embodiment, the parallel data pin Data[N1,0] of the external circuit (where the width of the parallel data is N, N is a positive integer greater than 1) and the Data pin of the first holding register 11 a connection for transmitting parallel data, the Data In Valid pin of the circuit is electrically connected to the Valid pin of the first holding register 11 for generating a Data In Valid signal to control parallel data writing into the first holding register 11 Cache. The Valid pin of the first shift register 12 is electrically connected to the WCtr pin of the first FIFO memory 13, and the Data pin of the first shift register 12 is electrically connected to the WData pin of the first FIFO memory 13, The first shift register 12 converts the parallel data into serial data, and generates a write control signal, that is, a control signal for controlling the first FIFO memory 13 to write the serial data. In practical applications, it is only necessary to calibrate the parallel data to be a write control signal, which greatly simplifies the control signal of the first shift register 12. First FIFO memory 13 REmpty bow | foot with external circuit DATA Out Valid bow | foot electrical connection, first FIFO memory 13 USSageing bow | foot with external circuit DataUsageing bow | foot electrical connection, first The TCtr pin of the FIFO memory 13 is electrically connected to the DATA Out Ready pin of the external circuit, so that the external circuit controls the first FIFO memory 13 by the non-empty signal and the Usage signal generated by the first FIFO memory 13. The output of the buffered serial data. In addition, the first FIFO The WRst pin of the memory 13 (ie, the write reset pin), the Rst pin of the first shift register 12 (ie, the reset pin), and the Rst pin of the first holding register 11 (ie, the reset pin) are external to the external circuit. The DataWRst pin is electrically connected; the RRst pin of the first FIFO memory 13 (ie, the read reset pin) is electrically coupled to the DataR Rst pin of the external circuit. In addition, the depth of the first FIFO memory 13 can be set according to actual needs, and is not limited herein.
[0059] 进一步地， 第一先进先出存储器 13可以采用同步模式或者异步模式工作， 第一 保持寄存器 11的 elk引脚 （即吋钟引脚） 与外部电路中连通并行数据的吋钟信号 的 Data In Clk引脚电连接， 第一移位寄存器 12的 elk引脚 （即吋钟引脚） 和第一先 进先出存储器 13的 Wclk引脚 （即写吋钟引脚） 均与外部电路中连通写吋钟信号 的 DataWClk引脚 （即数据写吋钟引脚） 电连接， 第一先进先出存储器 13的 Rclk 引脚 （即读吋钟引脚） 与外部电路中连通读吋钟信号的 DATARClk引脚电连接。  [0059] Further, the first FIFO memory 13 may operate in a synchronous mode or an asynchronous mode, and the elk pin of the first holding register 11 (ie, the 吋 clock pin) communicates with the 电路 clock signal of the parallel data in the external circuit. The Data In Clk pin is electrically connected, and the elk pin of the first shift register 12 (ie, the chirp clock pin) and the Wclk pin of the first FIFO memory 13 (ie, the write clock pin) are in the external circuit. The DataWClk pin (that is, the data write clock pin) connected to the write 吋 clock signal is electrically connected, and the Rclk pin of the first FIFO memory 13 (ie, the read 吋 clock pin) is connected to the external circuit to read the 吋 信号 signal. The DATARClk pin is electrically connected.
[0060] 在本实施例中， 第一先进先出存储器 13连通的写吋钟信号与读吋钟信号不同， 当第一先进先出存储器 13采用同步模式吋， 写吋钟信号与读吋钟信号之间存在 关联， 当第一先进先出存储器 13采用异步模式吋， 写吋钟信号与读吋钟信号之 间不存在关联。  [0060] In the embodiment, the write clock signal connected to the first FIFO memory 13 is different from the read chord signal, and when the first FIFO memory 13 is in the synchronous mode, the 吋 clock signal and the read 吋 clock are written. There is an association between the signals. When the first FIFO memory 13 is in the asynchronous mode, there is no correlation between the write 吋 clock signal and the read 吋 clock signal.
[0061] 进一步地， 当第一先进先出存储器 13采用同步模式吋， 外部电路的 DatalnClk引 脚连通的并行数据的吋钟信号频率 f DataInak、 并行数据位宽 N、 第一先进先出存储 器 13的 Wclk引脚接收的写吋钟信号频率 f wdk、 以及第一先进先出存储器 13的 Rclk 引脚接收的读吋钟信号频率 f Rdk之间存在如下关系： [0061] Further, when the first FIFO memory 13 adopts the synchronization mode 吋 , the clock signal frequency f DataInak of the parallel data connected by the DatalnClk pin of the external circuit, the parallel data bit width N, and the first FIFO memory 13 The following relationship exists between the write clock signal frequency f wdk received by the Wclk pin and the read chirp signal frequency f Rdk received by the Rclk pin of the first FIFO memory 13:
[0062] f DatalnClk/f Wclk" f DatalnClk/f Rclk" ；  [0062] f DatalnClk/f Wclk" f DatalnClk/f Rclk";
[0063] 第一先进先出存储器 13的 Wfull引脚 （即写满引脚） 分别与第一保持寄存器 11 的 Full引脚 （即满信号引脚） 和第一移位寄存器 12的 Full引脚连接， 当第一先进 先出存储器 13的 Wfull引脚产生满标识吋， 会控制第一保持寄存器 11和第一移位 寄存器 12暂停串行数据的输入。  [0063] The Wfull pin (ie, the full pin) of the first FIFO memory 13 and the Full pin of the first holding register 11 (ie, the full signal pin) and the Full pin of the first shift register 12, respectively The connection, when the Wfull pin of the first FIFO memory 13 generates a full flag, controls the first holding register 11 and the first shift register 12 to suspend the input of the serial data.
[0064] 进一步地， 当第一先进先出存储器 13采用异步模式吋， 外部电路的 DatalnClk引 脚连通的并行数据的吋钟信号频率 f DataInak、 并行数据位宽 N、 第一先进先出存储 器 13的 Wclk引脚接收的写吋钟信号频率 f wdk之间存在如下关系： [0064] Further, when the first FIFO memory 13 adopts the asynchronous mode 吋 , the clock signal frequency f DataInak of the parallel data connected by the DatalnClk pin of the external circuit, the parallel data bit width N, and the first FIFO memory 13 The following relationship exists between the write cuckoo clock signal frequency f wdk received by the Wclk pin:
[0065] f DatalnClk/f Wclk =N； [0066] 第一先进先出存储器 13的 Wfull弓 I脚分别与第一保持寄存器 11的 Full弓 |脚和第一 移位寄存器 12的 Full弓 I脚连接， 当第一先进先出存储器 13的 Wfull弓 |脚产生满标识 吋， 会控制第一保持寄存器 11和第一移位寄存器 12暂停串行数据的输入， 并标 识第一移位寄存器 12中并转串发生错误。 [0065] f DatalnClk/f Wclk =N; [0066] The Wfull bow of the first FIFO memory 13 is respectively connected to the Full Bow|foot of the first holding register 11 and the Full bow of the first shift register 12, when the first FIFO memory 13 is The Wfull bow|foot generates a full flag, which controls the first holding register 11 and the first shift register 12 to suspend the input of the serial data, and identifies the first shift register 12 and causes an error to be repeated.
[0067] 具体地， 参见图 3， 在串并转换单元 2中， 外部电路的 DATAInValid引脚与第二 先进先出存储器 21的 WCtr引脚电连接， 来控制外部电路中的串行数据写入第二 先进先出存储器 21中， 其中， 外部电路的 DATAIn引脚与第二先进先出存储器 21 的 Wdata弓 I脚电连接， 第二先进先出存储器 21的 WFull弓 |脚与外部电路的 DATAIn Ready弓 |脚电连接， 这样第二先进先出存储器 21通过 WCtr弓 |脚和 WFull弓 |脚来控 制外部电路写入串行数据。 第二先进先出存储器 21的 RData引脚与第二移位寄存 器 22的 Data弓 |脚电连接， 第二移位寄存器 22的 Ready弓 |脚与第二先进先出存储器 2 1的 RCtr弓 I脚电连接， 以控制第二先进先出存储器 21中的串行数据写入第二移位 寄存器 22中。 第二先进先出存储器 21的 REmpty弓 |脚和 Usaging弓 |脚分别与第二移 位寄存器 22的 Empty弓 |脚和 Use弓 |脚电连接， 以控制第二移位寄存器 22将串行数 据转化为并行数据， 其中， Usaging引脚产生的 Uasging信号表示的是第二先进先 出存储器 21中有效数据的 Bit数。 第二保持寄存器 23的 Active弓 |脚和 Ready弓 |脚分 别与外部电路的 DataOutActive弓 |脚和 DataOutReady弓 |脚电连接， 用于控制外部 电路读取第二保持寄存器 23中缓存的并行数据。 此外， 第二先进先出存储器 21 的 RRst引脚 （即读复位引脚） 、 第二移位寄存器 22的 Rst引脚 （即复位引脚） 、 第二保持寄存器 23的 Rst引脚 （即复位引脚） 均与外部电路的 DataRRst引脚电连 接； 第二先进先出存储器 21的 WRst引脚 （即写复位引脚） 与外部电路的 DataWR st引脚电连接。  [0067] Specifically, referring to FIG. 3, in the serial to parallel conversion unit 2, the DATAInValid pin of the external circuit is electrically connected to the WCtr pin of the second FIFO memory 21 to control serial data writing in the external circuit. In the second FIFO memory 21, wherein the DATAIn pin of the external circuit is electrically connected to the Wdata pin of the second FIFO memory 21, the WFull bow of the second FIFO memory 21 and the DATAIn of the external circuit Ready bow | foot electrical connection, so the second FIFO memory 21 through the WCtr bow | foot and WFull bow | foot to control the external circuit to write serial data. The RData pin of the second FIFO memory 21 is electrically coupled to the Data bow of the second shift register 22, the Ready bow of the second shift register 22, and the RCtr of the second FIFO memory 2 The foot is electrically connected to control the serial data in the second FIFO memory 21 to be written in the second shift register 22. The second FIFO memory 21's REmpty bow|foot and the Usaging bow|foot are respectively connected with the second shift register 22's Emptyy|foot and Use bow|foot to control the second shift register 22 to serial data. Converted into parallel data, wherein the Uasging signal generated by the Usaging pin represents the number of bits of valid data in the second FIFO memory 21. The second holding register 23 Active Bow | Foot and Ready Bow | Foot is separated from the external circuit DataOutActive Bow | Foot and DataOutReady Bow | Foot Electrical Connection, used to control the external circuit to read the parallel data in the second holding register 23 cache. In addition, the RRst pin of the second FIFO memory 21 (ie, the read reset pin), the Rst pin of the second shift register 22 (ie, the reset pin), and the Rst pin of the second holding register 23 (ie, reset) The pins are electrically connected to the DataRRst pin of the external circuit; the WRst pin of the second FIFO 21 (ie, the write reset pin) is electrically connected to the DataWR st pin of the external circuit.
[0068] 在本实施例中， 第二先进先出存储器 21的深度可以根据实际需求设定， 这里不 做限制。  In this embodiment, the depth of the second FIFO memory 21 can be set according to actual requirements, and is not limited herein.
[0069] 进一步地， 第二先进先出存储器 21可以采用同步模式或者异步模式工作， 第二 先进先出存储器 21的 Wclk弓 I脚与外部电路中连通写吋钟信号的 DATAWClk弓 |脚 电连接， 第二移位寄存器 22的 elk弓 I脚和第二先进先出存储器 21的 Rclk弓 I脚均与 外部电路中连通读吋钟信号的 DataRClk弓 |脚电连接， 第二保持寄存器 23的 elk弓 | 脚与外部电路中连通并行数据的吋钟信号的 DataOutClk弓 |脚电连接。 [0069] Further, the second FIFO memory 21 can operate in a synchronous mode or an asynchronous mode, and the Wclk bow of the second FIFO memory 21 is electrically connected to the DATAWClk bow of the external circuit in writing the sigma clock signal. The elk bow I of the second shift register 22 and the Rclk pin I of the second FIFO memory 21 are electrically connected to the DataRClk bow of the read clock signal in the external circuit, and the elk of the second hold register 23 Bow| The foot and the external circuit are connected to the DataOutClk bow of the parallel data and the foot is electrically connected.
[0070] 在本实施例中， 第二先进先出存储器 21连通的写吋钟信号与读吋钟信号不同， 当第二先进先出存储器 21采用同步模式吋， 写吋钟信号与读吋钟信号之间存在 关联， 当第二先进先出存储器 21采用异步模式吋， 写吋钟信号与读吋钟信号之 间不存在关联。 [0070] In this embodiment, the write 吋 clock signal communicated by the second FIFO memory 21 is different from the read 吋 clock signal, and when the second FIFO memory 21 is in the synchronous mode 吋, the write 吋 clock signal and the read 吋 clock There is an association between the signals. When the second FIFO memory 21 is in the asynchronous mode, there is no correlation between the write chirp signal and the read chirp signal.
[0071] 进一步地， 当第二先进先出存储器 21采用同步模式吋， 外部电路的 DataOutClk 引脚连通的并行数据的吋钟信号频率 f Data。utClk、 并行数据位宽 N、 第二先进先出 存储器 21的 Wclk引脚接收的写吋钟信号频率 f wdk、 以及第二先进先出存储器 21 的 Rclk弓 I脚接收的读吋钟信号频率 f Rdk之间存在如下关系： [0071] Further, when the second FIFO memory 21 adopts the synchronous mode 吋, the data of the parallel circuit of the external circuit is connected to the clock signal frequency f Data of the parallel data. utClk , parallel data bit width N, write clock signal frequency f wdk received by Wclk pin of second FIFO memory 21, and read chirp signal frequency f received by Rclk pin of second FIFO memory 21 The following relationships exist between Rdk :
[0072] f DataOutClk/f Wclk" f DataOutClk/f Rclk: N。  f DataOutClk/f Wclk" f DataOutClk/f Rclk: N.
[0073] 进一步地， 当第二先进先出存储器 21采用异步模式吋， 外部电路的 DataOutClk 引脚连通的并行数据的吋钟信号频率 f Data。utClk、 并行数据位宽 N、 以及第二先进 先出存储器 21的 Rclk弓 I脚接收的读吋钟信号频率 f Rdk之间存在如下关系： [0073] Further, when the second FIFO memory 21 adopts the asynchronous mode 吋, the data of the parallel circuit of the external circuit is connected to the clock signal frequency f Data of the parallel data. The following relationship exists between utClk , the parallel data bit width N, and the read chirp signal frequency f Rdk received by the Rclk pin I of the second FIFO memory 21:
[0074] f Data0utClk/f Rclk=N。 [0074] f Data0utClk /f Rclk =N.
[0075] 本发明实施例通过第一保持寄存器、 第一移位寄存器、 第一先进先出存储器构 成并串转换单元， 以实现并行数据转化为串行数据， 在第一移位寄存器进行数 据转化吋， 采用第一先进先出存储器构成数据缓冲区， 可以有效简化第一移位 寄存器控制信号的组成， 而且， 第一先进先出存储器可以采用与写吋钟不同的 读吋钟来控制缓存数据的输出， 使得并串转换单元的输入吋钟和输出吋钟可以 处于不同吋钟域， 进而可以克服由于输入吋钟和输出吋钟中存在吋钟偏移吋都 会导致的数据转换错误； 同理， 通过第二先进先出存储器、 第二移位寄存器、 第二保持寄存器构成串并转换单元， 以实现串行数据转化为并行数据， 在第二 移位寄存器进行数据转化吋， 采用第二先进先出存储器构成数据缓冲区， 可以 有效简化第二移位寄存器控制信号的组成， 而且， 第二先进先出存储器可以采 用与写吋钟不同的读吋钟来控制缓存数据的输出， 使得并串转换单元的输入吋 钟和输出吋钟可以处于不同吋钟域， 进而可以克服由于输入吋钟和输出吋钟中 存在吋钟偏移吋都会导致的数据转换错误。  [0075] Embodiments of the present invention form a parallel-to-serial conversion unit by using a first holding register, a first shift register, and a first FIFO memory to convert parallel data into serial data, and perform data conversion in the first shift register.吋, the first FIFO memory is used to form a data buffer, which can effectively simplify the composition of the first shift register control signal, and the first FIFO memory can control the cache data by using a different read clock from the write clock. The output makes the input chirp and output chirp of the parallel-to-serial conversion unit in different clock domains, which can overcome the data conversion error caused by the presence of the clock offset in the input chirp and the output chirp; The second FIFO memory, the second shift register, and the second holding register form a serial-to-parallel conversion unit to convert serial data into parallel data, and perform data conversion in the second shift register, using the second advanced The first-out memory constitutes a data buffer, which can effectively simplify the control signal of the second shift register. Moreover, the second FIFO memory can control the output of the buffer data by using a read clock different from the write clock, so that the input clock and the output clock of the parallel-to-serial conversion unit can be in different clock domains, and thus Overcome data conversion errors caused by the presence of a clock offset in the input cesium and output cesium.
[0076] 上述本发明实施例序号仅仅为了描述， 不代表实施例的优劣。 以上所述仅为本发明的较佳实施例， 并不用以限制本发明， 凡在本发明的精神 和原则之内， 所作的任何修改、 等同替换、 改进等， 均应包含在本发明的保护 范围之内。 [0076] The foregoing serial numbers of the embodiments of the present invention are merely for the description, and do not represent the advantages and disadvantages of the embodiments. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., which are within the spirit and scope of the present invention, should be included in the protection of the present invention. Within the scope.

Claims

权利要求书 Claim
[权利要求 1] 一种用于数据串行传输的并串、 串并转换装置， 其特征在于， 包括： 接收并行数据并将并行数据转换为串行数据输出的并串转换单元 （1 [Claim 1] A parallel-serial, serial-to-parallel conversion apparatus for data serial transmission, comprising: a parallel-to-serial conversion unit that receives parallel data and converts parallel data into serial data output (1)
) ， 和接收串行数据并将串行数据转化为并行数据输出的串并转换单 元 (2) ， ) , and a serial-to-parallel conversion unit (2) that receives serial data and converts the serial data into parallel data output.
所述并串转换单元 （1) 包括：  The parallel-to-serial conversion unit (1) includes:
第一保持寄存器 （11) ， 用于缓存外部电路传输的并行数据； 第一移位寄存器 （12) ， 用于将所述第一保持寄存器 （11) 中缓存的 并行数据转换成串行数据；  a first holding register (11) for buffering parallel data transmitted by the external circuit; a first shift register (12) for converting parallel data buffered in the first holding register (11) into serial data;
第一先进先出存储器 （13) ， 用于缓存所述第一移位寄存器 （12) 生 成的串行数据， 并采用与写吋钟不同的读吋钟来控制缓存数据的输出 所述串并转换单元 （2) 包括：  a first FIFO memory (13) for buffering serial data generated by the first shift register (12), and controlling the output of the buffer data by using a read clock different from the write clock The conversion unit (2) includes:
第二先进先出存储器 （21) ， 用于缓存外部电路传输的串行数据， 并 采用与写吋钟不同的读吋钟来控制缓存数据的输出； 第二移位寄存器 （22) ， 用于将所述第二先进先出存储器 （21) 中缓 存的串行数据转换成并行数据；  a second FIFO memory (21) for buffering serial data transmitted by the external circuit, and using a read clock different from the write clock to control the output of the buffer data; a second shift register (22) for Converting the serial data buffered in the second FIFO memory (21) into parallel data;
第二保持寄存器 （23) ， 用于缓存所述第二移位寄存器 （22) 中生成 的并行数据。  A second holding register (23) for buffering parallel data generated in the second shift register (22).
[权利要求 2] 根据权利要求 1所述的装置， 其特征在于， 在所述并串转换单元 （1) 中， 外部电路的第一引脚 （DatalnValid) 与所述第一保持寄存器 （11 ) 的第一引脚 （Valid) 电连接， 来控制外部电路中的并行数据写入 所述第一保持寄存器 （11) 中； 所述第一移位寄存器 （12) 的第一引 脚 （Valid) 与所述第一先进先出存储器 （13) 的第一引脚 （WCtr) 电连接， 当所述第一移位寄存器 （12) 将并行数据转换成串行数据吋 ， 其第一引脚 （Valid) 会产生写入控制信号， 以控制所述第一先进 先出存储器 （13) 写入串行数据； 当所述第一先进先出存储器 （13) 中写入串行数据吋， 其第二引脚 （REmpty) 和第三引脚 （Usageing ) 分别产生非空信号和 Usageing信号， 所述 Usageing信号表示所述第 一先进先出存储器 （13) 中储存串行数据的 Bit数， 外部电路通过非 空信号和 Usageing信号来控制所述第一先进先出存储器 （13) 中缓存 的串行数据的输出。 [Claim 2] The apparatus according to claim 1, wherein in the parallel-to-serial conversion unit (1), a first pin (DatalnValid) of the external circuit and the first holding register (11) The first pin (Valid) is electrically connected to control parallel data in the external circuit to be written into the first holding register (11); the first pin (Valid) of the first shift register (12) Electrically connected to a first pin (WCtr) of the first FIFO memory (13), when the first shift register (12) converts parallel data into serial data, its first pin ( Valid) a write control signal is generated to control the first FIFO memory (13) to write serial data; when the serial data is written in the first FIFO memory (13), Two pins (REmpty) and third pin (Usageing Generating a non-empty signal and a Usage signal, respectively, the Usageing signal indicating the number of bits storing the serial data in the first FIFO memory (13), and the external circuit controls the first by the non-empty signal and the Usage signal The output of the serial data buffered in the first in first out memory (13).
根据权利要求 2所述的装置， 其特征在于， 所述第一先进先出存储器 ( 13) 采用同步模式或者异步模式工作， 所述第一保持寄存器 （11) 的第二引脚 （elk) 与外部电路中连通并行数据的吋钟信号的第二引 脚 (DatalnClk) 电连接， 所述第一移位寄存器 ( 12) 的第二引脚 (cl k) 和所述第一先进先出存储器 （13) 的第四引脚 （Wclk) 均与外部 电路中连通写吋钟信号的第三引脚 （DataWClk) 电连接， 所述第一 先进先出存储器 （13) 的第五引脚 （Rclk) 与外部电路中连通读吋钟 信号的第三引脚 （DATARClk) 电连接。 The apparatus according to claim 2, wherein said first FIFO memory (13) operates in a synchronous mode or an asynchronous mode, and a second pin (elk) of said first holding register (11) is a second pin (DatalnClk) of the chopping clock signal connecting the parallel data in the external circuit is electrically connected, a second pin (cl k) of the first shift register (12) and the first FIFO memory ( The fourth pin (Wclk) of 13) is electrically connected to a third pin (DataWClk) connected to the write clock signal in the external circuit, and the fifth pin (Rclk) of the first FIFO memory (13) It is electrically connected to the third pin (DATARClk) of the external circuit that is connected to the read chirp signal.
根据权利要求 3所述的装置， 其特征在于， 当所述第一先进先出存储 器 （13) 采用同步模式吋， 外部电路的第二引脚 （DatalnClk) 连通 的并行数据的吋钟信号频率 f DataInak、 并行数据位宽 N、 所述第一先进 先出存储器 （13) 的第四引脚 （Wclk) 接收的写吋钟信号频率1^^、 以及所述第一先进先出存储器 （13) 的第五引脚 （Rclk) 接收的读吋 钟信号频率 f Rdk之间存在如下关系： The apparatus according to claim 3, wherein when said first FIFO memory (13) adopts a synchronization mode 吋, a second signal (DatalnClk) of the external circuit communicates a chirp signal frequency of parallel data f DataInak , parallel data bit width N, write clock signal frequency 1^^ received by the fourth pin (Wclk) of the first FIFO memory (13), and the first FIFO memory (13) The fifth pin (Rclk) receives the following relationship between the read chirp signal frequency f Rdk :
f DatalnClk/f Wclk" f DatalnClk/f Rclk" ； f DatalnClk/f Wclk" f DatalnClk/f Rclk" ;
所述第一先进先出存储器 （13) 的第六引脚 （Wfull) 分别与所述第 一保持寄存器 （11) 的第三引脚 （Full) 和所述第一移位寄存器 （12 ) 的第三引脚 （Full) 连接， 当所述第一先进先出存储器 （13) 的第 六引脚 （Wfull) 产生满标识吋， 会控制所述第一保持寄存器 （11) 和所述第一移位寄存器 （12) 暂停串行数据的输入。 a sixth pin (Wfull) of the first FIFO memory (13) and a third pin (Full) of the first holding register (11) and the first shift register (12), respectively a third pin (Full) connection, when the sixth pin (Wfull) of the first FIFO memory (13) generates a full flag, the first holding register (11) and the first The shift register (12) suspends the input of serial data.
根据权利要求 3所述的装置， 其特征在于， 当所述第一先进先出存储 器 （13) 采用异步模式吋， 外部电路的第二引脚 （DatalnClk) 连通 的并行数据的吋钟信号频率 f DataInClk、 并行数据位宽 N、 所述第一先进 先出存储器 （13) 的第四引脚 （Wclk) 接收的写吋钟信号频率 f wdk之 间存在如下关系： The apparatus according to claim 3, characterized in that, when said first FIFO memory (13) adopts an asynchronous mode 吋, a second signal (DatalnClk) of the external circuit communicates a clock signal frequency of parallel data f DataInClk , parallel data bit width N, write clock signal frequency f wdk received by the fourth pin (Wclk) of the first FIFO memory (13) There are the following relationships:
f DatalnClk/f Wclk" ；  f DatalnClk/f Wclk" ;
所述第一先进先出存储器 （13) 的第六引脚 （Wfull) 分别与所述第 一保持寄存器 （11) 的第三引脚 （Full) 和所述第一移位寄存器 （12 ) 的第三引脚 （Full) 连接， 当所述第一先进先出存储器 （13) 的第 六引脚 （Wfull) 产生满标识吋， 会控制所述第一保持寄存器 （11) 和所述第一移位寄存器 （12) 暂停串行数据的输入， 并标识所述第一 移位寄存器 （12) 中并转串发生错误。  a sixth pin (Wfull) of the first FIFO memory (13) and a third pin (Full) of the first holding register (11) and the first shift register (12), respectively a third pin (Full) connection, when the sixth pin (Wfull) of the first FIFO memory (13) generates a full flag, the first holding register (11) and the first The shift register (12) suspends the input of the serial data and identifies an error in the first shift register (12) and the serial string.
[权利要求 6] 根据权利要求 1所述的装置， 其特征在于， 在所述串并转换单元 （2) 中， 外部电路的第四引脚 （DATAInValid) 与所述第二先进先出存储 器 （21) 的第一引脚 （WCtr) 电连接， 来控制外部电路中的串行数 据写入所述第二先进先出存储器 （21) 中； 所述第二先进先出存储器[Claim 6] The apparatus according to claim 1, wherein in the serial to parallel conversion unit (2), a fourth pin (DATAInValid) of the external circuit and the second FIFO memory ( 21) a first pin (WCtr) electrically connected to control serial data in an external circuit to be written into the second FIFO memory (21); the second FIFO memory
(21) 的第二引脚 （RData) 与所述第二移位寄存器 （22) 的第一引 脚 （Data) 电连接， 所述第二移位寄存器 （22) 的第二引脚 （Ready ) 与所述第二先进先出存储器 （21) 的第三引脚 （RCtr) 电连接， 以 控制所述第二先进先出存储器 （21) 中的串行数据写入所述第二移位 寄存器 （22) 中； 所述第二先进先出存储器 （21) 的第四引脚 （REm pty) 和第五引脚 (Usaging) 分别与所述第二移位寄存器 (22) 的第 三引脚 （Empty) 和第四引脚 （Use) 电连接， 以控制所述第二移位 寄存器 （22) 将串行数据转化为并行数据； 所述第二保持寄存器 （23 ) 的第一引脚 （Active) 和第二引脚 （Ready) 分别与外部电路的第 五引脚 （DataOutActive) 和第六引脚 （DataOutReady) 电连接， 用于 控制外部电路读取所述第二保持寄存器 （23) 中缓存的并行数据。 a second pin (RData) of (21) is electrically coupled to a first pin (Data) of the second shift register (22), and a second pin of the second shift register (22) (Ready Electrically coupled to a third pin (RCtr) of the second FIFO memory (21) to control serial data writes in the second FIFO memory (21) to the second shift a register (22); a fourth pin (REm pty) and a fifth pin (Usaging) of the second FIFO memory (21) and a third lead of the second shift register (22), respectively An (Empty) and a fourth pin (Use) are electrically connected to control the second shift register (22) to convert serial data into parallel data; the first pin of the second holding register (23) (Active) and a second pin (Ready) are electrically connected to a fifth pin (DataOutActive) and a sixth pin (DataOutReady) of the external circuit, respectively, for controlling an external circuit to read the second holding register (23) Parallel data cached in .
[权利要求 7] 根据权利要求 6所述的装置， 其特征在于， 所述第二先进先出存储器 [Clave 7] The apparatus according to claim 6, wherein the second FIFO memory
(21) 采用同步模式或者异步模式工作， 所述第二先进先出存储器 （ 21) 的第六引脚 （Wclk) 与外部电路中连通写吋钟信号的第七引脚 (21) operating in synchronous mode or asynchronous mode, the sixth pin (Wclk) of the second FIFO memory (21) is connected to the external circuit to write the seventh pin of the sigma signal
(DATAWClk) 电连接， 所述第二移位寄存器 （22) 的第五引脚 （cl k) 和所述第二先进先出存储器 （21) 的第七引脚 （Rclk引脚） 均与 外部电路中连通读吋钟信号的第八引脚 （DataRClk) 电连接， 所述第 二保持寄存器 （23) 的第三引脚 （elk) 与外部电路中连通并行数据 的吋钟信号的第九引脚 （DataOutClk) 电连接。 (DATAWClk) electrically connected, the fifth pin (cl k) of the second shift register (22) and the seventh pin (Rclk pin) of the second FIFO memory (21) are both An eighth pin (DataRClk) that connects the read chirp signal in the external circuit is electrically connected, and a third pin (elk) of the second holding register (23) is connected to the ninth of the chirp signal of the parallel data in the external circuit. Pin (DataOutClk) is electrically connected.
[权利要求 8] 根据权利要求 7所述的装置， 其特征在于， 当所述第二先进先出存储 器 （21) 采用同步模式吋， 外部电路的第九引脚 （DataOutClk) 连通 的并行数据的吋钟信号频率 f Data。utak、 并行数据位宽 N、 所述第二先 进先出存储器 （21) 的第六引脚 （Wclk) 接收的写吋钟信号频率 f wdk 、 以及所述第二先进先出存储器 （21) 的第七引脚 （Rclk) 接收的读 吋钟信号频率 f Rdk之间存在如下关系： [Claim 8] The apparatus according to claim 7, wherein when the second FIFO memory (21) adopts a synchronous mode, the ninth pin (DataOutClk) of the external circuit is connected to the parallel data. Cuckoo clock signal frequency f Data . Utak , parallel data bit width N, write clock signal frequency f wdk received by the sixth pin (Wclk) of the second FIFO memory (21), and the second FIFO memory (21) The seventh pin (Rclk) receives the following relationship between the read chirp signal frequency f Rdk :
f DataOutCl kk/'f 1 Wclk—丄 f DataOutClkk' ^f RRccllkk"— N° f DataOutCl k k/'f 1 Wclk—丄f DataOutClkk' ^f RRccllkk"— N°
[权利要求 9] 根据权利要求 7所述的装置， 其特征在于， 当所述第二先进先出存储 器 （21) 采用异步模式吋， 外部电路的第九引脚 （DataOutClk) 连通 的并行数据的吋钟信号频率 f Data。utak、 并行数据位宽 N、 以及所述第 二先进先出存储器 （21) 的第七引脚 （Rclk) 接收的读吋钟信号频率 f Rdk之间存在如下关系： [Claim 9] The apparatus according to claim 7, wherein when the second FIFO memory (21) adopts an asynchronous mode, the ninth pin (DataOutClk) of the external circuit is connected to the parallel data. Cuckoo clock signal frequency f Data . The following relationship exists between utak , the parallel data bit width N, and the read chirp signal frequency f Rdk received by the seventh pin (Rclk) of the second FIFO memory (21):
f DataOutClk' /f =N。  f DataOutClk' /f =N.
PCT/CN2016/078628 2016-04-07 2016-04-07 Device for data transmission mode conversions WO2017173608A1 (en)

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