CN102956708A - 屏蔽栅极沟槽mosfet封装 - Google Patents
屏蔽栅极沟槽mosfet封装 Download PDFInfo
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- CN102956708A CN102956708A CN2012102869474A CN201210286947A CN102956708A CN 102956708 A CN102956708 A CN 102956708A CN 2012102869474 A CN2012102869474 A CN 2012102869474A CN 201210286947 A CN201210286947 A CN 201210286947A CN 102956708 A CN102956708 A CN 102956708A
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Abstract
一种屏蔽栅沟槽场效应晶体管可以形成在衬底上,具有一个外延层在衬底上,以及一个本体层在外延层上。形成在本体层和外延层中的沟槽,内衬电介质层。屏蔽电极形成在沟槽下部。通过电介质层使屏蔽电极绝缘。栅极电极形成在屏蔽电极上方的沟槽中,并通过额外的电介质层,与屏蔽电极绝缘。一个或多个源极区形成在本体层中,位于沟槽的侧壁附近。源极垫形成在本体层上方,电连接到一个或多个源极区,并与栅极电极和屏蔽电极绝缘。源极垫提供到源极区的外部接头。栅极垫提供到栅极电极的外部接头。屏蔽电极垫提供到屏蔽电极的外部接头。电阻元件可以电连接在封装中的屏蔽电极垫和源极引线之间。
Description
技术领域
本发明是涉及半导体功率场效应晶体管封装,尤其是带有改良反向恢复电流的屏蔽栅极沟槽MOSFET封装。
背景技术
由于屏蔽栅极沟槽MOSFET具有许多优良的性能,因此在一些应用中,它比传统的MOSFET和传统的沟槽MOSFET更具有优势。屏蔽栅沟槽MOSFET降低了晶体管的栅漏电容Cgd,减小了导通电阻RDSon,并且提高了击穿电压。对于传统的沟槽MOSFET而言,在一个通道中放置多个沟槽,在减小导通电阻的同时,也增大了整体的栅漏电容。引入屏蔽栅沟槽MOSFET结构可以修正该问题,通过使栅极与漏极区中的电场隔离,从而大幅降低了栅漏电容。屏蔽栅沟槽MOSFET结构还具有漏极区中少子浓度较高的附加优势,有利于器件的击穿电压,从而降低了导通电阻。
屏蔽栅沟槽MOSFET的改良型性能特点,使其非常适用于开关转换器(通常称为同步降压转换器(DC-DC转换器))等功率开关器件。屏蔽栅沟槽MOSFET尤其适用于同步降压转换器中的高端开关。然而,对于用作同步整流器的低端开关,体二极管反向恢复时过量的电荷,会导致功率耗散增大,转换效率降低。
正是在这一前提下,提出了本发明所述的实施例。
发明内容
本发明提供一种屏蔽栅场效应晶体管,包括:
a)一个第一导电类型的衬底;
b)一个第一导电类型的外延层,位于衬底的上方;
c)一个第二导电类型的本体区,形成在外延层上方,第二导电类型与第一导电类型相反;
d)一个形成在本体层和外延层中的沟槽,其中电介质层内衬沟槽;
e)一个形成在沟槽下部的屏蔽电极,其中通过电介质层,屏蔽电极与外延层绝缘;
f)一个形成在屏蔽电极上方的栅极电极,其中通过额外的电介质层,栅极电极与屏蔽电极绝缘;
g)一个或多个第一导电类型的源极区,形成在本体层的顶面内,其中每个源极区都靠近沟槽侧壁;
h)一个形成在本体层上方的源极垫,其中源极垫电连接到所述的一个或多个源极区,并与栅极电极和屏蔽电极绝缘,源极垫提供到源极区的外部接头;
i)一个形成在本体层上方的栅极垫,其中栅极垫电连接到栅极电极,并与所述的一个或多个源极区和屏蔽电极绝缘,栅极垫提供到栅极电极的外部接头;以及
j)一个形成在本体层上方的屏蔽垫,其中屏蔽垫电连接到屏蔽电极,并与所述的一个或多个源极区和栅极电极绝缘,屏蔽垫提供到屏蔽电极的外部接头。
上述的屏蔽栅场效应晶体管,还包括:k)一个块状电阻元件,在一个封装中,该块状电阻元件具有的一个末端连接屏蔽垫,另一个末端连接源极引线。
上述的屏蔽栅场效应晶体管,所述块状电阻元件为一金属层。
上述的屏蔽栅场效应晶体管,所述块状电阻元件为一掺杂的多晶硅层。
上述的屏蔽栅场效应晶体管,还包括一个内部电阻元件,在一个封装中,该块状电阻元件具有的一个末端电连接到屏蔽电极,另一个末端电连接到一屏蔽引线。
上述的屏蔽栅场效应晶体管,所述内部电阻元件为一个块状电阻,包括屏蔽电极中的多晶硅。
上述的屏蔽栅场效应晶体管,所述的衬底为n+掺杂,所述的外延层为n型外延层,所述的本体区为p掺杂,所述的源极区为n+掺杂。
上述的屏蔽栅场效应晶体管,所述的屏蔽电极电连接到位于两个有源区之间的一个屏蔽电极连接区,其中所述的屏蔽电极连接区包括数个屏蔽电极拾取沟槽,每个屏蔽电极拾取沟槽都带有一个屏蔽电极拾取接头。
上述的屏蔽栅场效应晶体管,利用掺杂多晶硅配置块状电阻,填充屏蔽电极拾取沟槽。
上述的屏蔽栅场效应晶体管,块状电阻位于围绕所述的两个有源区中的一个或多个的一个终接沟槽(termination trench)的外面。
上述的屏蔽栅场效应晶体管,屏蔽电极拾取接头形成在两个有源区中的一个或多个周围的一个终接区(termination region)里面。
在一种实施方式中,一种屏蔽栅场效应晶体管包括:第一和第二有源晶体管区;一个屏蔽电极接触区,位于两个有源晶体管区之间,其中屏蔽电极接触区包括多个屏蔽电极拾取沟槽,每个屏蔽电极拾取沟槽都含有一个屏蔽电极接头;以及一个屏蔽电极,电连接到屏蔽电极接触区。
此外,本发明还提供一种用于制备屏蔽栅沟槽场效应晶体管的方法,包括步骤:
a)在第一导电类型的衬底上方,制备一个第一导电类型的外延层;
b)在外延层上,制备一个第二导电类型的本体层;
c)在本体层和外延层中,制备一个沟槽,其中用电介质层内衬沟槽;
d)在沟槽的下部制备一个屏蔽电极,其中通过电介质层,屏蔽电极与外延层绝缘;
e)在沟槽内屏蔽电极上方,制备一个栅极电极,其中通过额外的电介质层,栅极电极与屏蔽电极绝缘;
f)在本体层的顶面内,制备一个或多个第一导电类型的源极区,其中每个源极区都位于沟槽的侧壁附近;
g)在本体层上方制备一个源极垫,其中源极垫电连接到所述的一个或多个源极区,并与栅极电极和屏蔽电极绝缘,源极垫提供到源极区的外部接头;
h)在本体层上方,制备一个栅极垫,其中栅极垫电连接到一个或多个栅极区,并与所述的一个或多个源极区和屏蔽电极绝缘,栅极垫提供到栅极电极的外部接头;并且
i)在本体层上方,制备一个屏蔽垫,其中屏蔽垫电连接到一个或多个屏蔽电极,并与所述的一个或多个源极区和栅极电极绝缘,屏蔽垫提供到屏蔽电极的外部接头。
上述的方法,还包括在屏蔽垫和一个源极引线之间,制备一个电阻元件,源极引线电连接到所述的一个或多个源极区。
上述的方法,在屏蔽垫和源极引线之间,制备一个电阻元件,包括将块状电阻置于封装中的屏蔽垫和源极引线之间。
上述的方法,还包括在屏蔽电极和屏蔽垫之间,制备一个内部电阻元件。
上述的方法,内部电阻是一个块状电阻,包含形成屏蔽电极或栅极电极的多晶硅。
上述的方法,屏蔽电极电连接到位于两个有源区之间的屏蔽电极接触区,其中屏蔽电极接触区包括多个屏蔽电极拾取沟槽,每个屏蔽电极拾取沟槽都具有一个屏蔽电极接头。
上述的方法,利用掺杂多晶硅配置块状电阻,填充屏蔽电极拾取沟槽。
上述的方法,块状电阻的电阻值由屏蔽电极拾取沟槽的长度和/或宽度决定,并且可以通过改变接头的数量来调节。
上述的方法,选取屏蔽电极拾取沟槽的数量,以满足所需的块状电阻的要求。
附图说明
阅读以下详细说明并参照附图之后,本发明的其他特点和优势将显而易见:
图1表示一种DC-DC降压转换器的电路图。
图2表示图1所示的DC-DC降压转换器的反向恢复动作的示意图。
图3表示一种屏蔽栅沟槽MOSFET的剖面示意图,电容器元件代表各寄生电容的来源。
图4A和4B表示依据本发明的一个较佳实施例,一种屏蔽栅沟槽MOSFET的剖面图和俯视图。
图5A-5H表示依据本发明的一个实施例,一种屏蔽栅沟槽MOSFET器件的制备方法的剖面示意图。
图6表示一种屏蔽栅沟槽MOSFET器件布局的俯视图,其中内部电阻器形成在两个有源零件之间的屏蔽电极中。
图7表示一种屏蔽栅沟槽MOSFET器件布局的俯视图,其中内部电阻器形成在屏蔽电极拾取区中,击穿电压(BV)由间距决定。
具体实施方式
以下详细说明并参照附图,用于解释说明本发明的典型实施例。在这种情况下,参照图中所示的方向,使用方向术语,例如“顶部”、“底部”、“正面”、“背面”、“前面”、“后面”等。由于本发明的实施例可以置于不同的方向上,因此所述的方向术语用于解释说明,并不作为局限。应明确也可以使用其他实施例,结构或逻辑上的调整不能偏离本发明的范围。因此,以下详细说明并不作为局限,本发明的范围应由所附的权利要求书限定。
为了简便,在电荷载流子类型(p或n)或导电类型的后面使用+或-,通常指半导体材料中指定类型的电荷载流子浓度的相对程度。一般来说,n+材料的负电荷载流子(例如电子)的浓度高于n材料,n材料的载流子浓度高于n-材料。同样地,p+材料的正电荷载流子(例如空穴)浓度高于p材料,p材料的载流子浓度高于p-材料。需注意的是,关键是电荷载流子的浓度,而不一定是掺杂物的。例如,一种材料可以重掺杂n-型掺杂物,但如果该材料也大量反掺杂p-型掺杂物,那么它仍然可以具有很低的电荷载流子浓度。文中所述的掺杂物浓度小于1016/cm3称为“轻掺杂”,掺杂物浓度大于1017/cm3称为“重掺杂”。
引言:当MOSFET器件的体二极管正向偏置时,在漂流区中形成少数载流子电荷,使电流流经源极区和漏极区之间。二极管反向恢复是指除去储存在漂流区中的少数载流子电荷的过程,使MOSFET器件的体二极管从正向偏置转换为反向偏置。对于屏蔽栅沟槽MOSFET来说,反向恢复动作对于屏蔽电极中的位移电流非常有利。位移电流是形成在屏蔽电极和漂流区之间的电容器的产物。与屏蔽位移电流有关的电荷数量,可以与二极管的反向恢复电流预计电荷的数量相比拟。因为对整体反向恢复电荷的任何缩减,都会被屏蔽电极对该电荷的贡献所抵消,因此使用集成的肖特基二极管对MOSFET的反向恢复动作只有很少的帮助。本发明的实施例解决了上述问题,同时使MOSFET器件更加灵活,在同步降压转换器中既可以用于的高端开关,也可以用于低端开关。
图1表示同步降压转换器100的电路图。降压转换器100包括一个高端开关101和一个低端开关103,两者都作为MOSFET器件。高端开关101连接在电压源Vcc和电感器105之间。低端开关103连接在电感器105和地之间。由高端开关101和低端开关103的各自栅极电极上所加的电压,驱动它们的开关动作。
如上所述,反向恢复电流增大,会降低降压转换器100的效率,从而削弱低端开关103的性能。在降压转换器100的开关循环中,低端开关103开启,同时高端开关101断开。当低端开关103断开后,在高端开关101开启前,必须有一段时滞,确保不会出现跨导。低端开关103和高端开关101都断开的这段时间称为“停滞时间”,用于使跨导产生的损耗最小化。低端MOSFET的体二极管在停顿时间内正向偏置。低端开关103的反向恢复电流(例如位移电流)的增大,会增加低端开关103恢复到其非传导状态时所需的恢复时间。当高端开关101在停顿时间的最后开启时,由于恢复电流增大,低端开关103处过量的恢复电荷反馈回高端开关101,产生能量损耗。
图2模拟的是一种典型的屏蔽栅沟槽MOSFET反向恢复。电流与时间的关系图200表示反向恢复电流202在1.16微秒(1.16×10-6)附近开始。在将屏蔽栅沟槽MOSFET恢复至其非传导状态时,MOSFET会出现一种称为相节点电压过冲/振荡的现象。这使得MOSFET器件电流在达到其非传导状态之前,会经历多种振荡。当屏蔽栅沟槽MOSFET从正向到反向偏置时,漂流区中电压转换会在屏蔽电极构成的电容器中产生位移电流。由于屏蔽电极连接到源极,因此在反向恢复时,屏蔽电极引入的位移电流对整体电流有贡献。位移电流占整体反向恢复电流的比例超过50%。因此,要大幅改善降压转换器的反向恢复动作,必须修改屏蔽栅沟槽MOSFET,以减小位移电流。
图3表示相关的寄生电容的来源。图3表示屏蔽栅沟槽MOSFET的剖面示意图。文中所述的其他图中所示零件的相关面积和尺寸并不反应真实面积,仅用于解释说明。
屏蔽栅沟槽MOSFET 300包括一个n+型衬底301(例如硅),作为MOSFET 300的漏极。N-型外延区303,也称为漂流区,连接到衬底301。外延区和衬底可以掺杂任何适宜的n-型掺杂物(离子或原子)(例如磷)。P-型本体区305连接到漂流区303,构成MOSFET 300的本体。本体区可以掺杂任何适宜的p-型掺杂物(例如硼)。
沟槽307形成在本体区305和漂流/外延区303中。电介质材料309(例如氧化硅)内衬沟槽307。由多晶硅构成的屏蔽电极311,沉积在沟槽307中。栅极电极313也是由多晶硅构成,沉积在沟槽307中。栅极电极313和屏蔽电极311与相邻区域绝缘,并且通过电介质材料309(例如氧化硅)相互绝缘。
一对n+源极区315形成在本体区305的顶层中。当栅极电极313上加载正电压时,MOSFET器件300开启,在本体区305中,沿沟槽307的侧壁,在源极315和漂流/外延区303之间的本体区305中,垂直形成一个传导通道。
MOSFET 300的整体寄生电容可以分为三个部分:漏极和源极之间的漂流区电容CDS、漏极和屏蔽电极之间的重叠电容CDsh、以及屏蔽电极和栅极电极之间的重叠电容CshG。屏蔽电极311屏蔽栅极电极313,不会与漂流/外延区303有任何实质的重叠,从而大幅降低栅漏重叠电容。
如上所述,参见图2,位移电流(即反向恢复电流的主要来源)是由储存在电容器中的电荷产生的,电容器是通过漏极-屏蔽电容,由屏蔽电极311构成的。因此,降低屏蔽电极处的位移电流,可以有效减少MOSFET器件开关时发生的过冲/振荡现象。
原有技术器件都是通过尝试在屏蔽电极和源极电极之间的MOSFET中引入一个电阻器,减小屏蔽电极处的位移电流。在屏蔽和源极之间增加连接一个电阻元件,可以在开关时当漏极电压转移到静态时,降低屏蔽位移电流。电阻元件和屏蔽电极电容器一起作为一个缓冲电路,缓解相节点振荡/过冲。
虽然原有技术器件通过削弱相节点电压过冲/振荡的效果,改善反向恢复动作,有效地降低了位移电流,但是这都是在应用-应用的基础上。否则,所述的原有技术器件,例如在屏蔽电极和源极之间配置一个内部固定的电阻元件的器件,就无法灵活地调节电阻值。就这点来说,每个特殊的屏蔽栅沟槽MOSFET器件都需要特殊的应用,这种应用无法用于其他应用。
图4A和4B表示依据本发明的一个实施例,一种屏蔽栅沟槽MOSFET器件的剖面图和俯视图。MOSFET器件400从第一导电类型的衬底401开始。衬底可以重掺杂适宜的掺杂物类型。作为示例,但不作为局限,衬底可以为n+衬底,例如硅。衬底401作为屏蔽栅沟槽MOSFET器件400的漏极。
第一导电类型的外延/漂流层403由衬底401承载。作为示例,但不作为局限,外延/漂流层403可以为n-型。第二导电类型的本体层405形成在外延/漂流层403上方。
然后,在本体层405和外延/漂流层403中,形成沟槽407。沟槽内衬电介质材料409,例如氧化硅。屏蔽电极411形成在沟槽407的底部中。作为示例,但不作为局限,屏蔽电极411可以由多晶硅或其他任何导电材料构成。通过内衬在沟槽407中的电介质材料409,屏蔽电极411与外延/漂流层403绝缘。栅极电极413形成在屏蔽电极411上方的沟槽407中。通过电介质材料409,栅极电极413与屏蔽电极411绝缘。
虽然所述的屏蔽电极411和栅极电极413位于沟槽407中的特定位置上,但是要注意的是,屏蔽电极411和栅极电极413可以沿着与图4A中的横截面垂直的方向延伸,并且在外延/漂流层403和本体层405中也可以垂直延伸,以便于形成外部接头。
在本体层405中沟槽415的侧壁附近,制备一对源极区415。源极区可以重掺杂与衬底401和外延/漂流层403的导电类型相同的掺杂物。作为示例,但不作为局限,对于n+型衬底401而言,这些源极区415可以掺杂n+型。如上所述,沟槽屏蔽栅MOSFET器件400的运行方式为:当栅极电极413上加载正电压时,MOSFET器件400开启,在源极415和外延/漂流区403之间的本体区405中,沿沟槽407的侧壁,垂直构成一个传导通道。
金属垫417、419、421沉积在本体层405上方,为源极区415、栅极电极413以及屏蔽电极411提供外部接头。金属垫417作为源极垫,提供连接到屏蔽栅沟槽MOSFET器件400的源极区415的外部接头。源极垫417与栅极电极413和屏蔽电极411绝缘。金属垫419作为栅极垫,提供到栅极电极413的电连接。栅极垫与屏蔽电极411和源极区415绝缘。金属垫421作为屏蔽垫,提供到屏蔽电极411的电连接。如上所述,栅极电极413和屏蔽电极411可以沿着与图4A中的横截面垂直的方向延伸,也可以垂直穿过外延/漂流层403和本体层405,以便与它们各自的金属垫419、421构成电接触。
为了减轻屏蔽栅沟槽MOSFET器件400不必要的反向恢复动作,可以选择在封装中在屏蔽垫421和引线框架的屏蔽引线/引脚425之间,外部连接一个电阻元件423。外部电阻元件423与原有技术器件的固定的内部电阻元件相比,同样也可以改善反向恢复。也就是说,在屏蔽电极411和源极之间增加一个电阻元件423,以便当漏极电压在开关时转移到静态时,阻止屏蔽位移电流。根据漏极401处电势的升高,而使整个屏蔽电介质409上的电容器产生的小电荷,电阻元件423使屏蔽电极411上的电压增大。屏蔽电极411上的感应电势的结果是使屏蔽电极411处的电压随外延/漂流层403中的电压变化而变化,从而减小了屏蔽电极411和漏极401之间的差分电压。因此,漏极-屏蔽电容器处的差分电压降低,屏蔽电极411整体的位移电流也减小。屏蔽电极处外延电流的减小,有助于使DC-DC开关器件中发生的相节点电压过冲/振荡最小。
通过将电阻元件423外部连接到屏蔽栅沟槽MOSFET器件400,而不是内部连接,使MOSFET器件400更加灵活。例如,MOSFET器件400的反向恢复动作可以根据特殊应用来调节。对于需要最小相节点电压过冲/振荡的应用,可以使用阻值较高的电阻元件423。对于相节点电压过冲/振荡不会影响器件性能的应用,屏蔽垫421可以直接短接至源极引线。这种灵活性在DC-DC降压转换器中格外有用,参见上述图1。在该特殊应用中,高端开关101在最小的程度上受到MOSFET器件的反向恢复动作的影响,而低端开关103在最大的程度上受到MOSFET器件的反向恢复动作的影响。与图4A和4B所示相同的MOSFET器件可以用于高端开关101和低端开关103,带有一个连接到低端开关103的额外的外部电阻元件,使相节点电压过冲/振荡达到最小。本发明所述的屏蔽栅沟槽MOSFET通过简单地调节外部电阻元件适应特殊应用,使同一个MOSFET可以用于各种应用,而不是必须为适应每个开关或不同的应用,设计一个不同的MOSFET器件。
外部电阻元件423可以用不同的方式配置。电阻元件423可以仅仅配置成一个简单的外部电阻器。电阻元件423也可以配置成一个金属层。当电阻元件423配置成一个金属层时,电阻率分布在整个金属层上。电阻元件423也可以配置成一个掺杂的多晶硅层。掺杂的多晶硅层的电阻率可以分布在整个掺杂多晶硅层上。
除了将一个外部电阻元件423连接在屏蔽垫421和屏蔽引线425之间,还可以在MOSFET器件中配置一个内部电阻元件(图中没有表示出),用于特定的应用。作为示例,但不作为局限,构成栅极电极413的多晶硅可以用作屏蔽电极411和屏蔽引线425之间的集中电阻器。再次作为示例,但不作为局限,构成屏蔽电极411的多晶硅也可以用作屏蔽电极411和屏蔽引线425之间的集中电阻器。
可以使用各种不同的工艺,制备上述图4A和图4B所示类型的MOSFET器件。作为示例,但不作为局限,于2010年3月11日存档的美国专利申请号12/722,384的专利中所述的工艺,可以用于制备图4A和4B所示类型的器件,特此引用以作参考。
图5A-5G表示用于制备图4A和4B所述的屏蔽栅沟槽MOSFET器件的方法。虽然说明和附图仅仅针对图4A和图4B所示类型的屏蔽栅沟槽MOSFET器件,但是本领域的技术人员应明确,只要包含或省略标准的制备工艺,该制备方法就可以轻松适用于上述任何一种屏蔽栅沟槽MOSFET器件。
屏蔽栅沟槽MOSFET 500的制备从第一导电类型的衬底501开始,如图5A所示,衬底501承载着与衬底501导电类型相同的外延/漂流层503。作为示例,但不作为局限,衬底501可以是n+型衬底,例如硅晶圆。外延/漂流层503可以生长在衬底501上方,并且可以是n型外延/漂流层503。衬底501构成MOSFET器件500的漏极。
然后如图5B所示,在外延/漂流层503上方,离子植入第二导电类型的本体层505。作为示例,本体层505可以是p型本体层505。利用离子植入掺杂本体层505,随后扩散,获得所需的掺杂浓度。本体层505在MOSFET器件的源极和漏极之间,当器件开启时,用作传导通道。
如图5C所示,然后在本体层505和外延/漂流层503中,形成一个沟槽507。利用硬掩膜(掩膜没有显示出),刻蚀沟槽507到一定深度,使沟槽507的底部位于外延/漂流层503中。沿沟槽507的侧壁,沉积或生长一个电介质层509。
如图5D所示,在沟槽507中制备一个屏蔽电极511。作为示例,但不作为局限,屏蔽电极511可以由多晶硅或任何其他导电材料构成。虽然没有表示出,但是要注意的是,屏蔽电极511可以沿着与图5A-5G中的横截面垂直的方向延伸,并且在外延/漂流层503和本体层505中也可以垂直延伸,以便于形成外部接头。
在沟槽507中制备一个栅极电极513,如图5E所示,使栅极电极513与屏蔽电极511绝缘。作为示例,但不作为局限,栅极电极513可以由多晶硅或任何其他导电材料构成。虽然没有表示出,但是要注意的是,栅极电极513可以沿着与图5A-5G中的横截面垂直的方向延伸,并且在外延/漂流层503和本体层505中也可以垂直延伸,以便于形成外部接头。为了绝缘,可以在栅极电极513上方,制备另一个电介质层。
然后如图5F所示,进行带掩膜的植入(掩膜没有显示出),制备一个或多个第一导电类型的源极区515。作为示例,但不作为局限,植入后进行扩散,以获得所需的掺杂浓度。源极区515形成在沟槽507侧壁附近的本体层505的顶面中。作为示例,但不作为局限,对于n+型衬底501来说,源极区505可以是n+源极区。
然后,利用金属掩膜(图中没有表示出),在本体层505上方形成金属垫,以便外部连接到源极区515、栅极电极513以及屏蔽电极511。屏蔽栅沟槽MOSFET器件500的剖面图和俯视图请分别参照图5G和图5H。源极垫517作为MOSFET器件500的源极区515的外部接头。源极垫517与屏蔽电极511和栅极电极513绝缘。栅极垫519作为栅极电极513的外部接头。栅极垫519与屏蔽电极511和源极区515绝缘。屏蔽垫521作为屏蔽电极511的外部接头。屏蔽垫521与栅极电极513和源极区515绝缘。
如图5H所示,可以在屏蔽垫521和封装中引线框架的源极引线/引脚525之间,连接一个外部电阻元件523,以便改善器件反向恢复动作。作为示例,但不作为局限,外部电阻元件523可以作为一个简单的外部电阻,其为金属层时其中电阻率分布在整个金属层上,或为掺杂的多晶硅层,其中如上所述,电阻率分布在整个掺杂的多晶硅层上。
虽然没有详细说明,但是屏蔽栅沟槽MOSFET器件500还可以含有一个内部电阻,在屏蔽电极511和屏蔽引线525之间。作为示例,但不作为局限,可以利用构成栅极电极513的多晶硅配置内部电阻。再次作为示例,但不作为局限,可以利用构成屏蔽电极511的多晶硅配置内部电阻。本领域的技术人员应明确,这种制备方法可以轻松用于包含额外的标准处理工艺的内部电阻元件。
依据本发明的另一个实施例,内部电阻可以形成在屏蔽电极拾取沟槽(Shield electrode pickup trenches,或称作屏蔽电极导出沟槽)中,屏蔽电极拾取沟槽位于两个有源区之间,如图6所示,图6表示屏蔽栅沟槽MOSFET 600布局的俯视图。在本图中,屏蔽电极连接区602位于两个有源区601之间。屏蔽电极拾取沟槽604中的每个屏蔽电极拾取接头(或称导出接头)606都形成在每个沟槽604中。可以利用重掺杂多晶硅配置块状电阻,填充屏蔽电极拾取沟槽604。因此,块状电阻位于一个或多个两个有源区601周围的终接沟槽608以外。电阻值由屏蔽电极拾取沟槽的长度和/或宽度决定,并可以通过改变接头的数量调节电阻值。可以选取屏蔽电极拾取沟槽中的接头,使屏蔽电极拾取沟槽的数量满足块状电阻目标值的要求。在屏蔽电极拾取沟槽中制备内部电阻不需要任何额外的掩膜和处理工艺。
图7表示依据本发明的一个可选实施例,一种屏蔽栅沟槽MOSFET 700的布局俯视图。如图所示,块状电阻器可以形成在屏蔽电极拾取区中,其击穿电压由沟槽间距决定。屏蔽电极拾取区可以被布局在位于晶片的中心,或晶片的边缘处。如图所示,屏蔽电极连接区702位于两个有源区701之间。利用重掺杂多晶硅配置块状电阻,填充屏蔽电极拾取沟槽704。在本实施例中,屏蔽电极拾取接头形成在一个或多个两个有源区701周围的终接区中(图中没有表示出)。在屏蔽电极拾取沟槽中制备内部电阻不需要任何额外的掩膜和处理工艺。
尽管以上是本发明的较佳实施例的完整说明,但是也有可能使用各种可选、修正和等效方案。因此,本发明的范围不应局限于以上说明,而应由所附的权利要求书及其全部等效内容决定。任何可选件(无论首选与否),都可与其他任何可选件(无论首选与否)组合。在以下权利要求中,不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。除非在特定的权利要求前使用“意思是”明确限定,否则所附的权利要求书不应认为是意思加功能的局限。任何没有用“意思是”明确指出限定功能的项目,不应认为是35 USC § 112, ? 6中所述条款的“意思”或“步骤”。
Claims (21)
1.一种屏蔽栅场效应晶体管,其特征在于,包括:
a)一个第一导电类型的衬底;
b)一个第一导电类型的外延层,位于衬底的上方;
c)一个第二导电类型的本体区,形成在外延层上方,第二导电类型与第一导电类型相反;
d)一个形成在本体层和外延层中的沟槽,其中电介质层内衬沟槽;
e)一个形成在沟槽下部的屏蔽电极,其中通过电介质层,屏蔽电极与外延层绝缘;
f)一个形成在屏蔽电极上方的栅极电极,其中通过额外的电介质层,栅极电极与屏蔽电极绝缘;
g)一个或多个第一导电类型的源极区,形成在本体层的顶面内,其中每个源极区都靠近沟槽侧壁;
h)一个形成在本体层上方的源极垫,其中源极垫电连接到所述的一个或多个源极区,并与栅极电极和屏蔽电极绝缘,源极垫提供到源极区的外部接头;
i)一个形成在本体层上方的栅极垫,其中栅极垫电连接到栅极电极,并与所述的一个或多个源极区和屏蔽电极绝缘,栅极垫提供到栅极电极的外部接头;以及
j)一个形成在本体层上方的屏蔽垫,其中屏蔽垫电连接到屏蔽电极,并与所述的一个或多个源极区和栅极电极绝缘,屏蔽垫提供到屏蔽电极的外部接头。
2.如权利要求1所述的屏蔽栅场效应晶体管,其特征在于,还包括:k)一个块状电阻元件,在一个封装中,该块状电阻元件具有的一个末端连接屏蔽垫,另一个末端连接源极引线。
3.如权利要求2所述的屏蔽栅场效应晶体管,其特征在于,所述块状电阻元件为一金属层。
4.如权利要求2所述的屏蔽栅场效应晶体管,其特征在于,所述块状电阻元件为一掺杂的多晶硅层。
5.如权利要求1所述的屏蔽栅场效应晶体管,其特征在于,还包括一个内部电阻元件,在一个封装中,该块状电阻元件具有的一个末端电连接到屏蔽电极,另一个末端电连接到一屏蔽引线。
6.如权利要求5所述的屏蔽栅场效应晶体管,其特征在于,所述内部电阻元件为一个块状电阻,包括屏蔽电极中的多晶硅。
7.如权利要求1所述的屏蔽栅场效应晶体管,其特征在于,所述的衬底为n+掺杂,所述的外延层为n型外延层,所述的本体区为p掺杂,所述的源极区为n+掺杂。
8.如权利要求1所述的屏蔽栅场效应晶体管,其特征在于,所述的屏蔽电极电连接到位于两个有源区之间的一个屏蔽电极连接区,其中所述的屏蔽电极连接区包括数个屏蔽电极拾取沟槽,每个屏蔽电极拾取沟槽都带有一个屏蔽电极拾取接头。
9.如权利要求8所述的屏蔽栅场效应晶体管,其特征在于,利用掺杂多晶硅配置块状电阻,填充屏蔽电极拾取沟槽。
10.如权利要求8所述的屏蔽栅场效应晶体管,其特征在于,块状电阻位于围绕所述的两个有源区中的一个或多个的一个终接沟槽的外面。
11.如权利要求8所述的屏蔽栅场效应晶体管,其特征在于,屏蔽电极拾取接头形成在两个有源区中的一个或多个周围的一个终接区里面。
12.一种屏蔽栅场效应晶体管,其特征在于,包括:
第一和第二有源晶体管区;
一个屏蔽电极接触区,位于两个有源晶体管区之间,其中屏蔽电极接触区包括多个屏蔽电极拾取沟槽,每个屏蔽电极拾取沟槽都含有一个屏蔽电极接头;以及
一个屏蔽电极,电连接到屏蔽电极接触区。
13.一种用于制备屏蔽栅沟槽场效应晶体管的方法,其特征在于,包括:
a)在第一导电类型的衬底上方,制备一个第一导电类型的外延层;
b)在外延层上,制备一个第二导电类型的本体层;
c)在本体层和外延层中,制备一个沟槽,其中用电介质层内衬沟槽;
d)在沟槽的下部制备一个屏蔽电极,其中通过电介质层,屏蔽电极与外延层绝缘;
e)在沟槽内屏蔽电极上方,制备一个栅极电极,其中通过额外的电介质层,栅极电极与屏蔽电极绝缘;
f)在本体层的顶面内,制备一个或多个第一导电类型的源极区,其中每个源极区都位于沟槽的侧壁附近;
g)在本体层上方制备一个源极垫,其中源极垫电连接到所述的一个或多个源极区,并与栅极电极和屏蔽电极绝缘,源极垫提供到源极区的外部接头;
h)在本体层上方,制备一个栅极垫,其中栅极垫电连接到一个或多个栅极区,并与所述的一个或多个源极区和屏蔽电极绝缘,栅极垫提供到栅极电极的外部接头;并且
i)在本体层上方,制备一个屏蔽垫,其中屏蔽垫电连接到一个或多个屏蔽电极,并与所述的一个或多个源极区和栅极电极绝缘,屏蔽垫提供到屏蔽电极的外部接头。
14.权利要求13所述的方法,其特征在于,还包括在屏蔽垫和一个源极引线之间,制备一个电阻元件,源极引线电连接到所述的一个或多个源极区。
15.如权利要求14所述的方法,其特征在于,在屏蔽垫和源极引线之间,制备一个电阻元件,包括将块状电阻置于封装中的屏蔽垫和源极引线之间。
16.如权利要求13所述的方法,其特征在于,还包括在屏蔽电极和屏蔽垫之间,制备一个内部电阻元件。
17.如权利要求16所述的方法,其特征在于,内部电阻是一个块状电阻,包含形成屏蔽电极或栅极电极的多晶硅。
18.如权利要求13所述的方法,其特征在于,屏蔽电极电连接到位于两个有源区之间的屏蔽电极接触区,其中屏蔽电极接触区包括多个屏蔽电极拾取沟槽,每个屏蔽电极拾取沟槽都具有一个屏蔽电极接头。
19.如权利要求18所述的方法,其特征在于,利用掺杂多晶硅配置块状电阻,填充屏蔽电极拾取沟槽。
20.如权利要求18所述的方法,其特征在于,块状电阻的电阻值由屏蔽电极拾取沟槽的长度和/或宽度决定,并且可以通过改变接头的数量来调节。
21.如权利要求18所述的方法,其特征在于,选取屏蔽电极拾取沟槽的数量,以满足所需的块状电阻的要求。
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