CN102903642B - 一种将芯片底部和周边包封的芯片级封装方法 - Google Patents
一种将芯片底部和周边包封的芯片级封装方法 Download PDFInfo
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- CN102903642B CN102903642B CN201110221870.8A CN201110221870A CN102903642B CN 102903642 B CN102903642 B CN 102903642B CN 201110221870 A CN201110221870 A CN 201110221870A CN 102903642 B CN102903642 B CN 102903642B
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 88
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 84
- 239000010703 silicon Substances 0.000 claims abstract description 84
- 239000002390 adhesive tape Substances 0.000 claims abstract description 23
- 239000005022 packaging material Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 238000005520 cutting process Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000012856 packing Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 150000003376 silicon Chemical class 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 238000009826 distribution Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000010992 reflux Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Packaging Frangible Articles (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201110221870.8A CN102903642B (zh) | 2011-07-29 | 2011-07-29 | 一种将芯片底部和周边包封的芯片级封装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110221870.8A CN102903642B (zh) | 2011-07-29 | 2011-07-29 | 一种将芯片底部和周边包封的芯片级封装方法 |
Publications (2)
Publication Number | Publication Date |
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CN102903642A CN102903642A (zh) | 2013-01-30 |
CN102903642B true CN102903642B (zh) | 2015-04-15 |
Family
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CN201110221870.8A Active CN102903642B (zh) | 2011-07-29 | 2011-07-29 | 一种将芯片底部和周边包封的芯片级封装方法 |
Country Status (1)
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CN (1) | CN102903642B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10181423B2 (en) | 2012-10-02 | 2019-01-15 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier in semiconductor packaging |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9496195B2 (en) | 2012-10-02 | 2016-11-15 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP |
US9721862B2 (en) * | 2013-01-03 | 2017-08-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages |
US9704824B2 (en) | 2013-01-03 | 2017-07-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming embedded wafer level chip scale packages |
CN103413785B (zh) * | 2013-08-02 | 2015-08-26 | 南通富士通微电子股份有限公司 | 芯片切割方法及芯片封装方法 |
CN104681525B (zh) * | 2013-11-27 | 2017-09-08 | 万国半导体股份有限公司 | 一种多芯片叠层的封装结构及其封装方法 |
CN104347542A (zh) * | 2014-09-26 | 2015-02-11 | 上海朕芯微电子科技有限公司 | 五面包封的csp结构及制造工艺 |
CN104617050B (zh) * | 2014-12-11 | 2017-08-11 | 通富微电子股份有限公司 | 晶圆级封装方法 |
CN106783642A (zh) * | 2016-12-29 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | 一种芯片及其封装方法 |
CN107342256A (zh) * | 2017-06-26 | 2017-11-10 | 矽力杰半导体技术(杭州)有限公司 | 半导体工艺及半导体结构 |
CN110098160A (zh) * | 2019-02-26 | 2019-08-06 | 上海朕芯微电子科技有限公司 | 一种晶圆级封装芯片及其制备方法 |
CN110676183A (zh) * | 2019-10-10 | 2020-01-10 | 广东佛智芯微电子技术研究有限公司 | 降低芯片塑性变形的扇出型封装方法 |
CN113035720A (zh) * | 2021-03-01 | 2021-06-25 | 紫光宏茂微电子(上海)有限公司 | 芯片上片方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4722130A (en) * | 1984-11-07 | 1988-02-02 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
Family Cites Families (2)
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JP3831287B2 (ja) * | 2002-04-08 | 2006-10-11 | 株式会社日立製作所 | 半導体装置の製造方法 |
JP2004311576A (ja) * | 2003-04-03 | 2004-11-04 | Toshiba Corp | 半導体装置の製造方法 |
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2011
- 2011-07-29 CN CN201110221870.8A patent/CN102903642B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US4722130A (en) * | 1984-11-07 | 1988-02-02 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10181423B2 (en) | 2012-10-02 | 2019-01-15 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier in semiconductor packaging |
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Effective date of registration: 20170622 Address after: Chongqing city Beibei district and high tech Industrial Park the road No. 5 of 407 Patentee after: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Address before: Bermuda Hamilton Church 2 Cola Lunden House Street Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd. Effective date of registration: 20170622 Address after: Bermuda Hamilton Church 2 Cola Lunden House Street Patentee after: ALPHA & OMEGA SEMICONDUCTOR, Ltd. Address before: The British West Indies Dakaiman Cayman Island KY1-1107 P.O. Box 709 No. 122 Marie street, and the wind floor Patentee before: Alpha and Omega Semiconductor (Cayman) Ltd. |
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Denomination of invention: Chip scale packaging method capable of encapsulating bottom and periphery of chip Effective date of registration: 20191210 Granted publication date: 20150415 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |
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PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20150415 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |