CN102595060B - Analog accumulator capable of implementing time delay integration (TDI) function inside complementary metal-oxide semiconductor (CMOS) image sensor - Google Patents

Abstract

The invention relates to the design field of analog integrated circuits. The technical scheme includes that an analog accumulator capable of implementing a TDI function inside a CMOS image sensor comprises two differential sample capacitors Cs+ and Cs-, fully differential operation, two input buses, two output buses, a n+1 group integrator, the CMOS-TID image sensor adopts roll exposure with an over-sampling rate of (n+1)/n, left electrode plates of sample capacitors Cs+ and Cs- are respectively connected with an array bus of a pixel array and a reference voltage Vref, and right electrode plates of sample capacitors Cs+ and Cs- are respectively connected with a positive input end and a negative input end of the fully differential operation, so that the CMOS image sensor can perform the TID function well and the application range of the TDI technology is extended. The analog accumulator is mainly applied to design and manufacture of semiconductor image sensors.

Description

The simulation accumulator of TDI function is realized in cmos image sensor inside

Technical field

The present invention relates to the analog integrated circuit design field, specifically, relate to the simulation accumulator that the TDI function is realized in cmos image sensor inside.

Background technology

The light signal that imageing sensor can obtain camera lens converts the electrical signal that is easy to storage, transmission and processes to.Imageing sensor can be divided into face formation and linear array type according to working method.The operation principle of face formation imageing sensor is to be the pel array that two-dimensional array arranges object is taken to obtain two-dimensional image information, and the operation principle of linear array type imageing sensor is to be the pel array that one dimensional linear array arranges to obtain two-dimensional image information by the mode to the object scanning shoot, wherein the working method of linear array type imageing sensor can be with reference to figure 1.The various fields such as the linear array type imageing sensor working method special with it is widely used in and takes photo by plane, aerial image, machine vision and imaging of medical.But because object during the pixel exposure of online formation imageing sensor is moving all the time, therefore the time for exposure of pixel seriously is limited to the translational speed of the relative subject of linear array type imageing sensor, especially under high-speed motion low-light (level) applied environment, the signal to noise ratio of (for example aerial image) linear array type imageing sensor (Signal to Noise Ratio, SNR) can become very low.For solving the low problem of SNR, someone has proposed time delays integration (Time Delay Integration, TDI) technology, it can increase SNR and the sensitivity of line scan image sensor, it is special scan mode with it, by same target is carried out to multiexposure, multiple exposure, realize very high SNR and sensitivity, therefore be specially adapted under the environment of high-speed motion low-light (level).The basic principle of TDI is that the pel array that use face battle array is arranged is worked in the mode of linear array scanning, and then the pixel that can realize different rows is carried out multiexposure, multiple exposure to the same object in movement, and the result of at every turn exposing is added up, equivalence has extended the exposure time of integration of pixel to object, therefore can significantly promote SNR and sensitivity.

The TDI technology is to realize by charge coupled device (Charge Coupled Device, CCD) imageing sensor the earliest, and ccd image sensor is also the desirable device of realizing the TDI technology, and it can realize that muting signal is cumulative.The TDI technology is applied in ccd image sensor more at present, the similar rectangular Array CCD transducer of structure of the CCD-TDI imageing sensor generally adopted, but its mode of sweeping with line is worked, as shown in Figure 2, the course of work of CCD-TDI imageing sensor is as follows: the total capable pixel of n of n level CCD-TDI imageing sensor one, the electric charge that a certain the first row pixel listed is collected in first exposure cycle is directly output not, but the electric charge addition of collecting in second exposure cycle with second pixel of same column, after the electric charge that collect for n-1 time the electric charge that the pixel of CCD-TDI imageing sensor last column (n is capable) is collected by that analogy and front is cumulative, according to the way of output of common line array CCD device, read again.In the CCD-TDI imageing sensor, the amplitude of output signal is the cumulative of n pixel integration electric charge, is equivalent to collected electric charge in a pixel n times exposure cycle, and amplitude output signal has enlarged n doubly and the amplitude of noise has only enlarged

times, so signal to noise ratio can improve doubly.

But because there are the shortcomings such as the large integrated level of power consumption is low in ccd image sensor, its application in every field is at present all being substituted by CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) imageing sensor gradually.If can realize TDI function (being the CMOS-TDI imageing sensor) by cmos image sensor, the cost of TDI camera will decline to a great extent and be more widely used so.In the prior art, someone proposes to realize the CMOS-TDI imageing sensor by the method at the inner integrated simulation signal of cmos image sensor accumulator, be that the analog signal of pixel output is introduced in the analog signal accumulator and completes cumulative to identical exposure signal, then will complete cumulative analog signal and send into ADC and quantizes to export.But in prior art, also do not have a kind of suitable simulation accumulator circuit can complete in cmos image sensor inside the TDI function.

Summary of the invention

The present invention is intended to solution and overcomes the deficiencies in the prior art, a kind of simulation accumulator is provided, make cmos image sensor can realize preferably the TDI function, enlarge the range of application of TDI technology, for achieving the above object, the technical scheme that the present invention takes is, the simulation accumulator of TDI function is realized in cmos image sensor inside, comprise: two difference sampling capacitance Cs+ and Cs-, Differential OPAMP, article two, input bus, article two, output bus, n+1 organizes integrator, the CMOS-TDI imageing sensor adopts the roll exposure that over-sampling rate is (n+1)/n, the left pole plate of sampling capacitance Cs+ and Cs-is connected respectively on the column bus of pel array and on certain reference voltage Vref, the right pole plate of sampling capacitance Cs+ and Cs-just is being connected respectively to Differential OPAMP, negative input end, described two input buss just are being connected respectively to Differential OPAMP, negative input end, described two output buss just are being connected respectively to Differential OPAMP, negative output terminal, described n+1 group integrator is connected between input bus and output bus, the negative output terminal of Differential OPAMP and positive input terminal, be respectively arranged with clock switch clk between positive output end and negative input end.

The structure of group integrator is: integrating capacitor Ch1+ mono-end by and two switches connecing be connected to the input bus be connected with the negative input end of Differential OPAMP, in two switches, one is reset switch Resetn, another is the In switch, and this electric capacity other end is connected on the output bus be connected with the positive output end of Differential OPAMP by a switch; Another integrating capacitor Ch1-by and another two switches of connecing be connected to the input bus be connected with the positive input terminal of Differential OPAMP, in another two switches, one is reset switch Resetn, another is the In switch, the progression that n is corresponding integrator, another integrating capacitor other end is connected on the output bus be connected with the negative output terminal of Differential OPAMP by a switch, and aforementioned two integrating capacitors are connected between two end points of output bus and are provided with a switch.

Accumulator starts the signal of pixel 1 output of pel array is added up, and one group of signal of output after 1 pair of object A exposure of pixel, be respectively pixel reset signal Vrst1 and pixel exposure signal V _sig1, suppose that now pixel 1 is corresponding with the 1st group of integrator in accumulator, pixel column bus output V _rst1during signal, at first the left polar plate voltage of sampling capacitance Cs+ becomes V _rst1, clock switch clk closure now, reset switch Reset1 closure, the I1 switch disconnects, the integrating capacitor in the 1st group of integrator and left pole plate be connected respectively to the positive-negative input end of amplifier, and right pole plate is shorted together, now sampling capacitance Cs+ and integrating capacitor C _h1+the electric charge summation of middle storage is:

Q ₊＝C _s+×(V _rst1-V _{com_out})-C _h1+×V _os (1)

V wherein _{com_out}for Differential OPAMP output common mode voltage, while sampling capacitance C _s-with integrating capacitor C _h1the electric charge summation of-middle storage is:

Q _-＝C _s-×(V _ref-V _{com_out}) (2)

The signal of exporting when the pixel column bus becomes V _sig1after, the left polar plate voltage of sampling capacitance Cs+ becomes V _sig1, and sampling capacitance C _s-left polar plate voltage be still V _refconstant, now clock switch clk disconnects, and reset switch Reset1 disconnects, I1 switch closure, and the electric charge summation of now storing in sampling capacitance Cs+ and integrating capacitor Ch1+ is:

Q ₊＝C _s+×(V _sig1-V _{com_in})+C _h1+×(V _out--V _{com_in}-V _os) (3)

V wherein _{com_in}for amplifier common mode input, V _out-for accumulator negative output terminal, V _out+for the accumulator positive output end, while sampling capacitance C _s-with integrating capacitor C _h1the electric charge summation of-middle storage is:

Q _-＝C _s-×(V _ref-V _{com_in})+C _h1-×(V _out+-V _{com_in}) (4)

If sampling capacitance Cs+ is all Cs, integrating capacitor C mutually with the Cs-size _h1+and C _h1-size is all C mutually _h1, therefore according to the charge conservation equation, can draw:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})---\left(5\right)$

After pixel 2 completes the exposure of A object, the signal of its output continues to be added to first group of integrator, and the now output of accumulator becomes:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})]---\left(6\right)$

V wherein _rst2and V _sig2be one group of signal of output after the exposure of the 2 pairs of A objects of pixel, n pixel be successively to all being added to the signal of output in first group of integrator after the exposure of A object, finally simulates accumulator and complete after adding up for n time and be output as:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})+......+(V_{\mathrm{rstn}}-V_{\mathrm{sign}})]---\left(7\right)$

Signal after finally by the Read switch, n time being added up reads into settling signal in the rear class adc circuit and quantizes.

Technical characterstic of the present invention and effect:

Simulation accumulator of the present invention is lacked of proper care memory technology elimination offset voltage to simulating the impact of accumulator Output rusults by input, has reduced imageing sensor column fixed pattern noise (Fixed Pattern Noise, FPN).The Vrst continuously pixel exported by sampling capacitance and Vsig sample and realize that Vrst-Vsig handles, and complete correlated-double-sampling (Correlated Double Sample, the CDS) operation to pixel output signal.In accumulator, integrating capacitor is resetted by the pole plate short circuit, and reset mode is simply without introducing additional reference voltage.Can realize cumulative to voltage signal by described simulation accumulator circuit, cumulative can directly being applied in the CMOS-TDI imageing sensor that the present invention proposes, realize the TDI technology better.

The accompanying drawing explanation

Fig. 1 is the mode of operation schematic diagram of the line scan image sensor that provides of prior art.

Fig. 2 is the operation principle schematic diagram of the CCD-TDI imageing sensor that provides of prior art.

Fig. 3 is the circuit diagram of simulation accumulator provided by the invention.

Fig. 4 is the over-sampling exposure time series schematic diagram that prior art provides.

Fig. 5 is the control sequential chart of simulation accumulator provided by the invention.

Fig. 6 is the concrete application example of simulation accumulator provided by the invention.

Embodiment

The circuit diagram of described simulation accumulator is with reference to figure 3, and it mainly comprises: sampling capacitance Cs, Differential OPAMP, two input buss, two output buss, n+1 organize integrator, and voltage source V os is used for meaning the input offset voltage of amplifier.Make the CMOS-TDI imageing sensor adopt the synchronism of roll exposure to realize that the different rows pixel is exposed to same object that over-sampling rate is (n+1)/n.The roll exposure that so-called over-sampling rate is (n+1)/n the 1st row that successively expose from the 1st row pixel to the capable pixel of n in an exposure cycle afterwards increases single exposure again and starts, and in an exposure cycle, the capable pixel of n can be exported n+1 data like this.In pel array in the capable pixel of n and described accumulator the corresponding relation of n+1 group integrator as shown in Figure 4, in an exposure cycle, pel array is read line by line, and signal is added up in corresponding integrator.Described accumulator adopts the fully differential structure, the left pole plate of two difference sampling capacitance Cs+ and Cs-is connected respectively on the column bus of pel array and on certain reference voltage Vref, the right pole plate of sampling capacitance Cs+ and Cs-is connected respectively to the positive-negative input end of amplifier, described two input buss are connected respectively to the input of amplifier, described two output buss are connected respectively to the output of amplifier, and described n+1 group integrator is connected between input bus and output bus.Wherein direct voltage source Vos is for simulating the equivalent input noise voltage of Differential OPAMP, and this voltage source is necessary being in structure not.

The work schedule of accumulator is with reference to figure 4, its course of work is as follows: after pixel 1 is to certain object A end exposure, accumulator starts the signal of pixel 1 output is added up, pixel 1 readout is exported one group of signal, be respectively pixel reset signal Vrst1 and pixel exposure signal Vsig1, suppose that now pixel 1 is corresponding with the 1st group of integrator in accumulator.During pixel column bus output Vrst1 signal, at first the left polar plate voltage of sampling capacitance Cs+ becomes Vrst1, the switch closure that now clk controls, the switch closure that Reset1 controls, the switch that I1 controls disconnects, integrating capacitor Ch1+ in the 1st group of integrator and the left pole plate of Ch1-are connected respectively to the positive-negative input end of amplifier, and right pole plate is shorted together.Because the storage of the right pole plate of integrating capacitor is differential signal, so after short circuit, its polar plate voltage can become the output common mode voltage of amplifier, completes the reset operation to the electric charge in integrating capacitor, now sampling capacitance Cs+ and integrating capacitor C _h1+the electric charge summation of middle storage is:

Q ₊＝C _s+×(V _rst1-V _{com_out})-C _h1+×V _os (1)

V wherein _{com_out}for amplifier output common mode voltage, while sampling capacitance Cs-and integrating capacitor C _h1-the electric charge summation of middle storage is:

Q _-＝C _s-×(V _ref-V _{com_out}) (2)

The signal of exporting when the pixel column bus becomes V _sig1after, the left polar plate voltage of sampling capacitance Cs+ becomes V _sig1, and the left polar plate voltage of sampling capacitance Cs-is still V _refconstant, the switch that now clk controls disconnects, and the switch that Reset1 controls disconnects, the switch closure that I1 controls, now sampling capacitance Cs+ and integrating capacitor C _h1+the electric charge summation of middle storage is:

Q ₊＝C _s+×(V _sig1-V _{com_in})+C _h1+×(V _out--V _{com_in}-V _os) (3)

V wherein _{com_in}for amplifier common mode input, V _out-for accumulator negative output terminal, V _out+for the accumulator positive output end, while sampling capacitance Cs-and integrating capacitor C _h1-the electric charge summation of middle storage is:

Q _-＝C _s-×(V _ref-V _{com_in})+C _h1-×(V _out+-V _{com_in}) (4)

Because the input of amplifier belongs to floating empty node, so sampling capacitance Cs+ and integrating capacitor C in these two processes _h1+the electric charge summation of middle storage can not become, and formula (1) equates with formula (3); This is equally applicable to sampling capacitance Cs-and integrating capacitor C _h1-, formula (2) equates with formula (4), establishes sampling capacitance Cs+ and is all mutually Cs, integrating capacitor C with the Cs-size _h1+and C _h1-size is all C mutually _h1, therefore according to the charge conservation equation, can draw:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})---\left(5\right)$

After pixel 2 completes the exposure of A object, the signal of its output continues to be added to first group of integrator, and the now output of accumulator becomes:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})]---\left(6\right)$

V wherein _rst2and V _sig2be one group of signal of output after the exposure of the 2 pairs of A objects of pixel, n pixel be successively to all being added to the signal of output in first group of integrator after the exposure of A object, finally simulates accumulator and complete after adding up for n time and be output as:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})+......+(V_{\mathrm{rstn}}-V_{\mathrm{sign}})]---\left(7\right)$

Signal after finally by the Read switch, n time being added up reads into settling signal in the rear class adc circuit and quantizes, from above-mentioned, the simulation accumulator that the present invention describes controls in the clock cycle at one CDS operation and the cumulative operation completed input signal, has eliminated the impact of Differential OPAMP offset voltage on the accumulator Output rusults simultaneously.

For making the purpose, technical solutions and advantages of the present invention more clear, provide the specific descriptions of embodiment of the present invention below in conjunction with an example.The simulation accumulator that the present invention is proposed is applied in cmos image sensor, described imageing sensor framework is with reference to figure 6, wherein pixel array sized is 128 row * 1024 row, the simulation accumulator adopts the row parallel schema, the simulation accumulator carries out voltage accumulation by the exposure signal to same object of every row pixel output, finally will complete 128 signals after cumulative outputs in the parallel monocline ADC of row and is quantized, finally the digital signal of every row output is exported by the shift register serial, realized 128 grades of CMOS-TDI imageing sensors.

Claims (2)

1. the simulation accumulator of TDI function is realized in a cmos image sensor inside, it is characterized in that, comprise: two difference sampling capacitance Cs+ and Cs-, Differential OPAMP, article two, input bus, article two, output bus, n+1 organizes integrator, the CMOS-TDI imageing sensor adopts the roll exposure that over-sampling rate is (n+1)/n, the left pole plate of sampling capacitance Cs+ and Cs-is connected respectively on the column bus of pel array and on certain reference voltage Vref, the right pole plate of sampling capacitance Cs+ and Cs-just is being connected respectively to Differential OPAMP, negative input end, described two input buss just are being connected respectively to Differential OPAMP, negative input end, described two output buss just are being connected respectively to Differential OPAMP, negative output terminal, described n+1 group integrator is connected between input bus and output bus, the negative output terminal of Differential OPAMP and positive input terminal, be respectively arranged with clock switch clk between positive output end and negative input end, the structure of group integrator is: an integrating capacitor C _h1+one end by and two switches connecing be connected to the input bus be connected with the negative input end of Differential OPAMP, in two switches, one is reset switch Resetn, another is the In switch, and this electric capacity other end is connected on the output bus be connected with the positive output end of Differential OPAMP by a switch, another integrating capacitor C _h1-by and another two switches of connecing be connected to the input bus be connected with the positive input terminal of Differential OPAMP, in another two switches, one is reset switch Resetn, another is the In switch, the progression that n is corresponding integrator, another integrating capacitor other end is connected on the output bus be connected with the negative output terminal of Differential OPAMP by a switch, and aforementioned two integrating capacitors are connected between two end points of output bus and are provided with a switch.

2. simulation accumulator as claimed in claim 1, is characterized in that, accumulator starts the signal of pixel 1 output of pel array is added up, and one group of signal of output after 1 pair of object A exposure of pixel, be respectively pixel reset signal V _rst1with pixel exposure signal V _sig1, suppose that now pixel 1 is corresponding with the 1st group of integrator in accumulator, pixel column bus output V _rst1during signal, at first the left polar plate voltage of sampling capacitance Cs+ becomes V _rst1, clock switch clk closure now, reset switch Reset1 closure, the I1 switch disconnects, the integrating capacitor in the 1st group of integrator and left pole plate be connected respectively to the positive-negative input end of amplifier, and right pole plate is shorted together, now sampling capacitance Cs+ and integrating capacitor C _h1+the electric charge summation of middle storage is:

Q ₊＝C _s+(V _rst1-V _{com_out})-C _h1+V _os (1)

V wherein _{com_out}for Differential OPAMP output common mode voltage, while sampling capacitance C _s-with integrating capacitor C _h1-the electric charge summation of middle storage is:

Q _-＝C _s-(V _ref-V _{com_out})(2)

The signal of exporting when the pixel column bus becomes V _sig1after, the left polar plate voltage of sampling capacitance Cs+ becomes V _sig1, and sampling capacitance C _s-left polar plate voltage be still V _refconstant, now clock switch clk disconnects, and reset switch Reset1 disconnects, I1 switch closure, and the electric charge summation of now storing in sampling capacitance Cs+ and integrating capacitor Ch1+ is:

Q ₊＝C _s+(V _sig1-V _{com_in})+C _h1+(V _out--V _{com_in}-V _os) (3)

V wherein _{com_in}for amplifier common mode input, V _out-for accumulator negative output terminal, V _out+for the accumulator positive output end, while sampling capacitance C _s-with integrating capacitor C _h1-the electric charge summation of middle storage is:

Q _-＝C _s-(V _ref-V _{com_in})+C _h1-(V _out+-V _{com_in}) (4)

If sampling capacitance Cs+ is all Cs, integrating capacitor C mutually with the Cs-size _h1+and C _h1-size is all C mutually _h1, therefore according to the charge conservation equation, can draw:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})---\left(5\right)$

After pixel 2 completes the exposure of A object, the signal of its output continues to be added to first group of integrator, and the output of now simulating accumulator becomes:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})]---\left(6\right)$

V wherein _rst2and V _sig2be one group of signal of output after the exposure of the 2 pairs of A objects of pixel, n pixel be successively to all being added to the signal of output in first group of integrator after the exposure of A object, finally simulates accumulator and complete after adding up for n time and be output as:

$V_{\mathrm{out}-}-V_{\mathrm{out}+}=\frac{C_s}{C_{h1}}[(V_{\mathrm{rst}1}-V_{\mathrm{sig}1})+(V_{\mathrm{rst}2}-V_{\mathrm{sig}2})+......+(V_{\mathrm{rstn}}-V_{\mathrm{sign}})]---\left(7\right)$

Signal after finally by the Read switch, n time being added up reads into settling signal in the rear class adc circuit and quantizes.

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