CN102412151A - Method for manufacturing super junction double-surface trench insulated gate bipolar translator (IGBT) device - Google Patents
Method for manufacturing super junction double-surface trench insulated gate bipolar translator (IGBT) device Download PDFInfo
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- CN102412151A CN102412151A CN2011103835042A CN201110383504A CN102412151A CN 102412151 A CN102412151 A CN 102412151A CN 2011103835042 A CN2011103835042 A CN 2011103835042A CN 201110383504 A CN201110383504 A CN 201110383504A CN 102412151 A CN102412151 A CN 102412151A
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Abstract
The invention discloses a method for manufacturing a super junction double-surface trench insulated gate bipolar translator (IGBT) device. The method comprises the following steps of: on an N-type substrate, performing graph exposure on the front of a silicon slice, etching a pillar P, and etching to form a trench; growing epitaxy highly doped with B on a hole or the trench; grinding the epitaxy till the surface of monocrystalline silicon; performing exposure definition on a trench gate; growing and doping N-type polycrystals; etching a polycrystal gate; implanting a source and a P well into the front and performing drive-in; etching a deep trench on the back, wherein the width of the trench is smaller than the phosphorus ion diffusion length in the trench; filling N-type polycrystalline silicon and performing drive-in at high temperature for a long time to ensure that N-type carriers among polycrystals are connected with each other; implanting boron ions into the back and activating; and performing metal steaming on a collector. By using up the pillar P and the N-type substrate, the effects of resisting voltage and further reducing specific on resistance can be achieved, current density is larger, resistance and joule heat in an on state are reduced, and turn-off response speed is higher.
Description
Technical field
The invention belongs to semiconductor device structure in the semiconductor device.
Background technology
IGBT (Insulated Gate Bipolar Transistor) insulated gate bipolar transistor; By the compound full-control type voltage driven type power semiconductor that BJT (double pole triode) and MOS (insulating gate type field effect tube) form, have the advantage of low conduction voltage drop two aspects of high input impedance and the GTR of MOSFET concurrently.The GTR saturation pressure reduces, and current carrying density is big, but drive current is bigger; The MOSFET driving power is very little, and switching speed is fast, but conduction voltage drop is big, and current carrying density is little.Insulated gate bipolar transistor IGBT combines the advantage of above two kinds of devices, and the little and saturation pressure of driving power reduces.Be fit to very much to be applied to direct voltage and be fields such as 600V and above converter system such as alternating current machine, frequency converter, Switching Power Supply, lighting circuit, traction transmission.
Withstand voltage enough in order to guarantee, will increase the thickness of substrate between N type MOS structure and the bottom collector electrode as far as possible, just the base thickness of PNP triode is thicker.Though withstand voltage much of that, base resistance is higher, Joule heat can be bigger during on-state, and on state voltage is bigger during work.
But for 8 cun sheets, production-line technique can only be handled 725 microns sheet, and the thin slice of handling below 600 microns is very difficult, relates to many board transformations, and cost is high, has a big risk.
Summary of the invention
Technical problem to be solved by this invention provides a kind of combining super and ties two-sided groove-shaped IGBT device making method, and it can be so that current density be bigger, and resistance when reducing on-state and Joule heat make that turn-off response speed is faster.
In order to solve above technical problem, the invention provides a kind of combining super and tie two-sided groove-shaped IGBT device making method, may further comprise the steps: on N type substrate, silicon chip face exposure figure carries out the etching of P post, carries out etching and forms groove; To the grow up extension of highly doped B of hole or groove; Carry out the grinding of extension, be ground to the surface of monocrystalline silicon; Carry out the exposure definition of trench gate; Growth doped N-type polycrystalline; The polycrystalline grid are carried out etching; The front is carried out the injection of source and P trap and is pushed away trap; The etching of deep trench is carried out at the back side, and the width of groove is less than the length of phosphonium ion diffusion in the groove; Carry out the filling of N type polysilicon then, carry out high temperature and push away trap for a long time, make that N type charge carrier links together between the polycrystalline; Then the boron ion is injected at the back side, the line activating of going forward side by side; Carry out the steaming gold of collector electrode.
Beneficial effect of the present invention is: reach the withstand voltage and further effect that reduces conduction resistance through exhausting of P post and N type substrate, make current density bigger, resistance when having reduced on-state and Joule heat make that turn-off response speed is faster.
The figure of silicon chip face exposure micron more than 0.5 micron carries out the etching of P post.
Carry out etching and form groove dark more than 5 microns.
To the grow up extension of highly doped boron of hole or groove, bulk concentration is more than 1E15.
Growth doped N-type polycrystalline, thickness is greater than 500 dusts.
The etching of deep trench is carried out at the back side, and the degree of depth of etching is more than 1 micron.
Carry out the steaming gold of collector electrode, the thickness of metal is more than 1 micron.
The bulk concentration that said N type substrate is mixed phosphorus is between 1E13-1E14.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
Fig. 1 is the sketch map of etching deep trench on the substrate of light doping;
Fig. 2 is the sketch map of highly doped N type polysilicon of in deep trench, growing up;
Fig. 3 (a) carries out high temperature to push away trap for a long time and join together and form the sketch map of a cutoff layer;
Fig. 3 (b) reaches the sketch map of the groove more than 5 microns deeply from positive etching;
Fig. 4 carries out etching groove from the front, growth extension, the sketch map of formation P post;
Fig. 5 is the etching of carrying out trench gate, the sketch map that growth polysilicon gate and positive source and P trap form;
Fig. 6 carries out the sketch map that thinning back side grinds;
Fig. 7 carries out back side boron ion to inject, and intensifies and steams goldenly, makees the sketch map that collector electrode is drawn.
Embodiment
Invention provides a kind of combining super to tie the device architecture of 8 inches of groove-shaped IGBT; Do the theoretical super junction N type groove type MOS structure of supporting of you MOS of outbound in the front of device; Reach the effect of withstand voltage and further reduction conduction resistance through exhausting of P post and N type substrate; Make current density bigger, resistance when having reduced on-state and Joule heat make that turn-off response speed is faster.
Utilize the present invention needn't transform board, under sheet technology, realize the exclusive characteristic of sheet devices, can bear bigger short circuit current.
Before doing positive technology and beginning, on the N type substrate of mixing between the bulk concentration 1E13-1E14 of phosphorus, it is carried out back-etching; The degree of depth of etching is greater than more than 1 micron; The width of groove is more than 1 micron, and the polysilicon of groove the inside growth N type carries out the extension of polysilicon then; Distance between groove and the groove has so just formed the field cutoff layer that joins together less than the diffusion length of phosphonium ion.
Silicon dioxide more than front growth 3000A is as the barrier layer of etching, and the figure of silicon chip face exposure micron more than 0.5 carries out the silicon dioxide etching then, removes photoresist after the etching.Carry out the etching of P type groove with silicon dioxide as the barrier layer then, the degree of depth at quarter washes silicon dioxide more than 5 microns, and the P type extension of growing up and mixing B is carried out the grinding of P type extension.To the exposure definition of trench gate, carry out etching, the degree of depth is greater than more than 1 micron, and the N type of growing up then polycrystalline carries out etching definition polycrystalline grid.Carry out the injection of positive source and trap, push away trap.Carry out the interconnected of metal then.
After accomplishing positive technology, will carry out attenuate according to withstand voltage requirement, directly carry out the injection and the activation of back side boron ion, steam the gold back and form collector electrode.
Through introducing Ku Er MOS notion, replace general metal-oxide-semiconductor with groove-shaped super junction and combine the PNP darlington structure again, form band deep trench field cut-off type IGBT device architecture, this device architecture has combined the advantage of super junction NMOS pipe and two kinds of structures of IGBT.Device is positive because super junction NMOS has replaced General N MOS, and doing this type device selection substrate so just can be denseer than the substrate concentration of existing IGBT device, and cost is lower; Like this littler than the PNP base width of general IGBT, on state resistance is littler, and the Joule heat of generation is littler; Bear under the equal withstand voltage prerequisite; During OFF state, the fall delay time is shorter, and the short circuit current that can bear is bigger.
The back side is through dig deep trench in advance, and it is highly doped to fill out the N type, and long-time high temperature pushes away the mode of trap, can form a cutoff layer in the mode of sheet.
The deep slot type IGBT technology device architecture and the process implementation method of combining super knot of the present invention are following:
1. the groove-shaped IGBT device architecture of a novel combining super knot, the thickness of this silicon chip can be as thin as 50 microns.
2. as shown in Figure 1, on the substrate of light doping, carry out the etching of back side deep trench earlier, the width of etching is 1 micron, and the degree of depth is more than 1 micron, and the distance between the groove guarantees connecting together after the phosphonium ion diffusion.
3. the polysilicon that carries out the raising doping then as shown in Figure 2, and shown in Fig. 3 (a), push away trap for a long time, make a cutoff layer connect together.
4. the figure of silicon chip face exposure micron more than 0.5 carries out the etching of P post.
5. shown in Fig. 3 (b), carry out etching and form groove dark more than 5 microns.
6. as shown in Figure 4, to the grow up extension of highly doped B of hole or groove, bulk concentration is more than 1E15.
7. carry out the grinding of extension, be ground to the surface of monocrystalline silicon.
8. carry out the exposure definition of trench gate.
9. growth doped N-type polycrystalline, thickness is greater than 500 dusts.
10. as shown in Figure 5, the polycrystalline grid are carried out etching.
11. the front is carried out the injection of source and P trap and is pushed away trap.
12. as shown in Figure 6, wafer thinning is carried out at the back side, is thinned to more than 50 microns.
13. as shown in Figure 7, the back side is carried out the injection of boron ion and pushed away trap.
14. carry out the steaming gold of collector electrode, the thickness of metal is more than 1 micron.
The present invention is not limited to the execution mode that preceding text are discussed.More than the description of embodiment is intended in order to describe and explain the technical scheme that the present invention relates to.Based on the conspicuous conversion of the present invention enlightenment or substitute and also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, so that those of ordinary skill in the art can use numerous embodiments of the present invention and multiple alternative reaches the object of the invention.
Claims (8)
1. a combining super is tied two-sided groove-shaped IGBT device making method, it is characterized in that, may further comprise the steps:
On N type substrate, silicon chip face exposure figure carries out the etching of P post, carries out etching and forms groove;
To the grow up extension of highly doped B of hole or groove;
Carry out the grinding of extension, be ground to the surface of monocrystalline silicon;
Carry out the exposure definition of trench gate;
Growth doped N-type polycrystalline;
The polycrystalline grid are carried out etching;
The front is carried out the injection of source and P trap and is pushed away trap;
The etching of deep trench is carried out at the back side, and the width of groove is less than the length of phosphonium ion diffusion in the groove;
Carry out the filling of N type polysilicon then, carry out high temperature and push away trap for a long time, make that N type charge carrier links together between the polycrystalline;
Then the boron ion is injected at the back side, the line activating of going forward side by side;
Carry out the steaming gold of collector electrode.
2. combining super as claimed in claim 1 is tied two-sided groove-shaped IGBT device making method, it is characterized in that, the figure of silicon chip face exposure micron more than 0.5 micron carries out the etching of P post.
3. combining super as claimed in claim 1 is tied two-sided groove-shaped IGBT device making method, it is characterized in that, carries out etching and forms groove dark more than 5 microns.
4. combining super as claimed in claim 1 is tied two-sided groove-shaped IGBT device making method, it is characterized in that, to the grow up extension of highly doped boron of hole or groove, bulk concentration is more than 1E15.
5. combining super as claimed in claim 1 is tied two-sided groove-shaped IGBT device making method, it is characterized in that, and growth doped N-type polycrystalline, thickness is greater than 500 dusts.
6. combining super as claimed in claim 1 is tied two-sided groove-shaped IGBT device making method, it is characterized in that the etching of deep trench is carried out at the back side, and the degree of depth of etching is more than 1 micron.
7. combining super as claimed in claim 1 is tied two-sided groove-shaped IGBT device making method, it is characterized in that, carries out the steaming gold of collector electrode, and the thickness of metal is more than 1 micron.
8. combining super as claimed in claim 1 is tied two-sided groove-shaped IGBT device making method, it is characterized in that, the bulk concentration that said N type substrate is mixed phosphorus is between 1E13-1E14.
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| CN2011103835042A CN102412151A (en) | 2011-11-25 | 2011-11-25 | Method for manufacturing super junction double-surface trench insulated gate bipolar translator (IGBT) device |
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| CN2011103835042A CN102412151A (en) | 2011-11-25 | 2011-11-25 | Method for manufacturing super junction double-surface trench insulated gate bipolar translator (IGBT) device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377903A (en) * | 2012-04-28 | 2013-10-30 | 上海华虹Nec电子有限公司 | Method for forming grate trench of deep trench type super junction with trench grates |
| CN111354677A (en) * | 2020-03-09 | 2020-06-30 | 上海华虹宏力半导体制造有限公司 | Preparation method of deep trench isolation structure and semiconductor device |
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| CN101308871A (en) * | 2007-05-17 | 2008-11-19 | 富士电机电子技术株式会社 | Insulated gate semiconductor device and manufacturing mnethod thereof |
| US20100039675A1 (en) * | 2005-11-18 | 2010-02-18 | The Go Daddy Group, Inc. | Relevant Messages Associated with Outgoing Fax Documents Using Previous Facsimile |
| JP2010062347A (en) * | 2008-09-04 | 2010-03-18 | Fuji Electric Systems Co Ltd | Method of manufacturing semiconductor device |
| CN102201437A (en) * | 2010-03-25 | 2011-09-28 | 力士科技股份有限公司 | Trench insulated gate bipolar transistor and manufacturing method thereof |
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2011
- 2011-11-25 CN CN2011103835042A patent/CN102412151A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100039675A1 (en) * | 2005-11-18 | 2010-02-18 | The Go Daddy Group, Inc. | Relevant Messages Associated with Outgoing Fax Documents Using Previous Facsimile |
| CN101308871A (en) * | 2007-05-17 | 2008-11-19 | 富士电机电子技术株式会社 | Insulated gate semiconductor device and manufacturing mnethod thereof |
| JP2010062347A (en) * | 2008-09-04 | 2010-03-18 | Fuji Electric Systems Co Ltd | Method of manufacturing semiconductor device |
| CN102201437A (en) * | 2010-03-25 | 2011-09-28 | 力士科技股份有限公司 | Trench insulated gate bipolar transistor and manufacturing method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377903A (en) * | 2012-04-28 | 2013-10-30 | 上海华虹Nec电子有限公司 | Method for forming grate trench of deep trench type super junction with trench grates |
| CN103377903B (en) * | 2012-04-28 | 2016-02-10 | 上海华虹宏力半导体制造有限公司 | The formation method of the gate groove of the deep slot type super junction containing trench gate |
| CN111354677A (en) * | 2020-03-09 | 2020-06-30 | 上海华虹宏力半导体制造有限公司 | Preparation method of deep trench isolation structure and semiconductor device |
| CN111354677B (en) * | 2020-03-09 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Preparation method of deep trench isolation structure and semiconductor device |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140115 |
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Effective date of registration: 20140115 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Application publication date: 20120411 |