CN101694851A - Grooved gate IGBT with P-type floating layer - Google Patents
Grooved gate IGBT with P-type floating layer Download PDFInfo
- Publication number
- CN101694851A CN101694851A CN200910167912A CN200910167912A CN101694851A CN 101694851 A CN101694851 A CN 101694851A CN 200910167912 A CN200910167912 A CN 200910167912A CN 200910167912 A CN200910167912 A CN 200910167912A CN 101694851 A CN101694851 A CN 101694851A
- Authority
- CN
- China
- Prior art keywords
- type
- base
- groove
- bipolar transistor
- igbt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Thyristors (AREA)
Abstract
The invention relates to a grooved gate IGBT with a P-type floating layer, belonging to the technical filed of semiconductor power devices. On a basis of grooved gate insulated-gate bipolar transistor (IGBT) controlled by an accumulation layer, a P-type floating layer (11) is introduced to effectively improve the electric-field integration effect of the bottom of the grooved gate and greatly increase the breakdown voltage of the device. Meanwhile, due to the existence of the P-type floating layer, a JFET zone is introduced to play the effect of shielding the groove barrier potential of the accumulation layer to a certain extent and greatly reduce the drain current of the device. When the device is forwardly conducted, the saturation current density of the device is greatly decreased so as to greatly improve the short-circuit safety operation area (SCSOA) of the device. The invention maintains the original low forward-conducted voltage drop of the grooved gate IGBT controlled by the accumulation layer and increases the forward bias safety operation area (FBSOA) and the bolt current density while decreasing the drain current of the device, improving the breakdown voltage of the device and greatly improving the SCSOA of the device.
Description
Technical field
A kind of groove grid IGBT with the floating dead level of P type belongs to the semiconductor power device technology field.
Background technology
Insulated gate bipolar transistor is rapid, the widely used power electronic device of a kind of development.The advantage that it is the input impedance height that utilizes MOSFET, drive circuit is simple and the bipolar transistor current density is big, saturation pressure reduces and the new unit that is combined into.Now be widely used in electromagnetic oven, UPS uninterrupted power supply, automotive electronic igniter, frequency converter, motor drive system and other energy conversion device.
IGBT proposes in nineteen eighty-two at first, is the punch structure, and as shown in Figure 1, it is the P in high concentration
+Substrate (P
+Collector region) extension N type resilient coating 3, N successively on 2
-The insulated gate bipolar transistor structure that manufactures behind the base layer 4.Since exist N type resilient coating 3, electric field in N type resilient coating 3, will obtain stopping, thereby form a trapezoidal Electric Field Distribution, as shown in Figure 1, so can utilize thin N
-The base can obtain higher puncture voltage, helps reducing conducting resistance, thereby reduces quiescent dissipation, but because P
+Substrate is thicker relatively, and is dense, makes that the injection efficiency of emitter junction is very high, electronics can not flow out from back of the body emitter region substantially during shutoff, only lean against the compound disappearance of base, thereby its turn-off time is very long, increase switching loss, often needed to increase Lifetime Control during fabrication.Simultaneously, when the high pressure punch IGBT that makes greater than 600V, the increase of required epitaxy layer thickness makes manufacturing cost increase greatly., developed the non-through insulated-gate bipolar transistor npn npn thereafter, its structure as shown in Figure 2, it is at monocrystalline N
-Make on the substrate, after surface texture is finished, inject the thin and more lightly doped back of the body P of formation by ion
+Collector region 2 (being commonly referred to transparent collector) reduces back of the body emitter region injection efficiency.Owing to adopted the transparent collecting zone technology, make the non-through insulated-gate bipolar transistor npn npn compare with the punch insulated gate bipolar transistor, have following Main Feature: conduction voltage drop is positive temperature coefficient, and power consumption and current tail are little with variation of temperature; Owing to the emission effciency of longitudinal P NP is decreased and controls, obviously improved the delay of OFF state; Because of without epitaxial wafer and low without Lifetime Control technology cost.But the non-through insulated-gate bipolar transistor npn npn is when adopting the transparent collecting zone technology to improve switching speed, owing to there has not been N type resilient coating, electric field will end at N
-The base, thus a leg-of-mutton Electric Field Distribution formed, as shown in Figure 2, so in order to guarantee the withstand voltage N that must adopt relative broad
-Base 4 causes the increase of conducting resistance, has also just increased quiescent dissipation.Particularly when bearing high voltage, conductivity modulation effect will obviously weaken, and it will be more remarkable that conduction loss increases.So, only optimize the contradictory relation of forward conduction voltage drop and turn-off power loss by reducing back of the body emitter region injection efficiency, its effect is very limited, document K.Sheng, F.Udrea, G.A.J.Amaratunga, " Optimum carrier distribution ofthe IGBT " (optimization of insulated gate bipolar transistor carrier concentration profile), Solid-State Electronics 44,1573-1583,2000 point out, realize optimizing preferably between forward conduction voltage drop and the turn-off power loss, and this and charge carrier are at N
-The distribution of base 4 is closely related, increases the concentration of emitter one side charge carrier, and the concentration that reduces collector electrode one side charge carrier helps realizing better optimize between them.
In order to realize trading off between better conduction voltage drop and the turn-off power loss, document T.Laska, M.Miinzer, F.Pfirsch, C.Schaeffer, T.Schmidt, " The Field Stop IGBT (FS IGBT)-A New Power Device Concept with aGreat Improvement Potential " (electric field termination type insulated gate bipolar transistor-a kind of novel power device) with very big lifting potentiality, ISPSD ' 2000, May 22-25, Toulouse, France has proposed a kind of electric field termination type insulated gate bipolar transistor, and its structure as shown in Figure 3, the method that it adopts ion to inject is made a N type resilient coating 3 earlier at the silicon chip back side, annotate boron again and form back of the body P
+Collector region 2, because the existence of N type resilient coating 3, electric field will end at N type resilient coating 3, thereby form a trapezoidal Electric Field Distribution, as shown in Figure 3, so can make N
-It is thinner that base 4 can be done.But the N type resilient coating 3 of electric field termination type insulated gate bipolar transistor surface texture all make finish after the back side inject to form, thereby can not carry out high temperature and anneal for a long time, therefore the thickness of N type resilient coating 3 and the activation concentration of impurity all are very limited, the highfield suspension layer of making high tension apparatus with so thin resilient coating is very unreliable physically, loses efficacy easily; And the silicon wafer thickness that electric field termination type insulated gate bipolar transistor requires is very thin, generally about 70 μ m, guarantee that so thin silicon chip does not break in the process of flow, and is not crooked, is quite difficult; Moreover electric field termination type insulated gate bipolar transistor is to N
-In the base 4 distribution of charge carrier change not remarkable, so the optimization between forward conduction voltage drop and the turn-off power loss also can further improve again.
Trench gate type insulated gate bipolar transistor as shown in Figure 4, is another developing direction of insulated gate bipolar transistor, and it adopts trench gate structure to replace planar gate, has improved the on state characteristic of device, reduces conducting resistance, has increased current density.In trench gate structure, the JFET in the planar gate structure has been cut out well by the technology of dry etching, also all digs up together with the part P type base that surrounds this zone, extends to formation raceway groove original grid under.So N
+Source region 9 and the P type base 8 that stays just are exposed to the sidewall of this groove, by a series of special processing such as sidewall oxidations, have formed the raceway groove perpendicular to silicon chip surface in the P type base 8 in the sidewall oxide outside.Electric current is from N during work
-Base 4 directly flows to vertical-channel and enters N
+Source region 9 makes primitive unit cell density increase, and current density increases, and latch-up reduces.But trench gate type insulated gate bipolar transistor is when hot operation, because temperature raises, and carrier lifetime increases, it is big that PNP transistor amplification coefficient becomes on the one hand, and the hole current that causes flowing through P type base 8 becomes big; On the other hand, temperature raises and makes the mobility in hole reduce greatly, and the resistance of P type base 8 increases; This two aspects reason all can cause the conventional groove insulated gate bipolar transistor because the rising of temperature, anti-breech lock ability reduces significantly, the safety operation area also reduces thereupon, and reliability reduces, and how seeking to have the anti-breech lock ability of better high temperature is the problem that presses for solution.
In order to improve the anti-breech lock ability of high temperature, reduce the parasitic thyristor effect in traditional insulated gate bipolar transistor structure, we had once proposed a kind of insulated gate bipolar transistor of accumulation layer control: Zehong Li, Mengliang Qian, Bo Zhang, " TAC-IGBT:an improved IGBT structure " (insulated gate bipolar transistor of accumulation layer control: a kind of insulated gate bipolar transistor structure of improvement), ISPSD ' 09, PP.124-127, May 2009, and its slot grid structure as shown in Figure 5.It has replaced P type base and MOS inversion channel in traditional insulated gate bipolar transistor with accumulation layer, by positive P
+N
-The blocking-up that the electronic barrier that the internal electric field of knot forms comes control device, form the operate as normal that the accumulation layer raceway groove comes control device by adding grid voltage, greatly reduced the parasitic thyristor effect in traditional insulated gate bipolar transistor structure, the safety operation area of device, reliability and hot operation characteristic are all significantly promoted, can obtain lower conduction voltage drop, bigger saturation current density, simultaneously, because the effect of accumulation layer, make the injection efficiency of emitter electronics strengthen greatly, optimized N
-Carrier concentration profile in the base 4 can realize between conduction voltage drop and the turn-off power loss better compromise.On the technology, it has saved the manufacturing of P type base in traditional insulated gate bipolar transistor, and structure is more simple, and manufacturing cost reduces.But meanwhile, the saturation current density of increase descends the short-circuit capacity of the insulated gate bipolar transistor of accumulation layer control to some extent, and puncture voltage depends on design size, insulated gate bipolar transistor withstand voltage not enough to some extent that makes accumulation layer control.So also need further to improve short circuit trouble free service ability.
Summary of the invention
The object of the present invention is to provide the groove grid IGBT of the floating dead level of a kind of P of having type, it passes through P on the one hand
+N
-The blocking-up that the electronic barrier that the internal electric field of knot forms comes control device, the operate as normal of coming control device by accumulation layer; On the other hand, the introducing of the floating dead level of P type has improved the electric field concentration effect of groove grid bottoms, thereby makes puncture voltage increase greatly.Simultaneously, a JFET district has been introduced in the existence of the floating dead level of P type, this JFET district has certain shielding action to the potential barrier of accumulation layer raceway groove, so make the leakage current of device greatly lower, identity unit for 1200V, its electric leakage reduces a nearly magnitude, thereby makes the design margin of device increase, and is more conducive to the actual manufacturing.And because the existence in JFET district " A ", saturation current density greatly reduces, and makes the short circuit safety operation area (SCSOA) of device significantly increase, and the trench gate type insulated gate bipolar transistor of manufacturing process and accumulation layer control is basic identical.
Technical solution of the present invention is as follows:
A kind of groove grid IGBT with the floating dead level of P type, as shown in Figure 6, each cellular comprises collector electrode 1, P
+Collector region 2, N
-Base 4, gate oxide 5, polysilicon gate 6, emitter 7, N
+Source region 9, P
+Tagma 10 and P type float dead level 11.
Described gate oxide 5 and polysilicon gate 6 constitute groove and delete structure, and described groove is deleted structure and is arranged in cellular N
-The middle top of base 4, and the oxide layer of deleting that groove is deleted the structure upper surface links to each other with emitter 7; Described P
+Tagma 10 is arranged in cellular N
-The top of the both sides of base 4, and respectively with emitter 7 and N
-Base 4 links to each other; Described N
+Source region 9 is positioned at emitter 7 belows, and respectively with P
+Tagma 10, N
-The oxide layer of deleting that base 4, emitter 7 and groove are deleted texture edge links to each other; The floating dead level 11 of described P type is positioned at groove and deletes structure and N
-Between the base 4, and delete oxide layer and N respectively at what groove was deleted the structure lower surface
-Base 4 links to each other.
Need to prove:
(1) described a kind of groove grid IGBT with the floating dead level of P type is under blocking state, P
+Tagma 10 and N
-The internal electric field that forms between the base 4 constitutes an electronic barrier, has stoped electronics by N
+Source region 9 flows into N
-Base 4 is so that device bears is high withstand voltage.
(2) described a kind ofly have the groove grid IGBT of the floating dead level of P type under conducting state, at N
-Form an accumulation layer between base 4 and the gate oxide 5, electronics can pass through N
+Source region 9 arrives N through accumulation layer
-Base 4, thereby the operate as normal of control device.
(3) described a kind of groove grid IGBT with the floating dead level of P type, because the existence of the floating dead level of P type, improved the electric field concentration effect of groove grid bottom, made the peak-peak electric field be effectively reduced and transfer to floating empty p type island region, improved the puncture voltage of device greatly by groove grid bottom corners.
(4) described a kind of groove grid IGBT with the floating dead level of P type, a JFET district has been introduced in the existence of the floating dead level of P type, shown in " A " among Fig. 6, along with the continuous increase of collector voltage, JFET district resistance constantly increases, thereby makes the saturation current density of device greatly reduce.Simultaneously, this JFET district has certain shielding action to the potential barrier of accumulation layer raceway groove, so make the leakage current of device greatly reduce.
Operation principle of the present invention:
A kind of groove grid IGBT provided by the invention with the floating dead level of P type, when keeping low forward conduction voltage drop and bigger forward bias safety operation area (FBSOA), reduced the leakage current of device, improved the puncture voltage of device, also make the short circuit safety operation area of device improve greatly, and make simply, design margin increases.Fig. 7 is the novel cell grid IGBT structure chart (with the internal electric field signal) of the floating dead level of a kind of P of having type, is that example illustrates operation principle of the present invention here with Fig. 7.
When polysilicon gate 6 not during making alive, because N
+The length in source 9 is less, P
+N
-Knot is (by P
+Tagma 10 and N
-Base 4 compositions) internal electric field 18 (transverse electric field shown in dotted lines in Figure 7) that forms forms the potential barrier of an electronics, and the blocking-up electronics is by N
+Source region 9 to N
-The path of base 4 is so when collector electrode 1 was high potential with respect to emitter 7, along with the continuous rising of collector electrode 1 voltage, depletion region will be at low-doped N
-Base 4 is constantly expanded; Because the existence of the floating dead level 11 of P type, improved the electric field concentration effect of groove grid bottoms, make the peak-peak electric field be effectively reduced and transfer to floating empty p type island region by groove grid bottom corners, improved puncture voltage greatly, thereby it is very high withstand voltage that the novel cell grid IGBT structure of the floating dead level of the described a kind of P of having type can be born; And floating empty p type island region introduced a JFET district (shown in " A " among Fig. 7), and the potential barrier of accumulation layer raceway groove is had certain shielding action, greatly reduces leakage current, makes device have only minimum leakage current; When polysilicon gate 6 adds positive voltage, at N
-Form an accumulation layer between base 4 and the gate oxide 5, electronics can pass through N
+Source region 9 arrives N through accumulation layer
-Base 4, for wide base PNP transistor (by P type collector region 23, N-base 4 and P+ tagma 10 are formed) provides base current, the hole is injected into N by P type collector region 2
- Base 4 carries out electricity to it and leads modulation, N
-The charge carrier of base 4 constantly increases, and along with the continuous rising of collector electrode 1 voltage, the electron injection efficiency of emitter 7 one sides also improves constantly, thus the effect that can realize improving emitter one side carrier concentration.Owing to adopted accumulation layer to replace inversion layer, electron concentration in the accumulation layer is high, therefore electron injection efficiency is also very high, modulating action is strong all the better leading near the N-base electricity of emitter, realized the carrier concentration profile of emitter one side carrier concentration greater than collector electrode one side, this charge carrier distributes and can realize compromise between better conduction voltage drop and the turn-off power loss with respect to traditional collector electrode one side carrier concentration greater than the distribution of emitter, and by adjusting the injection efficiency of emitters on back side, can be to N
-Further optimal design is carried out in the distribution of charge carrier in the base.Because the formation of accumulation layer is more easy than inversion layer, carrier concentration higher (electron injection efficiency is higher), mobility is bigger, so the more traditional insulated gate bipolar transistor of groove grid IGBT of the floating dead level of the described a kind of P of having type has littler grid electric charge, lower conduction voltage drop; Simultaneously, the floating dead level of P type has been introduced JFET district " A ", and along with the continuous increase of collector voltage, JFET district resistance constantly increases, thereby the saturation current density of greatly reducing makes the short circuit safety operation area (SCSOA) of device significantly increase.
In sum, a kind of groove grid IGBT provided by the invention with floating empty P type layer, on the chennel gate isolated gate bipolar transistor npn npn basis of existing accumulation layer control, introduce a floating empty P type layer, overcome relatively large, the withstand voltage lower shortcoming of chennel gate isolated gate bipolar transistor npn npn structure leakage current of accumulation layer control.Simulation result shows that the existence of the floating dead level of P type is very effective to leakage current and the raising puncture voltage that reduces device.Simultaneously, the JFET district that the floating dead level of P type is introduced has reduced the saturation current density of device effectively, thereby makes short circuit trouble free service ability be largely increased.Than traditional insulated gate bipolar transistor structure, it has bigger breech lock current density again when keeping relatively low forward voltage drop, bigger forward bias safety operation area (FBSOA) and short circuit safety operation area (SCSOA).The present invention makes simply, and design margin increases, and is more conducive to the actual manufacturing.
Description of drawings
Fig. 1 is traditional punch insulated gate bipolar transistor structural representation.
Wherein, the 1st, collector electrode, the 2nd, P
+Collector region, the 3rd, N type resilient coating, the 4th, N
-The base, the 5th, gate oxide, the 6th, polysilicon gate, the 7th, emitter, the 8th, P type base, the 9th, N
+The source region, the 10th, P
+The tagma.
Fig. 2 is traditional non-through insulated-gate bipolar transistor npn npn structural representation.
Fig. 3 is an electric field termination type insulated gate bipolar transistor structural representation.
Fig. 4 is a conventional trench gate insulated gate bipolar transistor structural representation.
Fig. 5 is the trench gate insulated gate bipolar transistor structural representation of accumulation layer control.
Fig. 6 is a kind of groove grid IGBT structural representation with floating empty P type layer provided by the invention.
Wherein, the 11st, the P type floats dead level.
Fig. 7 is a kind of groove grid IGBT structure and internal electric field schematic diagram with floating empty P type layer provided by the invention.
Wherein, the 18th, internal electric field.
Fig. 8 is a kind of groove grid IGBT and the trench gate insulated gate bipolar transistor of accumulation layer control and puncture voltage comparison diagram of conventional trench gate insulated gate bipolar transistor with floating empty P type layer provided by the invention.
Fig. 9 is a kind of have the groove grid IGBT of floating empty P type layer and the three-dimensional electric field distribution comparison diagram of trench gate insulated gate bipolar transistor when puncturing of accumulation layer control provided by the invention.
Figure 10 is a kind of have the groove grid IGBT of floating empty P type layer and the trench gate insulated gate bipolar transistor and the forward conduction voltage drop schematic diagram of conventional trench gate insulated gate bipolar transistor under different current density conditions of accumulation layer control provided by the invention.
Figure 11 is the trench gate insulated gate bipolar transistor of a kind of groove grid IGBT with floating empty P type layer provided by the invention and accumulation layer control and conventional trench gate insulated gate bipolar transistor in grid voltage is I-V characteristic curve comparison diagram under the 15V condition.
Embodiment
Adopt the novel cell grid IGBT structure with floating empty P type layer of the present invention, can obtain low conduction voltage drop, big forward bias safety operation area (FBSOA) and short circuit safety operation area (SCSOA), low current leakage, and can further improve puncture voltage, make simply, design margin is big.Along with development of semiconductor, adopt the present invention can also make more low pressure drop, the power device of high reliability.
A kind of groove grid IGBT with the floating dead level of P type, as shown in Figure 6, each cellular comprises collector electrode 1, P
+Collector region 2, N
-Base 4, gate oxide 5, polysilicon gate 6, emitter 7, N
+Source region 9, P
+Tagma 10 and P type float dead level 11.
Described gate oxide 5 and polysilicon gate 6 constitute groove and delete structure, and described groove is deleted structure and is arranged in cellular N
-The middle top of base 4, and the oxide layer of deleting that groove is deleted the structure upper surface links to each other with emitter 7; Described P
+Tagma 10 is arranged in cellular N
-The top of the both sides of base 4, and respectively with emitter 7 and N
-Base 4 links to each other; Described N
+Source region 9 is positioned at emitter 7 belows, and respectively with P
+Tagma 10, N
-The oxide layer of deleting that base 4, emitter 7 and groove are deleted texture edge links to each other; The floating dead level 11 of described P type is positioned at groove and deletes structure and N
-Between the base 4, and delete oxide layer and N respectively at what groove was deleted the structure lower surface
-Base 4 links to each other.
During concrete enforcement, if adopt epitaxy technique, then main manufacturing step is: P
+The preparation of substrate, N
+Extension, N
-Extension, P
+Source photoetching and P
+The source region is injected, oxidation and photoetching grid Trench window, and etching grid Trench, gate oxidation also injects the boron ion, and the deposit polysilicon is that hard mask anti-carves polysilicon, N with oxide layer
+Source photoetching and N
+The source region is injected, and removes the oxide layer that covers on the source, and depositing metal is finished the metallization in grid source, passivation etc.
During concrete enforcement, if adopt thin slice technology, then main manufacturing step is: the molten N in district
-The preparation of monocrystalline liner, P
+Source photoetching and P
+The source region is injected, oxidation and photoetching grid Trench window, and etching grid Trench, gate oxidation also injects the boron ion, and the deposit polysilicon is that hard mask anti-carves polysilicon, N with oxide layer
+Source photoetching and N
+The source region is injected, and removes the oxide layer that covers on the source, and depositing metal is finished the metallization in grid source, back side N
+Resilient coating injects (optional), and back side P type collector region injects, back face metalization, passivation etc.
In implementation process, can be as the case may be, under the constant situation of basic structure, carry out certain accommodation design, for example when adopting epitaxy technique to make, N
+Source photoetching and N
+The source region is injected and can be placed on oxidation and the manufacturing before of photoetching grid Trench window etc.Semi-conducting materials such as also available carborundum, GaAs, indium phosphide or germanium silicon replace body silicon when making device.
By two-dimensional simulation software TSUPREM IV and MEDICI emulation tool, the groove grid IGBT (as shown in Figure 6) of the floating dead level of a kind of P of having type provided by the present invention and traditional trench gate insulated gate bipolar transistor (as shown in Figure 4) and the insulated trench gate electrode bipolar type transistor (as shown in Figure 5) of a kind of accumulation layer control have been carried out the emulation comparison.The 1200V trench gate non-through insulated-gate bipolar transistor npn npn that analogue simulation thin slice technology is made, and simulation parameter is a P type collector region dosage 1 * 10
14Cm
-2N
-Base resistance rate 55 Ω cm, thickness are 169 μ m; Gate oxide thickness is 100nm; N
+ Source region dosage 1 * 10
16Cm
-2, length 2 μ m, junction depth 0.4 μ m; P
+ Source region dosage 1 * 10
16Cm
-2, length 1 μ m; P type base dosage 1.5 * 10
14Cm
-2Source gash depth 2.5 μ m, source groove and groove grid spacing 2 μ m; Groove grid width 1 μ m, the groove grid degree of depth 8 μ m; The life-span in electronics and hole is 1 μ s.Fig. 8 is the emulation comparative result of the insulated trench gate electrode bipolar type transistor controlled of groove grid IGBT and the accumulation layer of the floating dead level of a kind of P of having type of being provided and traditional trench gate insulated gate bipolar transistor puncture voltage, as seen from the figure, the insulated trench gate electrode bipolar type transistor of traditional trench gate insulated gate bipolar transistor and accumulation layer control almost can be realized identical puncture voltage, obtains higher puncture voltage and have the novel cell grid IGBT of floating empty P type layer owing to float the introducing of empty P type layer.Under the same conditions, when the puncture voltage of the insulated trench gate electrode bipolar type transistor of traditional trench gate insulated gate bipolar transistor and accumulation layer control had only 1200V, the groove grid IGBT with floating empty P type layer can obtain the puncture voltage of 1350V.The three-dimensional electric field distribution comparison curves of the insulated gate bipolar transistor that a kind of groove grid IGBT with floating empty P type layer provided by the present invention and accumulation layer are controlled as shown in Figure 9.As shown in Figure 9, the existence of floating empty P type layer has improved the electric field concentration effect of groove grid bottoms, makes the peak-peak electric field be effectively reduced and transfers to floating empty p type island region by groove grid bottom corners, thereby make puncture voltage increase greatly.On the other hand, a JFET district has been introduced in the existence of floating empty P type floor, shown in " A " among Fig. 6, this JFET district has certain shielding action to the potential barrier of accumulation layer raceway groove, so make the leakage current of device greatly lower, for the identity unit of 1200V, its electric leakage reduces a nearly magnitude.The insulated trench gate electrode bipolar type transistor of a kind of groove grid IGBT with floating empty P type layer provided by the present invention and accumulation layer control and the traditional forward conduction voltage drop of trench gate insulated gate bipolar transistor under different current density conditions are as shown in figure 10, owing to adopted the darker groove grid degree of depth 8 μ m relatively, increased the nearly emitter N of place
-The electron concentration of base makes that three's forward voltage drop variation tendency is not remarkable, at 100A/cm
2Current density under, their forward voltage drop is all about 1.5V.Figure 11 is the insulated trench gate electrode bipolar type transistor of groove grid IGBT with floating empty P type layer provided by the present invention and accumulation layer control and the I-V curve comparison diagram of traditional trench gate insulated gate bipolar transistor.As can be seen from Figure 11, have the existence of the groove grid IGBT of floating empty P type floor owing to JFET district " A ", along with the continuous increase of collector voltage, JFET district resistance constantly increases, thereby makes saturation current density greatly reduce.Under the same terms, the saturation current density with groove grid IGBT of floating empty P type layer can reduce a magnitude, thereby makes the short circuit safety operation area (SCSOA) of device significantly increase.
Claims (1)
1. one kind has the groove grid IGBT that the P type floats dead level, and each cellular comprises collector electrode (1), P
+Collector region (2), N
-Base (4), gate oxide (5), polysilicon gate (6), emitter (7), N
+Source region (9), P
+Tagma (10) and P type float dead level (11);
Peculiar levying is:
Described gate oxide (5) and polysilicon gate (6) constitute groove and delete structure, and described groove is deleted structure and is arranged in cellular N
-The middle top of base (4), and the oxide layer of deleting that groove is deleted the structure upper surface links to each other with emitter (7); Described P
+Tagma (10) is arranged in cellular N
-The top of the both sides of base (4), and respectively with emitter (7) and N
-Base (4) links to each other; Described N
+Source region (9) is positioned at emitter (7) below, and respectively with P
+Tagma (10), N
-Base (4), emitter (7) and the oxide layer of deleting that groove is deleted texture edge link to each other; The floating dead level (11) of described P type is positioned at groove and deletes structure and N
-Between the base (4), and delete oxide layer and N respectively at what groove was deleted the structure lower surface
-Base (4) links to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910167912A CN101694851A (en) | 2009-10-16 | 2009-10-16 | Grooved gate IGBT with P-type floating layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910167912A CN101694851A (en) | 2009-10-16 | 2009-10-16 | Grooved gate IGBT with P-type floating layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101694851A true CN101694851A (en) | 2010-04-14 |
Family
ID=42093804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910167912A Pending CN101694851A (en) | 2009-10-16 | 2009-10-16 | Grooved gate IGBT with P-type floating layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101694851A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489903A (en) * | 2012-06-11 | 2014-01-01 | 北大方正集团有限公司 | Trench IGBT and manufacturing method thereof |
| CN105789269A (en) * | 2016-03-04 | 2016-07-20 | 上海源翌吉电子科技有限公司 | Trench insulated gate bipolar transistor and preparation method therefor |
| CN106876255A (en) * | 2017-02-10 | 2017-06-20 | 中国科学院半导体研究所 | Sic semiconductor device and preparation method thereof |
| CN107623027A (en) * | 2017-10-20 | 2018-01-23 | 电子科技大学 | A kind of trench gate electric charge memory type insulated gate bipolar transistor and its manufacture method |
| CN107994069A (en) * | 2017-12-29 | 2018-05-04 | 安徽赛腾微电子有限公司 | A kind of IGBT device and its manufacture method |
| CN109860303A (en) * | 2019-03-26 | 2019-06-07 | 电子科技大学 | A kind of insulated-gate power device of accumulation type channel |
| CN110504315A (en) * | 2019-08-30 | 2019-11-26 | 电子科技大学 | A kind of groove-shaped insulated gate bipolar transistor and preparation method thereof |
| CN107731893B (en) * | 2017-09-02 | 2020-02-11 | 西安交通大学 | Low-on-resistance double-groove silicon carbide IGBT device with floating zone and preparation method |
| CN114678413A (en) * | 2022-03-25 | 2022-06-28 | 电子科技大学 | High-reliability silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) device integrating P-type channel |
-
2009
- 2009-10-16 CN CN200910167912A patent/CN101694851A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489903A (en) * | 2012-06-11 | 2014-01-01 | 北大方正集团有限公司 | Trench IGBT and manufacturing method thereof |
| CN105789269A (en) * | 2016-03-04 | 2016-07-20 | 上海源翌吉电子科技有限公司 | Trench insulated gate bipolar transistor and preparation method therefor |
| CN106876255B (en) * | 2017-02-10 | 2019-09-24 | 中国科学院半导体研究所 | Sic semiconductor device and preparation method thereof |
| CN106876255A (en) * | 2017-02-10 | 2017-06-20 | 中国科学院半导体研究所 | Sic semiconductor device and preparation method thereof |
| CN107731893B (en) * | 2017-09-02 | 2020-02-11 | 西安交通大学 | Low-on-resistance double-groove silicon carbide IGBT device with floating zone and preparation method |
| CN107623027A (en) * | 2017-10-20 | 2018-01-23 | 电子科技大学 | A kind of trench gate electric charge memory type insulated gate bipolar transistor and its manufacture method |
| CN107623027B (en) * | 2017-10-20 | 2020-03-31 | 电子科技大学 | Trench gate charge storage type insulated gate bipolar transistor and manufacturing method thereof |
| CN107994069A (en) * | 2017-12-29 | 2018-05-04 | 安徽赛腾微电子有限公司 | A kind of IGBT device and its manufacture method |
| CN107994069B (en) * | 2017-12-29 | 2024-03-15 | 安徽赛腾微电子有限公司 | IGBT device and manufacturing method thereof |
| CN109860303A (en) * | 2019-03-26 | 2019-06-07 | 电子科技大学 | A kind of insulated-gate power device of accumulation type channel |
| CN110504315A (en) * | 2019-08-30 | 2019-11-26 | 电子科技大学 | A kind of groove-shaped insulated gate bipolar transistor and preparation method thereof |
| CN110504315B (en) * | 2019-08-30 | 2020-09-15 | 电子科技大学 | Groove-type insulated gate bipolar transistor and preparation method thereof |
| CN114678413A (en) * | 2022-03-25 | 2022-06-28 | 电子科技大学 | High-reliability silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) device integrating P-type channel |
| CN114678413B (en) * | 2022-03-25 | 2023-04-28 | 电子科技大学 | High reliability silicon carbide MOSFET device integrating P-channel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101694850B (en) | Carrier-storing grooved gate IGBT with P-type floating layer | |
| CN101694851A (en) | Grooved gate IGBT with P-type floating layer | |
| CN107785415B (en) | SOI-RC-LIGBT device and preparation method thereof | |
| CN101393927A (en) | Accumulation layer controlled insulation gate type bipolar transistor | |
| CN105742346B (en) | Double division trench gate charge storage type RC-IGBT and its manufacturing method | |
| CN102169892B (en) | Enhancement mode planar insulated gate bipolar transistor (IGBT) | |
| CN107808899A (en) | Lateral power with hybrid conductive pattern and preparation method thereof | |
| CN110504308B (en) | High-speed low-loss multi-groove-gate high-voltage power device | |
| CN109065621A (en) | A kind of insulated gate bipolar transistor and preparation method thereof | |
| CN101478001B (en) | Collecting electrode IGBT having hole injection structure | |
| CN103489910A (en) | Power semiconductor device and manufacturing method thereof | |
| CN102184949B (en) | Deep groove side oxygen controlled planar isolated gate bipolar transistor | |
| CN101452952A (en) | Insulated trench gate electrode bipolar type transistor | |
| CN102157551A (en) | IGBT with current carrier storage layer and additional hole passage | |
| CN110518058A (en) | A kind of lateral trench type insulated gate bipolar transistor and preparation method thereof | |
| CN102306657A (en) | Insulated gate bipolar transistor with floating buried layer | |
| CN105993076A (en) | Bi-directional MOS device and manufacturing method thereof | |
| CN115241286A (en) | SiC semi-super junction type gate bipolar transistor device and manufacturing method thereof | |
| CN110504260B (en) | Transverse groove type IGBT with self-bias PMOS and preparation method thereof | |
| CN105789291A (en) | Double split trench gate charge storage type insulated gate bipolar transistor (IGBT) and manufacturing method thereof | |
| CN102354707A (en) | Insulated gate bipolar transistor (IGBT) with anti-latchup effect | |
| CN110473917A (en) | A kind of transversal I GBT and preparation method thereof | |
| CN110504313B (en) | Transverse groove type insulated gate bipolar transistor and preparation method thereof | |
| CN109065608A (en) | A kind of lateral bipolar power semiconductor and preparation method thereof | |
| CN109148566A (en) | Silicon carbide MOSFET device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20100414 |