CN103377903B - The formation method of the gate groove of the deep slot type super junction containing trench gate - Google Patents
The formation method of the gate groove of the deep slot type super junction containing trench gate Download PDFInfo
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- CN103377903B CN103377903B CN201210133322.4A CN201210133322A CN103377903B CN 103377903 B CN103377903 B CN 103377903B CN 201210133322 A CN201210133322 A CN 201210133322A CN 103377903 B CN103377903 B CN 103377903B
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Abstract
The invention discloses a kind of formation method of gate groove of the deep slot type super junction containing trench gate, comprise step: form hard mask on a semiconductor substrate; Photoetching process is adopted to define deep trench region; The hard mask in deep trench region is removed, carries out etching with hard mask for barrier layer and form multiple deep trench be alternately arranged; Semi-conducting material filling is carried out to deep trench; Carry out back being carved into the tip position of surface lower than deep trench to semi-conducting material; At the front deposition oxidation film of Semiconductor substrate; Carry out back carving to oxide-film until the nitride film of hard mask exposes; Utilize etching process to be removed by nitride film, the oxide-film being positioned at deep trench region is retained; The oxide-film be arranged alternately is utilized to form gate groove for mask carries out etching to Semiconductor substrate.Energy simplification of flowsheet of the present invention, improves the alignment precision of Product Process, improves the performance of product.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of formation method of gate groove of the deep slot type super junction containing trench gate.
Background technology
The size of existing shallow/deep groove type super junction reduces along with the raising of integrated level, and when this size is accomplished close to submicron-scale, the grid structure of existing shallow/deep groove type super junction needs to apply groove-shaped grid structure.In prior art when preparing the deep slot type super junction containing trench gate, needing the chemical wet etching carrying out twice groove, being respectively:
First time, etching forms deep trench, and the position of deep trench needs to adopt photoetching process to define.Epitaxial silicon is filled or polysilicon forms the P type thin layer and N-type thin layer that are alternately arranged on a silicon substrate in deep trench.
Second time etching forms gate groove, and on the silicon substrate of gate groove between deep trench, the position of gate groove needs to adopt photoetching process to define.The grid of gate dielectric layer and gate polysilicon formation super junction is filled in gate groove.
As from the foregoing, need in the preparation method of existing shallow/deep groove type super junction to adopt Twi-lithography technique to form deep trench and gate groove, and gate groove requires between two adjacent deep trench, therefore require between Twi-lithography technique to ensure good aligning.But along with the size of product is more and more less, the difficulty of the aligning between two grooves is increasing, poor to the performance that will definitely reduce product.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of formation method of gate groove of the deep slot type super junction containing trench gate, and energy simplification of flowsheet, improves the alignment precision of Product Process, improves the performance of product.
For solving the problems of the technologies described above, the formation method of the gate groove of the deep slot type super junction containing trench gate provided by the invention comprises the steps:
Step one, in the Semiconductor substrate of the first conduction type, form hard mask; Described hard mask is nitride film, or described hard mask is for nitride film, top are the duplicature of oxide-film bottom one.
Step 2, employing photoetching process define the deep trench region of deep slot type super junction; The described hard mask in described deep trench region is removed and formed etching window, etching the Semiconductor substrate bottom described etching window for barrier layer with described hard mask and form multiple deep trench, the Semiconductor substrate of described first conduction type between each adjacent described deep trench forms the first conduction type thin layer.
Step 3, employing are returned the nitride film of carving technology to described hard mask comprehensively and are etched, and make described etching window be greater than the size of described deep trench; Epitaxial growth technology or polycrystalline deposition technique is adopted to fill the semi-conducting material that described deep trench carries out the second conduction type.
Step 4, to described semi-conducting material carry out back carve, Hui Kehou, the top surface of described semi-conducting material is lower than the tip position of described deep trench, form the second conduction type thin layer by the described semi-conducting material be filled in each described deep trench, described first conduction type thin layer and described second conduction type thin layer are alternative expression arrangement architecture.
Step 5, front deposition oxidation film in described Semiconductor substrate; The described deep trench be positioned on each described second conduction type thin layer and described etching window are filled by the oxide-film of institute's deposit; The oxide-film of institute's deposit also extends to above the described hard mask outside described etching window.
Step 6, carry out back carving until the described nitride film of the described hard mask of composition outside described etching window exposes to described oxide-film.
Described nitride film is removed by step 7, the etching process utilizing the corrosion rate of nitride film to be greater than the corrosion rate of oxide-film, will be positioned at the described oxide-film reservation above each described second conduction type thin layer.
Step 8, utilize described oxide-film for mask to the described first conduction type thin layer between each described deep trench carry out etching formed gate groove.
Further improvement is, described Semiconductor substrate is epitaxial silicon chip; Described nitride film is silicon nitride film, and described oxide-film is silicon oxide film; Described semi-conducting material is silicon materials.
Further improvement is, described first conduction type is N-type, described second conduction type is P type; Or described first conduction type is P type, described second conduction type is N-type.
Further improvement is, regulates the interval between described gate groove and described deep trench by the difference of the size of the described etching window in regulating step three and the size of described deep trench
The present invention only adopts a photoetching process just energy deep trench and gate groove, wherein gate groove does not need to adopt photoetching process to carry out position definition more in addition, but adopt oxide-film to be the autoregistration definition that mask realizes gate groove position, a photoetching process of can saving in the process of the present invention, simplification of flowsheet, reduces process costs.
The autoregistration of gate groove position of the present invention can also realize the good alignment between deep trench and gate groove, avoid the problem of alignment precision difference when adopting Twi-lithography technique, thus greatly can improve alignment precision, enable the inventive method be applied to the product of smaller szie.The raising of alignment precision also can improve the performance of product.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is embodiment of the present invention method flow diagram;
Fig. 2 A-Fig. 2 F is the structural representation of the device in each step of embodiment of the present invention method.
Embodiment
As shown in Figure 1, be embodiment of the present invention method flow diagram; As shown in Fig. 2 A to Fig. 2 F, it is the structural representation of the device in each step of embodiment of the present invention method.The formation method that the embodiment of the present invention contains the gate groove of the deep slot type super junction of trench gate comprises the steps:
Step one, as shown in Figure 2 A, the Semiconductor substrate 1 of the first conduction type forms hard mask 2; In the embodiment of the present invention, described Semiconductor substrate 1 is epitaxial silicon chip; Described hard mask 2 is silicon nitride film.Described hard mask 2 also can be for silicon nitride film, top are the duplicature of silicon oxide film bottom one in other embodiments.In the embodiment of the present invention, the first conduction type is N-type or P type; Second conduction type is contrary with the first conduction type, is P type or N-type.
Step 2, as shown in Figure 2 B, adopts photoetching process to define the deep trench region of deep slot type super junction; The described hard mask 2 in described deep trench region is removed and formed etching window, be that barrier layer to etch the Semiconductor substrate 1 bottom described etching window and to form multiple deep trench 3a with described hard mask 2, the Semiconductor substrate 1 of described first conduction type between each adjacent described deep trench 3a forms the first conduction type thin layer 1a.Two deep trench 3a and first conduction type thin layer 1a are only illustrated in Fig. 2 B, according to the actual needs of the deep slot type super junction that will be formed, the quantity of described deep trench 3a and described first conduction type thin layer 1a can be multiple, the structure that both are arranged alternately.
Step 3, as shown in Figure 2 C, adopts and returns the nitride film of carving technology to described hard mask 2 comprehensively and etch, make described etching window be greater than the size of described deep trench 3a.Adopt epitaxial growth technology or polycrystalline deposition technique to carry out the filled with silicon material of the second conduction type to described deep trench 3a, namely in described deep trench 3a, fill silicon epitaxy layer or polysilicon.Wherein, the interval between the gate groove 5 of follow-up formation and described deep trench 3a is regulated by the difference of the size regulating the size of described etching window and described deep trench 3a in the embodiment of the present invention.
Step 4, as shown in Figure 2 C, carry out back carving to described semi-conducting material, Hui Kehou, the top surface of described semi-conducting material is lower than the tip position of described deep trench 3a, form the second conduction type thin layer 3 by the described semi-conducting material be filled in each described deep trench 3a, described first conduction type thin layer 1a and described second conduction type thin layer 3 are in alternative expression arrangement architecture.
Step 5, as shown in Figure 2 C, at the front deposition oxidation film of described Semiconductor substrate; The described deep trench 3a be positioned on each described second conduction type thin layer 3 and described etching window fill by the oxide-film 4 of institute's deposit; The oxide-film 4 of institute's deposit also extends to above the described hard mask 2 outside described etching window.Wherein, before deposition oxidation film 4, because the top of each described second conduction type thin layer 3 will lower than the top of described deep trench 3a, therefore the non-filler of described deep trench 3a above each described second conduction type thin layer 3.
Step 6, as shown in Figure 2 D, carries out back carving to described silicon oxide film 4 until the described silicon nitride film of the described hard mask 2 of composition outside described etching window exposes.
Step 7, as shown in Figure 2 E, described silicon nitride film is removed by the etching process utilizing the corrosion rate of silicon nitride film to be greater than the corrosion rate of silicon oxide film 4, retained by the described silicon oxide film 4a be positioned at above each described second conduction type thin layer 3 in described deep trench region.Described etching process in this step can be dry corrosion process, can be also wet corrosion technique, as long as the corrosion rate meeting silicon nitride film is greater than the corrosion rate of silicon oxide film 4, also namely adopts the etching process of silicon nitride film and silicon oxide film high selectivity.
Step 8, as shown in Figure 2 F, utilizes described silicon oxide film 4a to form gate groove 5 for mask carries out etching to the described first conduction type thin layer 1a between each described deep trench.Wherein, the interval between described gate groove 5 and described deep trench 3a is determined by the difference of the size of the described etching window in step 3 and the size of described deep trench 3a.Interval between described gate groove 5 and described deep trench 3a is the distance at the edge of described gate groove 5 and the edge of contiguous described deep trench 3a.
As from the foregoing, be adopt described silicon oxide film 4a to be the position that mask comes that autoregistration defines described gate groove 5 in the embodiment of the present invention, the accurate aligning between described gate groove 5 and described deep trench 3a can be realized, thus the performance of product can be improved.In addition, the present invention can also save a photoetching process, thus energy simplification of flowsheet, save process costs.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. a formation method for the gate groove of the deep slot type super junction containing trench gate, is characterized in that, comprise the steps:
Step one, in the Semiconductor substrate of the first conduction type, form hard mask; Described hard mask is nitride film, or described hard mask is for nitride film, top are the duplicature of oxide-film bottom one;
Step 2, employing photoetching process define the deep trench region of deep slot type super junction; The described hard mask in described deep trench region is removed and formed etching window, etching the Semiconductor substrate bottom described etching window for barrier layer with described hard mask and form multiple deep trench, the Semiconductor substrate of described first conduction type between each adjacent described deep trench forms the first conduction type thin layer;
Step 3, employing are returned the nitride film of carving technology to described hard mask comprehensively and are etched, and make described etching window be greater than the size of described deep trench; Epitaxial growth technology or polycrystalline deposition technique is adopted to fill the semi-conducting material that described deep trench carries out the second conduction type;
Step 4, to described semi-conducting material carry out back carve, Hui Kehou, the top surface of described semi-conducting material is lower than the tip position of described deep trench, form the second conduction type thin layer by the described semi-conducting material be filled in each described deep trench, described first conduction type thin layer and described second conduction type thin layer are alternative expression arrangement architecture;
Step 5, front deposition oxidation film in described Semiconductor substrate; The described deep trench be positioned on each described second conduction type thin layer and described etching window are filled by the oxide-film of institute's deposit; The oxide-film of institute's deposit also extends to above the described hard mask outside described etching window;
Step 6, carry out back carving until the described nitride film of the described hard mask of composition outside described etching window exposes to described oxide-film;
Described nitride film is removed by step 7, the etching process utilizing the corrosion rate of nitride film to be greater than the corrosion rate of oxide-film, will be positioned at the described oxide-film reservation above each described second conduction type thin layer;
Step 8, utilize described oxide-film for mask to the described first conduction type thin layer between each described deep trench carry out etching formed gate groove.
2. the formation method of the gate groove of the deep slot type super junction as claimed in claim 1 containing trench gate, is characterized in that: described Semiconductor substrate is epitaxial silicon chip; Described nitride film is silicon nitride film, and described oxide-film is silicon oxide film; Described semi-conducting material is silicon materials.
3. the formation method of the gate groove of the deep slot type super junction as claimed in claim 1 containing trench gate, is characterized in that: described first conduction type is N-type, described second conduction type is P type; Or described first conduction type is P type, described second conduction type is N-type.
4. the formation method of gate groove of the deep slot type super junction as claimed in claim 1 containing trench gate, is characterized in that: regulate the interval between described gate groove and described deep trench by the difference of the size of the described etching window in regulating step three and the size of described deep trench.
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| CN108807517B (en) * | 2018-06-29 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Trench gate super junction device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101847655A (en) * | 2010-04-22 | 2010-09-29 | 上海宏力半导体制造有限公司 | Trench grate capable of improving trench grate MOS device performance and manufacture method thereof |
| CN102412151A (en) * | 2011-11-25 | 2012-04-11 | 上海华虹Nec电子有限公司 | Method for manufacturing super junction double-surface trench insulated gate bipolar translator (IGBT) device |
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| US7790549B2 (en) * | 2008-08-20 | 2010-09-07 | Alpha & Omega Semiconductor, Ltd | Configurations and methods for manufacturing charge balanced devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101847655A (en) * | 2010-04-22 | 2010-09-29 | 上海宏力半导体制造有限公司 | Trench grate capable of improving trench grate MOS device performance and manufacture method thereof |
| CN102412151A (en) * | 2011-11-25 | 2012-04-11 | 上海华虹Nec电子有限公司 | Method for manufacturing super junction double-surface trench insulated gate bipolar translator (IGBT) device |
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