CN102800591A - Preparation method for FS-IGBT device - Google Patents
Preparation method for FS-IGBT device Download PDFInfo
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Abstract
A preparation method for an FS-IGBT (Field Stop-Insulated-Gate Bipolar Transistor) device belongs to the technical field of power semiconductor devices. In the preparation method, N-type impurity injection is performed on a substrate to form a field stop layer, then an epitaxial layer is generated, a front patterning is manufactured, then the back part is thinned, injection and annealing for a P-type collector region on the back part are performed, a manner of metalization on the back part is adopted to manufacture a field stop transistor, and impurities in the field stop layer can be activated fully. In addition, the preparation method can lead in an N-type transition region between the field stop layer and the P-type collector region by controlling thermal budget and back thinning positions, and the performance of the device can be improved.
Description
Technical field
The invention belongs to the power semiconductor technical field, relate to insulated gate bipolar transistor (IGBT), especially the preparation method of a cut-off type insulated gate bipolar transistor (FS-IGBT).
Background technology
Power semiconductor technologies is the core of power electronic technology, and along with the development of microelectric technique, the gated power device is that the modern power semiconductor technologies of representative obtained developing rapidly from the eighties in 20th century, and then has greatly promoted the progress of power electronic technology.
Power MOS pipe is a voltage-controlled device, can come the switch of control device through control-grid voltage, and driving circuit structure is simple, and the single carrier conductive characteristic makes its switching characteristic excellent.Yet how sub-device can't produce conductivity modulation effect in the drift region, is not suitable for being applied in the high pressure field.Press powerful power electronic device to form the technical market that GTO, IGCT, IGBT, IEGT vie each other and constantly bring forth new ideas at present.IGBT compares with GTO, through device grid terminal voltage control device switch, makes drive circuit simple, and IGBT compares with MOS, and conductivity modulation effect can reduce forward conduction voltage drop, makes static power consumption less.Thereby IGBT has occupied the very big market share in mesohigh is used.
Since the nineties in last century, through constantly development, IGBT makes and has stepped into maturation in the world, and the IGBT voltage range of commercial production contains from 370V to 6500V at present, and electric current does not wait from 2A to 4000A, and form comprises single tube and module.Above structure, IGBT has experienced PT (punch), NPT (non-punch) and FS (cut-off type) on longitudinal electric field distributes, on channel structure, mainly contain Planer (plane) and Trench (groove-shaped).
First generation PT (punch) utilization P+ type CZ silicon chip is a substrate, and extension N-layer is as the drift region, because substrate P+ collector electrode doping content is very high, emission effciency is excessive, causes hangover time long, and turn-off power loss can't be accepted.Thereby PT type IGBT need use the carrier lifetime control technology to reduce carrier lifetime, reduces turn-off power loss, but this method can make device demonstrate the voltage negative temperature coefficient, can't parallel connection use.NPT type IGBT uses the FZ silicon chip, lets substrate directly as the drift region, uses the transparent anode technology, has the characteristics of low emission effciency, thereby has removed the control technology in useful life from, makes device have the positive temperature coefficient of voltage.This makes IGBT parallel connection to use, and has significantly expanded the range of application of device.But NPT-IGBT has the bigger shortcoming of forward conduction voltage drop because the drift region is long.FS-IGBT utilizes N type field cutoff layer to make Electric Field Distribution transfer a type trapezoidal profile to by the triangle distribution of NPT type, has shortened the thickness of device, has significantly reduced the conduction voltage drop and the loss of device.But this has increased difficulty to technology, and positive technology is done in employing earlier usually at present, and the mode that back thin slice back is annotated is introduced the FS layer, owing to will protect the front metal figure, annealing temperature can not be too high, and impurity activation this moment rate is very low, influences device performance.Part producer adopts the mode of laser annealing to solve this problem, though this advanced person's technology can solve the low excessively problem of impurity activation rate, impurity is advanced; And because the restriction of wavelength; The annealing degree of depth has certain limitation, can only obtain the thin FS layer of one deck in the collector region place at the back, and this FS layer can't make the withstand voltage level of device reach maximum; Thin in addition FS layer can impact the reliability of device, is easy to generate vibration during shutoff.
Summary of the invention
The present invention provides a kind of FS-IGBT preparation of devices method; This method directly on silicon substrate, injects N type impurity and annealing forms a cutoff layer, and growing epitaxial uses epitaxial loayer as the drift region then; And at epi-layer surface making device surfacial pattern; Back attenuate silicon chip then, back inject p type impurity and annealing forms P type collector region, and last back metallization forms the metallization collector electrode.This technical process can avoid the use of wafer processes technology, under the prerequisite that guarantees the silicon chip integrality, has reduced technology difficulty.The activation of field, back cutoff layer impurity need not to use laser annealing, has reduced the requirement of technical process to equipment, has practiced thrift cost.In addition, this technical process can be adjusted the position of FS layer according to back attenuate degree, obtains more excellent device performance.
Technical scheme of the present invention is following:
A kind of FS-IGBT preparation of devices method, as shown in Figure 2, may further comprise the steps:
Step 1: choose Semiconductor substrate;
Step 2: remove the semiconductor substrate surface oxide layer and inject N type impurity and a high temperature knot formation cutoff layer (FS layer);
Step 3: grown epitaxial layer;
Step 4: in epitaxial loayer, make the required Facad structure of IGBT device;
Step 5: Semiconductor substrate thinning back side;
Step 6: p type impurity is injected at the Semiconductor substrate back side and the high temperature knot forms P type collector region;
Step 7: back metallization forms the metallization collector electrode.
FS-IGBT preparation of devices method provided by the invention and existing FS-IGBT preparation of devices method difference are:
Positive technology is done in the common employing of existing FS-IGBT preparation of devices method earlier; The mode annotated of back thin slice back is introduced the FS layer then, owing to will protect the front metal figure, annealing temperature can not too high (generally being no more than 460 ℃); Under this process annealing condition; The impurity that injects the FS layer not only can't knot and also activity ratio very low, and activity ratio receives influence of temperature change very big, these problems can have a strong impact on the overall performance of device.Though part producer adopts the mode of laser annealing to solve this problem,, impurity is advanced though this advanced person's technology can solve the low excessively problem of impurity activation rate; And because the restriction of wavelength; The annealing degree of depth has certain limitation, can only obtain the thin FS layer of one deck in the collector region place at the back, and this FS layer can't make the withstand voltage level of device reach maximum; Thin in addition FS layer can impact the reliability of device, is easy to generate vibration during shutoff.
The present invention at first made the FS layer on silicon substrate before making the device front description, because front description is not made as yet, for the implanted dopant of FS layer, can adopt high-temperature annealing process to obtain the FS layer of desired thickness and position and high activity ratio.
What need further specify is:
1, a cutoff layer implanted dopant can be phosphorus, arsenic or other has the impurity of donor level.
2, the high temperature knot condition of a cutoff layer will be considered front process heat budget.
3, need be during outer layer growth according to the thickness and the doping content of the parameter adjustment epitaxial loayer of making device.
When 4, in epitaxial loayer, making the required Facad structure of IGBT device, comprise grid structure, and grid structure can be planar gate structure, trench gate structure, also can be to be the grid structure that buried regions is contained on the basis with planar gate or trench gate.
5, the spacing of back substrate thinning thickness and attenuate back court cutoff layer and back P type collector region can change according to design requirement.
6, said Semiconductor substrate can adopt silicon (Si), carborundum (SiC), GaAs (GaAs) or gallium nitride (GaN) etc.
Go into shown in Figure 12ly, through Medici emulation, we can find if the position of FS layer next-door neighbour P type collector region, and device performance is relatively poor, and withstand voltage have only 1573V, along with the increasing of FS layer and P+ collector region distance, withstand voltagely reduce after increasing to maximum.In addition, bigger spacing provides extra charge carrier in the time of oppositely recovering for the FS-IGBT device, obtains softer recovery characteristics, avoids the generation of vibrating in the reversely restoring process, helps improving the reliability of device.Yet it is shown in figure 13 to utilize Tsuprem4 software to obtain the distribution that traditional handicraft phosphorus injects, and projector distance can't satisfy the requirement of buried FS layer, and the FS layer thickness that obtains is very thin.In the method, can fully activate FS layer impurity through high temperature knot process, control back thickness thinning is adjusted the position of back P type collector region, thereby can obtain buried FS layer through heat budget that calculates the FS layer and the thickness of accurately controlling the back attenuate.
In sum, the present invention provides a kind of FS-IGBT preparation of devices method, and this method directly on silicon substrate, injects N type impurity and annealing forms a cutoff layer; Growing epitaxial then; Use epitaxial loayer as the drift region, and make device surfacial pattern, back attenuate silicon chip then in epi-layer surface; P type impurity is injected at the back and annealing forms P type collector region, and last back metallization forms the metallization collector electrode.This technical process can avoid the use of wafer processes technology, under the prerequisite that guarantees the silicon chip integrality, has reduced technology difficulty.The activation of field, back cutoff layer impurity need not to use laser annealing, has reduced the requirement of technical process to equipment, has practiced thrift cost.In addition, this technical process can be adjusted the position of FS layer according to back attenuate degree, obtains more excellent device performance.
Description of drawings
Fig. 1 is typical process flow figure of the present invention.
Fig. 2 is device architecture sketch map in the part technical process of the present invention to Figure 11.
Figure 12 is the simulation result figure of P type collector region with the size and the device withstand voltage relation of FS interlamellar spacing.Wherein transverse axis is represented P type collector region with the FS interlamellar spacing, and the longitudinal axis is represented the device withstand voltage size.
Figure 13 is an ion implantation technology, is 1E12/cm at implantation dosage
2The time, under the different injection energy conditions, impurity profile.
Embodiment
A kind of manufacture method of power device is an example with groove field cut-off type insulated gate bipolar transistor, comprises and chooses silicon chip, removes surface oxide layer; Inject N type impurity and high temperature knot and form the FS layer, grown epitaxial layer, growth field oxide, photoetching active area and field limiting ring terminal; Growth scattering oxide layer is also injected boron, etches away the scattering oxide layer and the knot of annealing, the photoetching emitter region, and growth scattering oxide layer is also injected N type impurity; Remove the scattering oxide layer and the knot of annealing, remove oxide layer and deposited silicon nitride, photoetching groove district also etches the Trench groove, the growth gate oxide; Fill polycrystalline, etched portions polycrystalline and planarization, the polycrystalline oxidation is also removed silicon nitride; Deposit passivation layer is carried out ohmic contact and is injected, deposition front metal and etching front metal figure behind the lithography contact hole; The back attenuate, boron and knot, back metallization are injected in the back.
Except that the cut-off type structure of groove field, this method can also be used for the making of flat field cut-off type structure.
At the back during attenuate, to inject P type collector region behind the FS layer and can obtain structure as shown in Figure 6 if be thinned to, this moment, P type collector region was close to the FS layer.When arriving apart from FS layer certain thickness, inject P type collector region, can between P type collector region and FS layer, obtain N type transition region 13 through the control thickness thinning, as shown in Figure 7.
To sum up, this method not only can also be controlled the position of FS layer so that FS layer impurity fully activates, obtain performance better during.
Claims (6)
1. FS-IGBT preparation of devices method may further comprise the steps:
Step 1: choose Semiconductor substrate;
Step 2: remove the semiconductor substrate surface oxide layer and inject N type impurity and a high temperature knot formation cutoff layer;
Step 3: grown epitaxial layer;
Step 4: in epitaxial loayer, make the required Facad structure of IGBT device;
Step 5: Semiconductor substrate thinning back side;
Step 6: p type impurity is injected at the Semiconductor substrate back side and the high temperature knot forms P type collector region;
Step 7: back metallization forms the metallization collector electrode.
2. a kind of FS-IGBT preparation of devices method according to claim 1 is characterized in that, the N type impurity that step 2 is injected is that phosphorus, arsenic or other have the impurity of donor level.
3. a kind of FS-IGBT preparation of devices method according to claim 1 is characterized in that, need be according to the thickness and the doping content of the parameter adjustment epitaxial loayer of making device during step 3 outer layer growth.
4. a kind of FS-IGBT preparation of devices method according to claim 1; It is characterized in that; When step 4 is made the required Facad structure of IGBT device in epitaxial loayer; Comprise grid structure, and grid structure is planar gate structure, trench gate structure, or is the grid structure that buried regions is contained on the basis with planar gate or trench gate.
5. a kind of FS-IGBT preparation of devices method according to claim 1 is characterized in that, the spacing of step 5 back substrate thinning thickness and attenuate back court cutoff layer and back P type collector region can change according to design requirement.
6. a kind of FS-IGBT preparation of devices method according to claim 1 is characterized in that said Semiconductor substrate can adopt silicon, carborundum, GaAs or gallium nitride.
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Cited By (23)
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| CN103137473A (en) * | 2011-12-02 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method of manufacturing field termination type insulated gate bipolar translator (IGBT) component with substrate provided with outward-extending layer |
| CN103268860A (en) * | 2013-04-03 | 2013-08-28 | 吴宗宪 | Manufacturing method of IGBT (insulated gate bipolar transistor) device integrated with diode |
| CN103441074A (en) * | 2013-08-30 | 2013-12-11 | 吴宗宪 | Method for manufacturing IGBT device integrated with diode |
| CN103489776A (en) * | 2013-09-18 | 2014-01-01 | 中国东方电气集团有限公司 | Method for achieving process of field-stop type insulated gate bipolar transistor |
| CN103578959A (en) * | 2013-11-19 | 2014-02-12 | 电子科技大学 | Manufacturing method of anode of FS-IGBT device |
| CN103871852A (en) * | 2012-12-14 | 2014-06-18 | 中国科学院微电子研究所 | Manufacture method of PT type power device with FS layers |
| CN103928309A (en) * | 2014-04-21 | 2014-07-16 | 西安电子科技大学 | Method for manufacturing N-channel silicon carbide insulated gate bipolar transistor |
| WO2014206177A1 (en) * | 2013-06-25 | 2014-12-31 | 无锡华润上华半导体有限公司 | Method for preparing insulated gate bipolar transistor of trench fs structure |
| CN104269357A (en) * | 2013-03-26 | 2015-01-07 | 杭州士兰集成电路有限公司 | Power semiconductor device and manufacturing method thereof |
| CN104282555A (en) * | 2013-07-11 | 2015-01-14 | 无锡华润上华半导体有限公司 | Manufacturing method for insulated gate bipolar transistor |
| CN104299900A (en) * | 2013-07-15 | 2015-01-21 | 无锡华润上华半导体有限公司 | Method for manufacturing field cut-off type insulated gate bipolar transistor |
| WO2015014263A1 (en) * | 2013-07-29 | 2015-02-05 | 无锡华润上华半导体有限公司 | Igbt manufacturing method |
| WO2015014289A1 (en) * | 2013-07-31 | 2015-02-05 | 无锡华润上华半导体有限公司 | Insulated-gate bipolar transistor manufacturing method |
| WO2015027621A1 (en) * | 2013-08-30 | 2015-03-05 | 国家电网公司 | Method for manufacturing field stop igbt device |
| CN104425251A (en) * | 2013-08-30 | 2015-03-18 | 无锡华润上华半导体有限公司 | Manufacturing method of reverse conduction FS IGBT (field stop insulated gate bipolar transistor) |
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| CN103871852B (en) * | 2012-12-14 | 2018-01-30 | 中国科学院微电子研究所 | A kind of preparation method of the PT type power devices of band FS layers |
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