CN102403279B - 功率半导体芯片封装 - Google Patents

功率半导体芯片封装 Download PDF

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Publication number
CN102403279B
CN102403279B CN201110267260.1A CN201110267260A CN102403279B CN 102403279 B CN102403279 B CN 102403279B CN 201110267260 A CN201110267260 A CN 201110267260A CN 102403279 B CN102403279 B CN 102403279B
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power semiconductor
semiconductor chip
thickness
contact pad
epitaxial loayer
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CN102403279A (zh
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R.奥特伦巴
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及功率半导体芯片封装。一种器件包括具有外延层和体半导体层的竖直功率半导体芯片。第一接触焊盘布置于功率半导体芯片的第一主要面上，而第二接触焊盘布置于功率半导体芯片的与第一主要面相对的第二主要面上。该器件还包括附着到第二接触焊盘的导电载体。

Description

功率半导体芯片封装
技术领域
本发明一般涉及半导体芯片封装并且更具体地涉及功率半导体芯片的封装。
背景技术
半导体器件制造商持续致力于增加它们的产品的性能同时减少它们的制造成本。在半导体器件制造中的成本密集区是封装半导体芯片。如本领域技术人员所知，在晶片中制作集成电路，然后切分晶片以生产半导体芯片。一个或者多个半导体芯片放置于封装中以保护它们免受环境和物理影响从而保证可靠性和性能。封装半导体芯片增加制造半导体器件的成本和复杂性，因为封装设计应当不仅提供保护而且它们也应当允许向和从半导体芯片发送电信号。
附图说明
包括附图以提供对实施例的进一步理解，并且附图并入于本说明书中并且构成本说明书的部分。附图图示了实施例并且与描述一起用于说明实施例的原理。其它实施例和实施例的许多预计优点将在它们通过参照以下具体描述而变得更好理解时容易得到认识。附图的元件未必相对于彼此按比例绘制。相似参考标号表示对应的类似部分。
图1是半导体器件的一个实施例的横截面图，该半导体器件包括装配于导电载体上的功率半导体芯片；
图2是图1的功率半导体器件的简化图示，示出了载体在功率半导体芯片上施加的张应力；
图3是根据图1中所示的实施例的一个具体实施例的横截面图；
图4是图示了针对如图3中所示的载体上在应力加载条件下装配的相同功率半导体芯片的总体（ensemble）和针对在无外部张应力下操作的相同功率半导体芯片的总体的接通电阻概率分布的图；
图5是一个实施例的横截面图，该实施例包括在嵌入功率半导体芯片的封装体中封装的图1的半导体器件；
图6是一个实施例的横截面图，该实施例包括在嵌入功率半导体芯片和载体的封装体中封装的图1的半导体器件；
图7是图示了针对各种厚度的功率半导体芯片的、以Mpa为单位的张应力比对以mm2为单位的芯片面积的图；
图8是在封装体50中封装的图2的半导体器件的图示，示出了由于封装工艺而在功率半导体芯片的上主要面（mainface）上施加的张应力的减轻和向下压力的增强；并且
图9是图示了针对各种厚度的功率半导体芯片的、以μm为单位的芯片翘曲（warpage）比对以mm2为单位的芯片面积的图。
具体实施方式
在以下具体描述中参照附图，这些附图形成该描述的部分并且在这些附图中通过图示方式示出了其中可以实现本发明的具体实施例。就这一点而言，参照描述的（一个或多个）附图的定向来使用诸如“顶部”、“底部”、“前”、“后”、“前导”、“尾随”等的方向术语。由于实施例的部件可以定位于多个不同定向上，所以方向术语用于图示而决非限制的目的。将理解可以利用其它实施例并且可以做出结构或逻辑改变而不脱离本发明的范围。以下具体描述因此将不理解为限制意义，并且本发明的范围由所附权利要求限定。
将理解除非另有具体声明，这里描述的各种示例性实施例的特征可以相互组合。
如在本说明书中采用的，术语“耦合”和/或“电耦合”并不打算意味着元件必须直接耦合在一起——可以在“耦合”或“电耦合”的元件之间提供居间元件。
下面描述包含功率半导体芯片的器件。功率半导体芯片可以有不同类型、可以通过不同技术来制造并且可以例如包括集成电、光电或者机电电路或者无源电路（passive）。功率半导体芯片无需由具体半导体材料例如Si、SiC、SiGe、GaAs制造并且另外可以包含并非是半导体的无机和/或有机材料（诸如例如分立无源电路、天线、绝缘体、塑料或者金属）。另外，下面描述的器件可以包括更多集成电路以控制功率半导体芯片的功率集成电路。
功率半导体芯片可以包括功率MOSFET（金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极晶体管）、JFET（结栅场效应晶体管）、功率双极晶体管或者功率二极管。具体而言，涉及到具有竖直结构的功率半导体芯片，也就是说，以电流可以在与功率半导体芯片的主要面垂直的方向上流动的这样的方式制作功率半导体芯片。
具有竖直结构的功率半导体芯片可以在它的两个主要面上（也就是说，在它的顶侧和底侧上）具有接触焊盘。举例而言，功率MOSFET的源极电极和栅极电极可以处于一个主要面上，而功率MOSFET的漏极电极可以布置于另一主要面上。接触焊盘可以由铝、铜或者任何其它适当材料制成。可以向功率半导体芯片的接触焊盘施加一个或者多个金属层。金属层可以例如由钛、镍钒、金、银、铜、钯、铂、镍、铬或者任何其它适当材料制成。金属层无需同质或者由仅一种材料制造，也就是说，在金属层中包含的材料的各种组成和浓度是可能的。
功率半导体芯片可以由体半导体层和在体半导体层上生成的外延层制成。外延层可以具有比体半导体层的厚度更大的厚度。具体而言，外延层可以具有等于或者大于20μm、30μm、40μm或者50μm的厚度。通常，外延层的厚度越大，功率半导体芯片的操作电压就越高。体半导体层可以具有等于或者少于30μm、20μm或者15μm的厚度。
可以向功率半导体芯片施加导电载体。导电载体可以通过与功率半导体芯片的机械相互作用来明显影响功率半导体芯片的电性质。载体可以是引线框，即结构化的金属片。引线框可以具有等于或者大于1.0mm、1.5mm或者2.0mm的厚度以便在功率半导体芯片上施加机械应力。
封装材料可以至少部分覆盖功率半导体芯片以形成封装体。封装材料可以基于聚合物材料，也就是说，它可以包括由任何适当硬塑、热塑或者热固材料或者叠层（预浸渍制品）制成的基本材料（在以下中也称为基质材料）。具体而言，可以使用基于环氧树脂的基质材料。基质材料可以嵌入填充物材料（例如SiO2、Al2O3或者AlN颗粒）以调节封装体的物理性质，诸如例如弹性模量或者CTE（热膨胀系数）。
封装材料在它的沉积之后可能仅部分硬化并且可以然后通过施加能量（例如热、UV光等）来固化和/完全硬化以形成固体封装体。可以采用各种技术来通过封装材料形成封装体，例如压缩模制、转移模制、注入模制、粉末模制、液体模制、点胶（dispense）或者层压。热和/或压力可以用来施加封装材料。
封装体可以被设计成通过与功率半导体芯片的机械相互作用来明显影响功率半导体芯片的电性质。封装体可以具有等于或者大于50,000MPa的弹性模量和/或大到足以满足如下条件的芯片覆盖厚度（即在功率半导体芯片的上表面上的厚度）：芯片覆盖厚度与功率半导体芯片的厚度、连接层的厚度和导电载体的厚度的总和的比值等于或者大于3以便在功率半导体芯片上施加压缩或者向下压力。
图1在横截面中示意地图示了功率器件100。器件100包括功率半导体芯片10。功率半导体芯片10具有在功率半导体芯片10的第一主要面12上布置的一个或者多个第一接触焊盘11并且具有在功率半导体芯片10的与第一主要面12相对的第二主要面14上布置的一个或者多个第二接触焊盘13。另外，功率器件100包括功率半导体芯片10装配于其上的载体20。
功率半导体芯片10是竖直器件，即电流可以在与功率半导体芯片10的主要面12、14垂直的方向上流动。在一个实施例中，功率半导体芯片10是功率晶体管，并且（一个或多个）第一接触焊盘11可以形成源极端子而（一个或多个）第二接触焊盘13可以形成漏极端子。在这一实施例中，栅极端子（未示出）通常布置于功率半导体芯片10的第一主要面12上。在其它实施例中，功率半导体芯片10可以是功率二极管，并且（一个或多个）第一接触焊盘11可以例如形成阳极端子而（一个或多个）第二接触焊盘13可以形成功率二极管的阴极端子，或者反之亦然。
更具体而言，功率半导体芯片10可以包括例如在体半导体层16上布置的外延层15。本领域技术人员非常了解用于生产这样的结构的多种半导体处理技术。简言之，可以在由半导体材料制成的晶片上制作功率半导体芯片10。晶片的上表面可以对应于图1中的体半导体层16的上表面。晶片（例如硅晶片）可以由适当杂质原子（掺杂物）掺杂以增强体半导体层16的半导体材料的电导率。举例而言，可以掺杂晶片以获得高电导率的n+掺杂体硅层16。
仍然在前端晶片处理期间，可以在晶片的上表面上生成外延层15。可以使用本领域技术人员所知的所有外延技术，例如MBE（分子束外延）、LPE（液相外延）等。外延层15被设计成包含p-n结序列以形成竖直功率器件的有源半导体区。
在外延层15的上表面12上形成（一个或多个）第一接触焊盘11。仍然可以在晶片处理期间、也就是在前端处理期间实现这一步骤。在其它实施例中，可以在将晶片分离成多个功率半导体芯片10之后在单个功率半导体芯片10上形成（一个或多个）第一接触焊盘11。
类似于（一个或多个）第一接触焊盘11，在对完整晶片的晶片处理期间或者在从晶片切分的功率半导体芯片10上形成（一个或多个）第二接触焊盘13。
可以经由接触焊盘11、13电接入集成功率电路和可能更多集成电路。接触焊盘11、13可以由金属例如铝或者铜制成并且可以具有任何期望的形状和尺寸。
可以在载体20的上表面上装配功率半导体芯片10。焊接材料（例如，例如包括AuSn和/或其它金属材料的扩散焊接材料）的连接层17可以用来将（一个或多个）第二接触焊盘13电连接和机械固定到载体20。
载体20可以有各种类型。在一个实施例中，载体20可以是图案化的金属片或者板，例如引线框。载体20可以包括相互由间距分离的金属板区。在另一实施例中，载体20可以是连续、非图案化的金属板或者片。可以通过压印和/或碾磨工艺来生产载体20。由其制成载体的金属可以例如包括铜、铝、镍、金、或者基于这些金属中的一种或者多种的任何合金的组中的一种或者多种金属。载体（例如引线框）可以由一个单体金属层或者多金属层结构制成。载体20可以用作用于耗散由功率半导体芯片10生成的热的散热器。
D1是在载体20与外延层15之间的距离、也就是在载体20的上表面与外延层15的开头（在图1中所示的例子中，外延层15的开头是在体硅层16与外延层15之间的过渡）之间的距离。距离D1是对载体20在功率半导体芯片10的外延层15上施加（exercise）的应力程度具有强影响的参数。通常，载体20的CTE和半导体芯片10的CTE明显不同。一般而言，载体20的CTE可以例如为功率半导体芯片10的CTE的5、6、7、8、9、10或者甚至更多倍。举例而言，由硅制成的功率半导体芯片10具有约2.55ppm的CTE，而由铜制成的典型引线框的CTE为约18ppm。因此，在焊接之后，由于载体20的收缩明显大于功率半导体芯片10的收缩，所以载体20（例如引线框）在功率半导体芯片10上施加高张应力。
在简化地示出了半导体芯片100的图2中图示了这一点。载体20的收缩由箭头“收缩”表示。在功率半导体芯片10上施加的张应力由箭头“张应力”表示。如图2中显然的，张应力在竖直方向上（也就是在与在水平方向上伸展的载体20的延伸基本上垂直的方向上）作用于功率半导体芯片10的***区。张应力伴随有翘曲，即迫使半导体器件10变成弓形或者凸形。在图2中，为了图示起见而夸大功率半导体芯片10和载体20的曲率。另外，虚线对应于功率半导体芯片10和载体20在焊接之前的直线延伸。
距离D1越短，作用于功率半导体芯片10的张应力就越大。根据实施例，已经发现：作用于外延层15的高张应力改进功率半导体芯片10的电性质。具体而言，通过增强作用于功率半导体芯片10的外延层15的外部张应力来明显减少功率半导体芯片10的接通状态电阻（Ron）。
换而言之，通过设计D1=50μm来向功率半导体芯片10的外延层15中选择性地引入张应力。另外，可以使用更小尺度，诸如D1=40μm或者30μm或者20μm或者甚至10μm。这与常规方式对照，在常规方式中使用大的D1尺度以便补偿不同CTE并且因此减少作用于功率半导体芯片10的张应力。
可以通过使用由易碎焊接材料（诸如例如基于AuSn的焊接材料）制成的连接层17来增强作用于外延层15的张应力。AuSn具有约59,000Mpa的高弹性模量。也可以使用其它无铅焊接材料。这与常规方式对照，在常规方式中使用可变形或者弹性接合材料（诸如基于Pb的导电粘合剂或者焊接材料）以便补偿不同CTE并且因此减少作用于半导体芯片10的张应力。
可以通过使用焊接材料的薄连接层17来增强作用于外延层15的张应力。例如，焊接材料的连接层17可以如10μm、5μm、2μm或者甚至1μm那样薄或者比此更薄。另外，第二接触焊盘13可以具有等于或者少于2μm或者甚至1μm的厚度。这与常规方式对照，在常规方式中使用明显厚度的连接层以便补偿不同CTE并且因此减少作用于半导体芯片10的张应力。
可以通过使用扩散焊接材料来增强作用于功率半导体芯片10的外延层15的张应力。扩散焊接材料（诸如例如AuSn、CuSn、AgSn）可以具有由至少两种焊料成分形成的金属间相。第一焊料成分具有比金属间相的熔点更低的熔点，而第二焊料成分具有比金属间相的熔点更高的熔点。此外，扩散焊料在它的扩散区中可以包括填充物材料的纳米颗粒，这可以防止在热机加载的情况下形成源于金属间相的微裂纹。扩散焊接材料所产生的连接是易碎的，可以具有如上文提到的高弹性模量并且可以如上文提到的那样薄。因此，用于连接层17的无铅扩散焊料连接高度适合于向功率半导体芯片10有效地施加由载体20所产生的张应力。
可以通过使用薄的体半导体层16来增强作用于外延层15的张应力。例如在一个实施例中，体半导体层16可以如30μm那样薄或者比此更薄，具体为20μm、15μm或者甚至10μm。这可以通过将晶片在它的底侧减薄以生成如下共同平面晶片表面来实现，该共同平面晶片表面包括功率半导体芯片10的第二主要面14。可以例如通过研磨或者抛光（lap）来实现减薄。尽管研磨工具使用磨轮，但是抛光工具使用如下流体（“浆”），该流体充有在两个表面之间作用的“滚动”磨蚀颗粒。例如可以应用CMP（化学机械抛光）。由于体半导体层16对半导体器件100的性能无影响（它向第二接触焊盘13简单地提供高度导电结），所以可以继续减薄晶片直至达到最小研磨厚度容限。在一个实施例中，体半导体层16可以如10μm、5μm或者甚至2μm那样薄或者比此更薄。这可以通过在晶片的底侧蚀刻它以生成如下共同平面晶片表面来实现，该共同平面晶片表面包括功率半导体芯片10的第二主要面14。由于体半导体层16对半导体器件100的性能无操作影响（除了向第二接触焊盘13提供高度导电结之外），所以可以继续蚀刻晶片直至达到最小蚀刻厚度容限。
使用这些方法中的一种或者多种方法，作用于外延层15的张应力可以设置成约数百Mpa，例如多于200Mpa、500Mpa或者甚至1000Mpa。甚至可以获得如一个或者多个GPa那样高的张应力。将注意张应力必须未超过断裂张应力，其例如对于操作电压约为500V的典型硅功率芯片而言约为5GPa。
将注意其它设计参数可以用来调节向外延层15施加的张应力程度。举例而言，载体20的厚度Dcar可以对张应力加载具有一些影响。根据一个方面，导电载体20的厚度Dcar与功率半导体芯片10的厚度Dchip、第二接触焊盘13的厚度Dpad和连接层17的厚度Dcon的总和的比值等于或者大于3，即：
Dcar/（Dchip+Dpad+Dcon）=3（1）。
这一比值甚至可以等于或者大于5，具体为7、更具体为10。载体20的厚度Dcar越大，将热运送出半导体器件100就越高效。
图3是根据图1中所示的实施例的一个具体示例性实施例的横截面图。图3中所示的半导体器件200是操作电压为600V的功率MOSFET。载体20是例如具有厚度Dcar=1.3mm的由铜制成的引线框。一般而言，Dcar可以等于或者大于1.0mm或者甚至2.0mm。连接层17由AuSn扩散焊料制成并且具有1.2μm的厚度。第二接触焊盘13包括由铝（Al）制成的下焊盘层13a、在下焊盘层13a之后并且由钛（Ti）制成的上焊盘层13b以及在上焊盘层13b之后并且由镍钒（NiV）制成的涂层13c。这些第二接触焊盘层13a、13b、13c可以例如具有约400nm（Al层）、400nm（Ti层）和75nm（NiV层）的厚度。因此，连接层17和第二接触焊盘13的总厚度Dcon+Dpad约如2.075μm那样小。如果期望的话，这一厚度Dcon+Dpad也可以容易减少成等于或者小于2.0μm。
继续图3，体半导体层16可以由n+掺杂硅制成并且可以具有约17.5μm的厚度Dbulk（见图1）。可以通过晶片研磨来获得这一厚度。掺杂体半导体层16可以实质上表现为金属。在体半导体层16与第二接触焊盘13的下焊盘层13a之间的退化半导体金属结也具有高电导率。体半导体层16和第二接触焊盘13代表功率MOSFET的漏极端子。
外延层15代表功率半导体芯片10的有源区。在这一例子中，它具有52.5μm的厚度Depi（见图1）从而允许约600V的操作电压。外延层15包括位于图3中的箭头p-n所指示的外延层的区域内的一连串p-n结。一般而言，外延层15可以具有等于或者大于20μm、具体等于或者大于30μm、更具体等于或者大于40μm或者具体等于或者大于50μm的厚度。作为经验法则，每100V的操作电压可能需要约9μm的外延层厚度。因此，竖直功率半导体芯片10可以具有等于或者大于200V、具体等于或者大于300V、更具体等于或者大于400V或者具体等于或者大于500V的操作电压。
在外延层15内提供高度导电插塞（plug）41。高度导电插塞41电连接到外延层15的p-n结以形成其源极接触。
导电插塞41由在外延层15的顶部上提供的第一绝缘层42（诸如例如氧化物层）覆盖。绝缘层42在图3中称为EOX并且配置成具有如下开口，经过这些开口可以接入导电插塞41。
第一结构化的金属层43可以布置于绝缘层42上。第一结构化的金属层43可以用于提供电功能，诸如例如功率MOSFET的静电屏蔽。另外，在图3的截面图中未示出的附加结构化的金属层可以布置于外延层15的上面12附近，例如用于提供附加连接性和/或信号路由的结构化的金属层（诸如例如用于形成外延层15的p-n结的栅极接触的结构化的金属层）。
第二结构化的绝缘层44诸如例如氧化物层可以布置于第一结构化的金属层43上。第二绝缘层44在图3中称为ZwOX，被配置成具有如下开口，经过这些开口第二金属层45可以电接触导电插塞41。第二金属层45可以例如由AlSiCu制成并且可以代表功率MOSFET的源极端子。另外，可以提供聚合物层46以覆盖第二金属层45。可以使用聚合物材料，诸如聚对二甲苯、光致抗蚀剂材料、酰亚胺、环氧树脂、硬塑料或者硅树脂。
举例而言，层42、43、44、45和46可以具有以下厚度尺度。第一绝缘层42可以具有2.4μm的厚度Dins1，第二绝缘层44可以具有1.5μm的厚度Dins2，第一金属层43可以具有5.0μm的厚度Dmet，并且聚合物层46可以具有6.0μm的厚度Dpoly。将注意这些层的尺度、材料和提供是示例性并且根据半导体设计的需求而经受变化。
图4是图示了针对如图3中所示的载体（引线框）20上装配的N个相同功率半导体芯片10的总体和针对在无张应力下操作的N个相同功率半导体芯片10的总体的Ron概率分布的图。x轴显示以毫欧姆（mohm）为单位的Ron，而y轴是按对数刻度绘制的范围从0至1的概率。图4图示了Ron对于应力加载的功率半导体芯片10（测量结果沿着线A显露）和在无外部应力的条件下的功率半导体芯片10（测量结果沿着线B显露）而言明显不同。尽管在无外部应力的条件下获得Ron=90毫欧姆的平均值，但是施加外部应力将接通状态电阻Ron减少至Ron=65毫欧姆的平均值。因此，在这一例子中，可以通过施加外部张应力来达到相对于65毫欧姆的目标值而言Ron平均减少38%。换而言之，在外延层15中的p-n结上施加外部应力明显增加外延层15中的电荷载流子迁移率。将注意图4还示范每个总体内的Ron标准偏差与在Ron的相应平均值之间的差相比是小的。因此，借助这里说明的机械测量和方法来形成外部张应力以及外部张应力对功率半导体芯片10的电性能的影响是清楚***性和高度可再现的结果。
图5示意地图示了一个实施例的半导体器件300的横截面图，其包括在嵌入功率半导体芯片10的封装体50中封装的图1的半导体器件100。封装体50也可以部分或者完全嵌入载体20。举例而言，在图5中所示的半导体器件300中，载体20在一个侧面22从封装体50突出并且在另一侧面21、上面23和与上面23相对的下面24由封装体50覆盖。
图6图示了根据一个实施例的半导体器件400的横截面图。除了载体20的下面24保持暴露（即未由封装体50覆盖）之外，半导体器件400类似于图5的半导体器件300。
封装体50可以由任何适当硬塑、热塑或者热固（基质）材料或者叠层（例如预浸渍制品（预浸渍纤维的简称））制成。具体而言，可以使用基于环氧树脂的（基质）材料。形成封装体50的电介质（基质）材料可以包含填充物材料。举例而言，填充物材料可以由小的玻璃颗粒（SiO2）或者其它电绝缘矿物填充物材料如Al2O3或者有机填充物材料构成。电介质材料在它的沉积之后可能仅部分硬化并且可以通过施加能量（例如热、UV光等）来完全硬化以形成封装体50。
可以采用各种技术来通过电介质材料形成封装体50，例如压缩模制、转移模制、注入模制、粉末模制、液体模制、点胶或者层压。例如，可以使用压缩模制。在压缩模制中，向打开的下半个模具（载体20和装配于其上的功率半导体芯片10放置于该半个模具中）中点胶液体模制材料。然后，在点胶液体模制材料之后，上半个模具被下移并且展开液体模制材料直至完全填充在下半个模具与上半个模具之间形成的腔。这一工艺可以伴随有施加热和压力。
图7是图示了针对在焊接之后（实线）和在封装之后（虚线）的50、100、150、220和315μm各种厚度的功率半导体芯片的、以Mpa为单位的张应力比对以mm2为单位的芯片面积的图。作为第一结果，发现张应力仅略微依赖于芯片面积。因此认为所有尺寸的半导体芯片受益于上文说明的原理。作为第二结果，张应力随着芯片厚度增加而明显增强。因此，功率半导体芯片越厚，通过施加外部应力而引起的电效果（电荷载流子迁移率增加）就越显著。另外作为第三结果，图7指示可以通过封装来明显减少张应力。下面更具体地考虑这一方面。
根据另一方面，封装体50可以用来向功率半导体芯片10的外延层15施加应力。为此，封装体50的封装材料可以具有等于或者大于50,000Mpa的弹性模量。
通过使用由弹性模量等于或者大于50,000MPa的封装材料制成的封装体50，作用于功率半导体芯片10的应力明显受封装体50而不是受载体20影响或者甚至受其支配。
图8图示了当在封装体50中封装半导体芯片10时在半导体器件（诸如例如图5的器件300）中作用的力。图8图示了由于封装工艺而作用于功率半导体芯片10的张应力的减轻和向下压力的增强。更具体而言，如图8中所指示，功率半导体芯片10由于载体20在焊接之后收缩所致的翘曲被封装体50在硬化期间的收缩所抵消并且由此减少。同时，封装体50在硬化期间的收缩使封装体50在功率半导体芯片10的上主要面12上生成向下压力。两种效果（翘曲和张应力的减少以及向下压力的增强）强依赖于封装体50的封装材料的弹性模量。封装体50的封装材料的弹性模量越大，（固化的）封装材料在功率半导体芯片10的上主要芯片面12上施加的翘曲和张应力的减少以及向下压力的增强就越大。一般而言，封装材料的弹性模量甚至可以等于或者大于60,000MPa、具体等于或者大于70,000Mpa或者等于或者大于80,000MPa。这可以通过向封装材料添加填充物材料来实现，填充物材料在封装材料中的百分比可以等于或者大于80vol%（体积百分比）、具体等于或者大于85vol%。与在图8中示例的相同的原理适用于图6中所示的半导体器件400。
简言之，封装体50将张应力转换成向下压力，而转换效率随着封装材料的弹性模量而增加。已经发现在功率半导体芯片10的上主要面12上施加外部压力将接通状态电阻Ron减少至与和相同翘曲（该翘曲是针对给定芯片厚度的张应力的测量）但是在功率半导体芯片10的上主要面12上的更低外部压力关联的Ron值相比明显更低的值。因此，提供由等于或者大于50,000MPa的弹性模量制成的封装材料允许减少翘曲（并且因此减少张应力）并且可以同时改进功率半导体芯片10的电性能。
图9是图示了针对50μm、100μm、150μm、220μm和315μm各种厚度的功率半导体芯片的、以μm为单位的芯片翘曲比对以mm2为单位的芯片面积的图。实线对应于在焊接之后的芯片翘曲，而虚线对应于在封装之后的（减少的）芯片翘曲。将注意针对所有芯片面积通过封装来减少芯片翘曲。芯片翘曲在封装之后的减少随着芯片面积而增加。另外，芯片翘曲随着芯片厚度而略微减少。注意作用于功率半导体芯片10的外部张应力针对给定芯片厚度仅依赖于翘曲。
表1涉及设计与图3中所示的半导体器件或者封装200的设计类似的称为封装P-SOT223-4的半导体器件。因此，为了避免重复，参照半导体器件200。
表1-封装材料的机械性质
如在表1中所指示，封装体50的封装材料可以具有约13,000MPa的弹性模量。这是本领域中常用的封装材料的典型弹性模量值。由于这一值相对于封装的其它部分的弹性模量而言是比较小的（见表1），所以封装体对作用于功率半导体芯片的力的贡献可能是小的。因此，可能获得高翘曲和高张应力。另一方面，根据上文说明的方面，可以例如通过添加填充物材料或者通过用具有这样的高弹性模量的封装材料取代KMC180-7（见表1）而将封装体50的封装材料的弹性模量设置为如约50,000MPa那样高或者更多。在这一情况下，减少翘曲和张应力（见图9）。然而如上文说明的那样，借助增强在功率半导体芯片10的上主要面12上施加向下压力来仍然维持或者甚至降低Ron的低值。
使用由弹性模量等于或者大于50,000MPa的封装材料制成的封装体50的概念可以与这里结合其它实施例提到的所有方法和测量组合。具体而言，可以使用由易碎焊接材料（诸如例如基于AuSn的焊接材料）制成的连接层17。可以使用例如基于AuSn的扩散焊接材料，并且该材料可以具有约59,000MPa的高弹性模量（见表1）。
举例而言，在表1中示例的封装P-SOT223-4使用在载体20上的厚度为1mm的封装体50，其中载体20是厚度为250μm的镀银的铜引线框。采用由弹性模量等于或者大于50,000MPa的封装材料制成的封装体明显减少封装的翘曲同时允许低的Ron值。因此，应用具有这样的高弹性模量的封装材料可以有助于限制翘曲同时改进（或者至少未负面地影响）低Ron特性。
在一些实施例中，例如见图5或者图6，在功率半导体芯片10的上表面12与封装体50的上表面51之间的距离Denc与功率半导体芯片10的厚度Dchip、第二接触焊盘13的厚度Dpad、连接层17的厚度Dcon和导电载体20的厚度Dcar的总和的比值等于或者大于3，即：
Denc/（Dchip+Dpad+Dcon+Dcar）=3（2）。
这一比值甚至可以等于或者大于5，具体为6、更具体为7。
如果满足条件（2），则通常将大量张应力转换成作用于功率半导体芯片10的压缩（也就是向下压力）。已经结合前述实施例说明了这一转换对Ron的有益效果。不同于前述实施例（其中效果主要由封装材料的高弹性模量引起），效果在这里主要由根据条件（2）的几何设计约束（例如由封装体50在功率半导体芯片10的上面12上的明显厚度Denc）引起。将注意在本领域中，在条件（2）中限定的比值在发明人的最佳理解之下总是明显小于3。
当然，可以组合上文说明的用于将外部张应力高效转换成外部向下压力的两种方法，也就是可以组合使用尺度设成满足条件（2）并且由具有高弹性模量（例如弹性模量=50,000MPa或者更多）的封装材料制成的封装体50。
在一种制造半导体器件的方法的一个实施例中，首先提供具有外延层15和体半导体层16的竖直功率半导体芯片10。功率半导体芯片10具有在功率半导体芯片10的第一主要面12上布置的第一接触焊盘11和在功率半导体芯片10的与第一主要面12相对的第二主要面14上布置的第二接触焊盘13。
然后，竖直功率半导体芯片10装配于导电载体20上，该载体由此附着到第二接触焊盘13。如上文提到的那样，在导电载体20与外延层15之间的距离可以少于50μm和/或可以满足条件（1）。
另外，功率半导体芯片10并且可选载体20可以嵌入于形成封装体50的封装材料中。可以例如通过模制、点胶或者层压技术来实现封装。
封装材料可以具有低弹性模量或者可以不满足条件（2）。在这些情况下，封装材料可以不明显影响或者支配作用于功率半导体芯片10的力。另一方面，如上文提到的那样，封装材料可以具有等于或者大于50,000MPa的弹性模量和/或可以满足条件（2）。在这一情况下，减少芯片翘曲并且将张应力转换成由封装体50在功率半导体芯片10的外延层15上施加的向下芯片压力。
此外，尽管关于若干实施方式中的仅一种实施方式公开了本发明实施例的具体特征或方面，但是这样的特征或者方面可以如对于任何给定或者具体应用而言可能期望和有利的那样与其它实施方式的一个或者多个其它特征或者方面组合。另外，就术语“包括”、“具有”、“带有”或者它们的其它变体在具体描述或者权利要求中使用来说，这样的术语旨在以与术语“包括”类似的方式是包含的。另外，应当理解可以用分立电路、部分集成电路或者完全集成电路或者编程装置来实施本发明的实施例。术语“示例性”也仅意味着作为例子而不是最佳或者最优的。也将认识到：为了简化和易于理解的目的，用相对于彼此的具体尺度图示这里描绘的特征和/或元件，并且实际尺度可以明显不同于这里图示的尺度。
虽然这里图示和描述了具体实施例，但是本领域普通技术人员将认识到各种替代和/或等效实施方式可以取代示出和描述的具体实施例而不脱离本发明的范围。本申请旨在覆盖这里讨论的具体实施例的任何适配或者变化。因此，旨在让本发明仅受权利要求及其等效物限制。

Claims (23)

1.一种功率半导体器件，包括：
竖直功率半导体芯片，具有外延层和体半导体层，
第一接触焊盘，布置于所述功率半导体芯片的第一主要面上，
第二接触焊盘，布置于所述功率半导体芯片的第二主要面上，所述第二主要面与所述第一主要面相对，
导电载体，以增强作用于所述外延层的张应力的方式附着到所述第二接触焊盘，以及
连接层，位于所述第二接触焊盘与所述导电载体之间，
其中在所述导电载体与所述外延层之间的距离等于或者少于50μm并且大于30μm并且连接层比体半导体层薄。
2.根据权利要求1所述的功率半导体器件，还包括：
其中所述连接层具有等于或者少于10μm的厚度。
3.根据权利要求2所述的功率半导体器件，其中所述连接层包括扩散焊接材料。
4.根据权利要求1所述的功率半导体器件，其中所述体半导体层具有等于或者少于30μm的厚度。
5.根据权利要求1所述的功率半导体器件，其中所述外延层具有等于或者大于20μm的厚度。
6.根据权利要求1所述的功率半导体器件，其中所述功率半导体芯片是操作电压等于或者大于200V的竖直功率晶体管。
7.一种功率半导体器件，包括：
竖直功率半导体芯片，具有外延层和体半导体层，
第一接触焊盘，布置于所述功率半导体芯片的第一主要面上，
第二接触焊盘，布置于所述功率半导体芯片的与所述第一主要面相对的第二主要面上，
导电载体，以及
连接层，以增强作用于所述外延层的张应力的方式位于所述第二接触焊盘与所述导电载体之间，其中所述导电载体的厚度与所述功率半导体芯片的厚度、所述第二接触焊盘的厚度和所述连接层的厚度的总和的比值等于或者大于3；并且其中在所述导电载体与所述外延层之间的距离等于或者少于50μm并且大于30μm并且连接层比体半导体层薄。
8.根据权利要求7所述的功率半导体器件，其中所述比值等于或者大于5。
9.根据权利要求7所述的功率半导体器件，其中所述连接层具有等于或者少于10μm的厚度。
10.根据权利要求7所述的功率半导体器件，其中所述导电载体具有等于或者大于1.0mm的厚度。
11.根据权利要求7所述的功率半导体器件，其中所述功率半导体芯片是操作电压等于或者大于200V的竖直功率晶体管。
12.一种功率半导体器件，包括：
竖直功率半导体芯片，具有外延层和体半导体层，
第一接触焊盘，布置于所述功率半导体芯片的第一主要面上，
第二接触焊盘，布置于所述功率半导体芯片的与所述第一主要面相对的第二主要面上，
导电载体，以增强作用于所述外延层的张应力的方式附着到所述第二接触焊盘，
连接层，位于所述第二接触焊盘与所述导电载体之间，以及
封装体，包括覆盖所述功率半导体芯片的封装材料，其中所述封装材料具有等于或者大于50,000MPa的弹性模量；并且其中在所述导电载体与所述外延层之间的距离等于或者少于50μm并且大于30μm并且连接层比体半导体层薄。
13.根据权利要求12所述的功率半导体器件，其中所述封装材料的弹性模量等于或者大于60,000MPa。
14.根据权利要求12所述的功率半导体器件，还包括：
其中所述连接层的材料的弹性模量等于或者大于50,000MPa。
15.根据权利要求12所述的功率半导体器件，其中所述封装材料包括填充物材料，填充物材料在所述封装材料中的百分比等于或者大于80vol%。
16.根据权利要求12所述的功率半导体器件，其中所述功率半导体芯片是操作电压等于或者大于200V的竖直功率晶体管。
17.一种功率半导体器件，包括：
竖直功率半导体芯片，具有外延层和体半导体层，
第一接触焊盘，布置于所述功率半导体芯片的第一主要面上，
第二接触焊盘，布置于所述功率半导体芯片的与所述第一主要面相对的第二主要面上，
导电载体，
连接层，以增强作用于所述外延层的张应力的方式位于所述第二接触焊盘与所述导电载体之间，以及
封装体，包括覆盖所述功率半导体芯片的封装材料，其中在所述功率半导体芯片的上表面与所述封装体的上表面之间的距离与所述功率半导体芯片的厚度、所述第二接触焊盘的厚度、所述连接层的厚度和所述导电载体的厚度的总和的比值等于或者大于3；并且其中在所述导电载体与所述外延层之间的距离等于或者少于50μm并且大于30μm并且连接层比体半导体层薄。
18.根据权利要求17所述的功率半导体器件，其中所述比值等于或者大于5。
19.一种制造功率半导体器件的方法，所述方法包括：
提供具有外延层和体半导体层的竖直功率半导体芯片，
提供在所述功率半导体芯片的第一主要面上布置的第一接触焊盘，
提供在所述功率半导体芯片的与所述第一主要面相对的第二主要面上布置的第二接触焊盘，并且
在附着到所述第二接触焊盘的导电载体上以增强作用于所述外延层的张应力的方式装配所述竖直功率半导体芯片，
在所述第二接触焊盘与所述导电载体之间施加连接层，其中在所述导电载体与所述外延层之间的距离少于50μm并且大于30μm并且连接层比体半导体层薄。
20.根据权利要求19所述的方法，还包括：
所述连接层具有等于或者少于10μm的厚度。
21.根据权利要求19所述的方法，其中所述体半导体层具有等于或者少于30μm的厚度。
22.根据权利要求19所述的方法，其中所述外延层具有等于或者大于20μm的厚度。
23.根据权利要求19所述的方法，其中所述导电载体的厚度与所述功率半导体芯片的厚度、所述第二接触焊盘的厚度和所述连接层的厚度的总和的比值等于或者大于3。
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US20130295724A1 (en) 2013-11-07
US20120061812A1 (en) 2012-03-15
DE102011053362A1 (de) 2012-03-15
CN102403279A (zh) 2012-04-04
US8513798B2 (en) 2013-08-20

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