CN102346236B - Time parameter measurement system - Google Patents

Abstract

The invention discloses a time parameter measurement system for digital integrated circuits. The system is implemented by converting a to-be-measured signal IN into a time interval start signal Start and a stop signal Stop as well as pulse signals RStart and RStop by a channel circuit unit; then, the four signals are respectively provided for an accurate time measurement unit and a coarse time measurement unit to carry out measurement, wherein the accurate time measurement unit is composed of a multi-stage delay line and a calibration unit, and used for carrying out measurement under the condition that the rising edge of the to-be-measured signal is steep; and the coarse time measurement unit is composed of a jittering shielding circuit, a counter 1 and a counter 2 (the operating frequencies of the counter 1 and the counter 2 are complementary), and used for carrying out measurement under the condition that the rising edge of the to-be-measured signal is slow. By using the system disclosed by the invention, the difficulty of improving the resolution ratio of a time parameter measurement system for high-precision digital integrated circuits in the prior art is overcome, and the technical difficulty that the measurement bandwidth of a time parameter measurement system is limited caused by the jitter of output signals of a comparator for channel circuits.

Description

A kind of time parameter measurement system

Technical field

The invention belongs to electronic measuring technology field, more specifically say, relate to a kind of digital integrated circuit time parameter measurement system.

Background technology

Integrated circuit is as basis and the core of information industry, it is the strategic industry of national economy and social development, the aspect plays an important role promoting economic development, social progress, uplift the people's living standard and safeguard national security etc., has become the focus of current international competition and has weighed the important symbol of a country up-to-dateness and overall national strength.

High-precision time parameter measurement system has been brought into play very important effect in design, checking and the encapsulation process of integrated circuit.It is whether qualified powerful measure of test and validation integrated circuit and time dependent parameter.

Fig. 1 is the schematic diagram of existing a kind of time parameter measurement system.

As shown in Figure 1, time parameter measurement system comprises main control unit, channel circuit unit and measuring unit three parts.Wherein, main control unit is responsible for the sending of various control signals and reading back of measurement result of channel circuit unit and measuring unit.Measured signal IN is connected to comparer A1 in the channel circuit unit and the anode of A2, and the negative terminal of comparer A1 and A2 meets level comparison signal VrefA and VrefB.The level of measured signal IN compares in comparer A1 and A2 with comparative level VrefA and VrefB respectively, output signal RStart and RStop, signal RStart and the RStop time interval signal in the channel circuit unit produces in circuit and is converted to time interval commencing signal Start and the stop signal Stop that measuring unit can be identified, then send into carry out XOR in measuring unit after, meet the Enable Pin EN of counter as the enable signal of counter, counter is counted, and output represents the output CNT[31:0 in the time interval].Wherein CLK is the counting pulse signal of counter, connects the CP end of counter, counter output CNT[31:0] be 32 bit binary data.

Fig. 2 is the measurement timing waveform of Fig. 1 time parameter measurement system.

At first the channel circuit unit is converted to signal RStart and RStop with measured signal IN, and time interval signal produces circuit signal RStart and RStop are converted to time interval commencing signal Start and stop signal Stop.Suppose counter output CNT[31:0] value be N, the count pulse of counter, namely the cycle of CLK is T, time interval T _x, namely measured signal IN time between VrefA and VrefB is:

T _x＝NT (1)

Time interval measurement this moment resolution is the count pulse cycle T of counter.

If requiring measuring resolution is 1ns, the frequency that requires clock CLK is 1GHz.Resolution requirement is higher, requires the rolling counters forward pulsed frequency higher, if resolution is brought up to 125ps, the frequency that requires CLK is 8GHz, and existing techniques in realizing is got up very difficult.Obviously it is difficult only depending on the way that improves the counter pulse frequency to improve resolving power.

Simultaneously, when measured signal IN rising edge was slow, can there be shake in the comparer A1 in the channel circuit unit and A2 output, cause its output pulse signal RStart and RStop jitter phenomenon to occur, finally cause measuring unit to measure difficulty, the time parameter measurement system Measurement bandwidth is limited.

Summary of the invention

The object of the invention is to overcome the deficiencies in the prior art, the time parameter measurement system of a kind of high resolving power and high measurement bandwidth is provided.

For achieving the above object, time parameter measurement system of the present invention comprises:

One main control unit;

One channel circuit unit, be used for measured signal is compared in the comparer of channel circuit unit, output two pulse signals RStart and RStop, simultaneously, under the control of main control unit, pulse signal RStart and the RStop time interval signal in the channel circuit unit produces in circuit and is converted to time interval commencing signal Start and stop signal Stop;

Characterized by further comprising:

One time accurate measurement unit is used for the measured signal rising edge more precipitous, and there is not the measurement in the situation of shake in comparer output, is comprised of multilevel delay line and scrambler;

Successively with many lag line formation multilevel delay connected in series lines, lag line comprises a plurality of delay cells and a plurality of d type flip flop by interconnection line; Time interval commencing signal Start from upper level connects first delay cell, if lag line is the first order, connect the time interval commencing signal Start of circuit unit output, then after each delay cell postpones successively to time interval commencing signal Start, all be connected to a d type flip flop, the D end of each d type flip flop meets the time interval commencing signal Start after delay units delay successively, the Clock pulse CP end of each d type flip flop all meets time interval stop signal Stop, and its reset terminal R meets the reset signal RESET that main control unit sends;

The Q end output of the d type flip flop on each lag line is sent in scrambler, and when time interval stop signal Stop arrived, the Q of each d type flip flop end output locking obtained representing time interval T _xScrambler output N, the time interval T of the delay cell number of interior time interval commencing signal Start process _xFor:

$T_x=N*t+\mathrm{ROUND}\left(\frac{N}{N_2}\right)*t_{\mathrm{\ΔL}},$

Wherein, ROUND represents rounding operation, N ₂The delay cell number of expression single-stage passive delay, t _{Δ L}Be the time delay of interconnection line;

One time bigness scale unit, be used for the measured signal rising edge slower, there are the measurement in the situation of shaking in comparer output pulse signal RStart and RStop, be comprised of dither mask circuit and time-interval-unit, the dither mask circuit comprises that debouncing circuit, waveform restoring circuit and time interval signal produce circuit;

Debouncing circuit comprises that two debounces move d type flip flop, two not gates, two programmable delay modules, a synchronous d type flip flop and a NAND gate;

The Clock pulse CP end of the pulse signal RStart of comparer output and the moving d type flip flop of RStop input debounce separately in the channel circuit unit, the output of two the moving d type flip flop output of debounce Q ends postpones Δ t by programmable delay module separately _L1, Δ t _L2After, behind the door non-through one respectively, be input to the R end that resets separately, the data D end of two moving d type flip flops of debounce all meets the Q end output of synchronous d type flip flop, Δ t time delay of programmable delay module _L1, Δ t _L2Should be respectively greater than the edge trembling time Δ t of pulse signal RStart and RStop separately _Start, Δ t _StopPulse signal RStart and RStop receive synchronous d type flip flop Clock pulse CP end through after NAND gate, the R termination synchronous reset signal TRI that resets of synchronous d type flip flop, data D termination high level; Signal Q after the moving d type flip flop output of pulse signal RStart and RStop debounce separately debounce is moving _StartWith signal Q _Stop

The waveform restoring circuit comprises two JK flip-flop, the J of two JK flip-flop, K end all connects high level, the R termination that resets is from the synchronous reset signal TRI of main control unit, and the Clock pulse CP end of two JK flip-flop is connected with the moving d type flip flop output of two debounces Q end respectively, the signal Q after the output debounce is moving _StartWith signal Q _StopRestoring signal JStart and signal JStop;

Time interval signal produces circuit and comprises two d type flip flops, the D termination high level Vcc of a d type flip flop, Clock pulse CP termination signal JStart, Q end output time interval commencing signal JJStart; The D termination signal JStart of another d type flip flop, clock pulse terminal CP meets signal JStop, Q end output time interval stop signal JJStop; The equal welding system reset signal of the reset terminal R RESET of two d type flip flops;

Time-interval-unit is used for measuring the time interval T that rising edge is tandem time interval commencing signal JJStart, stop signal JJStop _x

Goal of the invention of the present invention is achieved in that

measured signal compares in the comparer in the channel circuit unit, output two pulse signals RStart and RStop, simultaneously, under the control of main control unit, pulse signal RStart and the RStop time interval signal in the channel circuit unit produces in circuit and is converted to time interval commencing signal Start and stop signal Stop, because the time accurate measurement unit that adopts the multilevel delay line structure has very high Measurement Resolution, the generation that has overcome the high-frequency counting pulse signal of prior art is very difficult, the high resolution time parameter measurement system is difficult for the defective of realization.Simultaneously, adopted have the dither mask circuit time bigness scale unit, overcome the comparer output that prior art measured signal rising edge slowly causes and had shake, the defective that the time parameter measurement system Measurement bandwidth is limited.

Description of drawings

Fig. 1 is the schematic diagram of prior art time parameter measurement system.

Fig. 2 is the working timing figure of Fig. 1 time parameter measurement system.

Fig. 3 is a kind of embodiment schematic diagram in channel circuit unit in the present invention;

Fig. 4 is a kind of embodiment structural drawing of time accurate measurement unit in the present invention;

Fig. 5 is the working timing figure of time accurate measurement unit;

Fig. 6 is a kind of embodiment schematic diagram in time bigness scale unit in the present invention;

Fig. 7 is the circuit of dither mask shown in Fig. 6 embodiment schematic diagram;

Fig. 8 is the working timing figure of dither mask circuit shown in Figure 7;

Fig. 9 is the theory diagram of time parameter measurement system embodiment of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described, so that those skilled in the art understands the present invention better.What need to point out especially is that in the following description, when perhaps the detailed description of known function and design can desalinate main contents of the present invention, these were described in here and will be left in the basket.

Embodiment

One, channel circuit unit

Fig. 3 is a kind of embodiment schematic diagram in channel circuit unit in the present invention.

The channel circuit unit is the front end of time parameter measurement system, and in the present embodiment, the channel circuit unit comprises: input interface circuit, high-speed comparator, data selector and the time interval produce circuit.Its function is for correctly effectively being incorporated into time parameter measurement system with measured signal, and measured signal is converted to pulse signal RStart, RStop and time interval commencing signal Start and the stop signal Stop that time bigness scale unit, time accurate measurement unit can be identified.

As shown in Figure 3, in this enforcement, measured signal IN is connected to input interface circuit, in input interface circuit, the resistance R 1, R2 that is connected in series to ground IN to measured signal carried out dividing potential drop, and relay R ELAY1 selects measured signal IN directly or selects voltage division signal to send in high-speed comparator.Then this signal is connected to the anode of comparer A1 and A2+, at the negative terminal of comparer A1, A2-connect respectively comparative level VrefA and VrefB.

Data selector is selected forward output or the oppositely output of comparer A1, A2 by control signal SelStr and SelStop, signal RStart, the RStop after selection sends into time interval signal and produce circuit generation time interval commencing signal Start and stop signal Stop.

Time interval signal produces circuit and comprises two d type flip flop D1 and D2, the data D termination high level Vcc of D1, Clock pulse CP termination pulse signal RStart, Q end output time interval commencing signal Start; The Q end of the data D termination D1 of D2, Clock pulse CP termination pulse signal RStop, Q end output time interval stop signal Stop.The reset terminal R of D1 and D2 all fetches the reset signal RESET from the master control unit.

The channel circuit unit is work like this:

To measure the measured signal IN rise time as example, at first relay R ELAY1 selects the voltage measurement scope of measured signal IN.Then set comparative level VrefA and be measured signal IN dividing potential drop amplitude 10%, comparative level VrefB is 90% of measured signal IN amplitude.Simultaneously, main control unit begins control signal SelStr and stop control signal SelStop, makes data selector select the forward output of comparer A1, A2.At last, main control unit sends reset signal RESET.At this moment, rising edge time interval commencing signal Start the preceding appears at d type flip flop D1, after the time interval, commencing signal Start became high level, d type flip flop D2 occur rising edge after time interval stop signal Stop, and data selector output pulse signal RStart and RStop.When measured signal IN rising edge was slow, can there be shake in the comparer A1 in the channel circuit unit and A2 output, cause its output pulse signal RStart and RStop jitter phenomenon to occur.

Two, time accurate measurement unit

Fig. 4 is a kind of embodiment of time accurate measurement unit in the present invention.Fig. 5 is corresponding working timing figure.

In the present embodiment, as shown in Figure 4, time accurate measurement unit is comprised of multilevel delay line and alignment unit.The multilevel delay line is comprised of lag line and 6 interconnection lines of 7 same structures, and lag line is by delay cell L ₁-L ₆₈Form with d type flip flop DFFE1-DFFE68.Alignment unit is comprised of lag line and 1 interconnection line of 2 same structures.

In delay-line structure, delay cell L ₁-L ₆₈Connected in series successively, connect first delay cell from the time interval signal Start of upper level, if lag line is the first order, connect the time interval commencing signal Start of circuit unit output,, then transmit on the multilevel delay line successively.The data terminal of d type flip flop DFFE1D-FFE68 is received in the output of every grade of lag line successively.Time interval stop signal Stop connects the clock end of all d type flip flops.The reset terminal R of all d type flip flops meets reset signal RESET, so just can be removed to latch by d type flip flop the output state of delay unit, i.e. A_Q1 ... A_Q68, B_Q1 ... B_Q68 ..., G_Q1 ... G_Q68.Then output is sent into and just can be obtained between time interval commencing signal Start and stop signal Stop the delay cell number of transmission altogether in decimal encoder.The scrambler Output rusults is N, and be t the time delay of single delay cell, namely obtains time interval T _x:

T _x＝N*t (2)

Along with the birth of scale programmable logic device CPLD and FPGA, the metering circuit of showing for Fig. 4 provides good physical Design platform.Build lag line and need to satisfy following two conditions in FPGA: one, require t time delay of delay cell very little, and highly stable; Two, in FPGA inside, a kind of like this special construction must be arranged, be convenient to build lag line.In the present embodiment, the FPGA of the ACEX1K50 series of selected altera corp is in order to realize multilevel delay line and the alignment unit shown in Fig. 4.

Under common situations, the length of this FPGA internal latency line is limited, searches the device handbook and learns and be 72 grades to the maximum, and t time delay of stage delay unit is the 125ps left and right.Maximum measuring intervals of TIME is 125ps * 72=9ns as can be known.In the present invention, utilize interconnection line in FPGA with a plurality of such wall scroll lag line cascades, just can expansion time the range of dynamic measurement at interval.

In the present embodiment, as shown in Figure 4.The output of the wall scroll lag line of upper level is connected to the input of the wall scroll lag line of next stage by interconnection line, cascade up successively, has altogether formed 7 wall scroll lag lines and 6 multilevel delay line structures that interconnection line consists of.

Fig. 5 is the work schedule of multilevel delay line, D ₁-D ₄₇₆Be the output of each delay cell of lag line, remove to latch the transmission state of delay cell on lag line by time interval stop signal Stop signal, then with this transmission state by the decimal encoder output of encoding.The scrambler Output rusults is N, and be t the time delay of delay cell, and be t the time delay of interconnection line _{Δ L}, time interval T _xFor:

T _x＝N*t+N ₁*t _ΔL(3)

And N ₁For:

${\mathrm{<figure-callout\; id="1"\; label="N"\; filenames="HDA0000069763570000012.png,HDA0000069763570000031.png"\; state="\{\{state\}\}">N</figure-callout>}}_1=\mathrm{ROUND}\left(\frac{N}{N_2}\right),---\left(4\right)$

Wherein, ROUND represents rounding operation, N ₂The delay cell number of expression wall scroll lag line.Formula (4) is brought in formula (3), T _xFor:

$T_x=N*t+\mathrm{ROUND}\left(\frac{N}{N_2}\right)*t_{\mathrm{\&Delta;L}}---\left(5\right)$

In the present embodiment, time accurate measurement unit: N ₂=68, N ₁=6, t=125ps, measurement range: 0ns-50ns, Measurement Resolution 125ps.

Simultaneously, due to the difference of the size of FPGA power consumption, working temperature and use resource, the t and t time delay of interconnection line time delay of the delay cell in the multilevel delay line _{Δ L}Different sizes can appear.So, in the present embodiment, for the multilevel delay line provides an alignment unit, in order to real-time measurement t and t _{Δ L}Size, the measurement performance of alignment time accurate measurement unit.

Delay line calibration unit schematic diagram as shown in Figure 4.

In the present embodiment, alignment unit is comprised of 2 lag lines, 1 interconnection line and scrambler 2.

The alignment unit principle of work is: be approximately t the time delay of supposing the wall scroll lag line _LAt first, produce former and later two time interval signals SStart and SStop by a reference instrument, the time interval of establishing this moment is T _x1, and T _x1＜t _LTime interval commencing signal SStart is from lag line 1 input, and time interval stop signal SStop latchs the output state of delay cell in lag line 1 and lag line 2, then obtains Output rusults N through decimal encoder _Cal-1In like manner, again produce two time interval signal SStart and SStop by reference instrument, the time interval of this moment is T _x2, and t _L＜T _x2＜2*t _L, in like manner obtain Output rusults N _Cal-2

By formula (3) as can be known:

$\left\{\begin{array}{c}{T}_{x1}=N_{\mathrm{cal}-1}*t\\ T_{x2}=N_{\mathrm{cal}-2}*t+t_{\mathrm{\&Delta;L}}\end{array}\right.---\left(6\right)$

T and t _{Δ L}:

$\left\{\begin{array}{c}t=\frac{T_{x1}}{N_{\mathrm{cal}-1}}\\ t_{\mathrm{\&Delta;L}}=T_{x2}-N_{\mathrm{cal}-2}*\frac{T_{x1}}{N_{\mathrm{cal}-1}}\end{array}\right.---\left(7\right)$

Can measure t and t in system works environment by formula (7) this moment _{Δ L}Size, with t and t _{Δ L}In substitution formula (5), reached the purpose of alignment time accurate measurement unit.

Three, time bigness scale unit

In the present embodiment, as shown in Figure 3, pulse signal RStart and RStop are obtained through data selector by comparer A1, A2 output.When the measured signal rising edge more precipitous, when comparer A1, A2 output pulse signal RStart and RStop do not shake, can directly utilize pulse signal RStart and RStop to remove to trigger d type flip flop D1 and D2 generation time interval commencing signal Start and stop signal Stop.When the measured signal rising edge slower, when there are shake in comparer A1, A2 output pulse signal RStart and RStop, when if reset signal RESET resets to d type flip flop D1 and D2, during pulse signal RStart is in high level or negative edge shake, the negative edge shake will make the upset of d type flip flop D1 generation from the low level to the high level, negative edge can be judged as rising edge mistakenly like this, cause the time parameter measuring error.At this moment just can not directly utilize pulse signal RStart and RStop to remove to trigger d type flip flop generation time interval commencing signal Start Start and stop signal Stop.

Wherein, time bigness scale unit is also to realize in the FPGA of above-mentioned time accurate measurement unit.

Fig. 6 is a kind of embodiment schematic diagram in time bigness scale unit.

As shown in Figure 6, time bigness scale unit comprises and contains dither mask circuit and time-interval-unit, in the present embodiment, is to improve resolution, and the gate time interval measurement unit comprises two counters, i.e. counter 1 and 2 and one XOR gate.Wherein, counter 1 and 2 clock end CP connect respectively clock signal

And CLK, Enable Pin EN connects XOR gate output, and

With CLK 180 ° of phasic differences mutually, frequency is 125MHz, and measurement resolution is 4ns.In the situation that the counter clock frequency is constant, resolving power is doubled.

Time bigness scale unit is work like this:

As shown in Figure 7 and Figure 8, at first, low level of given synchronous reset signal TRI, synchronous d type flip flop 5 is output as low, at this moment, and two moving d type flip flops 3 of debounce, 4 output Qstart and Qstop, two JK flip-flop 1,2 output JStart and JStop are low; When given synchronous reset signal is high level, enable synchronous d type flip flop 5 and two JK flip-flop 1,2.When if in the channel circuit unit, the pulse RStart of data selector output and RStop are low level simultaneously, triggering synchronous d type flip flop 5, the output high level enables the moving d type flip flop 3,4 of two debounces.

Synchronous d type flip flop 5 and synchronous reset signal TRI, make the moving d type flip flop D of two debounces be simultaneously Low level effective at pulse signal RStart and RStop, start working, making output JStart and the JStop of two JK flip-flop is low simultaneously, its state is consistent, has guaranteed that so whole dither mask circuit sequence is synchronous, consistent.

Pulse signal RStart and RStop are through being reduced into signal JStart and the JStop that there is no shake after the dither mask circuit.Then produce in circuit at time interval signal, by reset signal RESET, generation time interval commencing signal JJStart and stop signal JJStop.Signal JJStart and JJStop export the CNTEN signal after XOR in XOR gate, counting in counter 1,2, thus measure time interval T _xThe measurement result of supposing counter 1 sum counter 2 is respectively CNT1 and CNT2, and time interval Tx is:

$T_x=\frac{\mathrm{<figure-callout\; id="1"\; label="CNT"\; filenames="HDA0000069763570000012.png,HDA0000069763570000031.png"\; state="\{\{state\}\}">CNT</figure-callout>}1+\mathrm{CNT}2}{2}*T---\left(8\right)$

Wherein, T is the count pulse clk cycle of counter.

Fig. 7 is a kind of embodiment schematic diagram of dither mask circuit.

As shown in Figure 7, the dither mask circuit comprises debouncing circuit, waveform restoring circuit and time interval signal generation circuit.

As shown in Figure 7, debouncing circuit comprises that a synchronous d type flip flop is that d type flip flop 5, two moving d type flip flops of debounce are d type flip flop 3,4, two not gates and two programmable delay modules.Pulse signal RStart and RStop are through receiving the CP end of synchronous d type flip flop, the R termination that resets synchronous reset signal TRI, data D termination high level after NAND gate; Pulse signal RStart and RStop input the moving d type flip flop 3 of debounce separately, 4 clock CP end simultaneously, and the programmable delay module that output Q end passes through separately postpones Δ t _L1, Δ t _L2After time, behind the door non-through one respectively, be input to the moving d type flip flop 3 of debounce, 4 the R end that resets, two moving d type flip flops 3 of debounce, 4 data D end all connect the Q end output of synchronous d type flip flop, and debounce is moved d type flip flop 3, Q is used respectively in 4 output _Start, Q _StopExpression, Δ t time delay of programmable delay module _L1, Δ t _L2Should be respectively greater than the edge trembling time Δ t of pulse signal RStart and RStop separately _Start, Δ t _Stop

As shown in Figure 7, the waveform restoring circuit comprises two JK flip-flop, and namely J, the K of JK flip-flop 1,2, two JK flip-flop end all meets high level Vcc, the R termination that resets synchronous reset signal TRI, the Clock pulse CP end of two JK flip-flop are connected with the moving d type flip flop 3 of two debounces, 4 output Q ends respectively.JStart is used respectively in the output of two JK flip-flop, and JStop represents.

As shown in Figure 7, it is identical with time interval signal generation circuit in Fig. 3 channel circuit unit that time interval signal produces circuit, comprise two d type flip flops 6,7, the data D termination high level Vcc of d type flip flop 6, Clock pulse CP termination signal JStart, Q end output time interval commencing signal JJStart; The Q end of the D termination d type flip flop 6 of d type flip flop 7, clock pulse terminal CP meets signal JStop, Q end output time interval stop signal JJStop.D type flip flop 1,2 reset terminal R all meet reset signal RESET.

Fig. 8 is the working timing figure of Fig. 7 institute dither mask circuit.

The dither mask circuit is work like this:

The principle of eliminating pulse signal RStart and RStop shake is similar, and take pulse signal RStart as example, as shown in Figure 8, the shake time of pulse signal RStart is Δ t _Start, when pulse signal RStart arrived, the data D end of the moving d type flip flop 3 of debounce was for carrying out the high level of synchronous d type flip flop 5 outputs after timing synchronization.When the Clock pulse CP termination of the moving d type flip flop 3 of debounce is received the rising edge of pulse RStart, the output terminal Q output signal Q of the moving d type flip flop 3 of debounce _StartBe high level, signal Q _StartPostpone a period of time Δ t through programmable Postponement module 1 _L1Rear output postpones Δ t _L1Be the size that main control unit is in advance set, and time delay Δ t _L1Edge trembling time Δ t greater than pulse RStart _StartPulse Q _StartBy the moving d type flip flop 3 of the debounce that resets after the not gate negate, the moving d type flip flop 3 output pulse Q of debounce this moment _StartEqual low level, until the rising edge of pulse RStart signal when this arrives again, triggers the moving d type flip flop 3 of debounce, the moving d type flip flop 3 output pulse Q of debounce again _StartBecome again high level, and afterpulse Q _StartPostpone a period of time Δ t through programmable Postponement module 1 again _L1Rear output.Then by the moving d type flip flop 3 of the debounce that resets after the not gate negate, the moving d type flip flop 3 of debounce this moment is exported pulse Q again _StartEqual low level, so just pulse RStart is converted to pulse Q _StartAnd pulse Q _StartThe high level width equal Δ t _L1

Due to pulse Q _StartReceive the clock end CP of JK flip-flop 1, and the data terminal J of JK flip-flop 1 and K all connect fixedly high level.Principle of work by JK flip-flop can know, when coming a rising edge, the output of JK flip-flop just is turned to state 1 from state 0, or is turned to state 0 from state 1.JK flip-flop is just with signal Q like this _StartConversion is for signal JStart.And the JStart signal is that the RStart signal removes the signal that reduces after shake as can be known.

Fig. 9 is the theory diagram of time parameter measurement system embodiment.

As shown in Figure 9, in the present embodiment, time parameter measurement system of the present invention comprises main control unit, channel circuit unit, time accurate measurement unit and time bigness scale unit.

Main control unit sends control command, and the channel circuit unit is converted to time interval commencing signal Start and stop signal Stop with measured signal, and pulse signal RStart and the RStop of pulse after data selector that produce of comparer.

When measurement range 0ns-50ns, accurate measurement service time unit is measured, the time interval between measuring intervals of TIME commencing signal Start and stop signal Stop.At last measurement result is transferred to main control unit from the SPI interface.

When measurement range 50ns-1ms, bigness scale service time unit is measured.Comparer output through the pulse RStart after data selector and RStop process dither mask circuit, is removed signal jitter, then send into counter and measure.At last measurement result is transferred to main control unit from the SPI interface.

Control signal from main control unit produces various control signals in control logic circuit, comprise control signal of synchronous reset signal TRI, reset signal RESET and channel circuit unit, time accurate measurement unit and time bigness scale unit etc.

In the present embodiment, digital integrated circuit time parameter measurement system of the present invention provides respectively time accurate measurement unit and time bigness scale unit to be used for measuring.Not only solve the difficulty that the time parameter Measurement Resolution improves, and solved the comparator output signal shake, the defective that the time parameter measurement system Measurement bandwidth is limited.Test result proves that this system testing resolution, repeatability and stability all satisfy the indices requirement of digital integrated circuit time parameter test macro, and the measurement index of realization is:

1, time accurate measurement unit: range of dynamic measurement 0ns-50ns, resolution is 125ps, measuring accuracy 500ps ± 1%.

2, time bigness scale unit: range of dynamic measurement 50ns-1ms, resolution is 4ns, measuring accuracy 4ns ± 0.1%.

Simultaneously, time parameter measurement system of the present invention also has important using value and development meaning in every field such as theory research, test scientific and engineering, medical skill and science, Communications And Navigation, Modulation domain analyzers.

Although the above is described the illustrative embodiment of the present invention; so that those skilled in the art understand the present invention; but should be clear; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various variations appended claim limit and the spirit and scope of the present invention determined in, these variations are apparent, all utilize innovation and creation that the present invention conceives all at the row of protection.

Claims (3)

1. time parameter measurement system comprises:

One main control unit;

One channel circuit unit, be used for measured signal is compared in the comparer of channel circuit unit, output two pulse signals RStart and RStop, simultaneously, under the control of main control unit, pulse signal RStart and the RStop time interval signal in the channel circuit unit produces in circuit and is converted to time interval commencing signal Start and stop signal Stop;

Characterized by further comprising:

One time accurate measurement unit is used for the measured signal rising edge more precipitous, and there is not the measurement in the situation of shake in comparer output, is comprised of multilevel delay line and scrambler;

Successively with many lag line formation multilevel delay connected in series lines, lag line comprises a plurality of delay cells and a plurality of d type flip flop by interconnection line; Time interval commencing signal Start from upper level connects first delay cell, if lag line is the first order, connect the time interval commencing signal Start of circuit unit output, then after each delay cell postpones successively to time interval commencing signal Start, all be connected to a d type flip flop, the D end of each d type flip flop meets the time interval commencing signal Start after delay units delay successively, the Clock pulse CP end of each d type flip flop all meets time interval stop signal Stop, and its reset terminal R meets the reset signal RESET that main control unit sends;

The Q end output of the d type flip flop on each lag line is sent in scrambler, and when time interval stop signal Stop arrived, the Q of each d type flip flop end output locking obtained representing time interval T _xScrambler output N, the time interval T of the delay cell number of interior time interval commencing signal Start process _xFor:

$T_x=N*t+\mathrm{ROUND}\left(\frac{N}{N_2}\right)*t_{\mathrm{\&Delta;L}},$

Wherein, ROUND represents rounding operation, N ₂The delay cell number of expression single-stage passive delay, t _{Δ L}Be the time delay of interconnection line, t is the time delay of delay cell;

One time bigness scale unit, be used for the measured signal rising edge slower, there are the measurement in the situation of shaking in comparer output pulse signal RStart and RStop, be comprised of dither mask circuit and time-interval-unit, the dither mask circuit comprises that debouncing circuit, waveform restoring circuit and time interval signal produce circuit;

Debouncing circuit comprises that two debounces move d type flip flop, two not gates, two programmable delay modules, a synchronous d type flip flop and a NAND gate;

The Clock pulse CP end of the pulse signal RStart of comparer output and the moving d type flip flop of RStop input debounce separately in the channel circuit unit, the output of two the moving d type flip flop output of debounce Q ends postpones △ t by programmable delay module separately _L1, △ t _L2After, behind the door non-through one respectively, be input to the R end that resets separately, the data D end of two moving d type flip flops of debounce all meets the Q end output of synchronous d type flip flop, △ t time delay of programmable delay module _L1, △ t _L2Should be respectively greater than the edge trembling time △ t of pulse signal RStart and RStop separately _Start, △ t _StopPulse signal RStart and RStop receive synchronous d type flip flop Clock pulse CP end through after NAND gate, and the R termination that resets of synchronous d type flip flop is from the synchronous reset signal TRI of main control unit, data D termination high level; Signal Q after the moving d type flip flop output of pulse signal RStart and RStop debounce separately debounce is moving _StartWith signal Q _Stop

The waveform restoring circuit comprises two JK flip-flop, the J of two JK flip-flop, K end all connects high level, the R termination that resets synchronous reset signal TRI, the Clock pulse CP end of two JK flip-flop are connected with the moving d type flip flop output of two debounces Q end respectively, the signal Q after the output debounce is moving _StartWith signal Q _StopRestoring signal JStart and signal JStop;

Time interval signal produces circuit and comprises two d type flip flops, the D termination high level Vcc of a d type flip flop, Clock pulse CP termination signal JStart, Q end output time interval commencing signal JJStart; The D termination signal JStart of another d type flip flop, clock pulse terminal CP meets signal JStop, Q end output time interval stop signal JJStop; The equal welding system reset signal of the reset terminal R RESET of two d type flip flops;

Time-interval-unit is used for measuring the time interval T that rising edge is tandem time interval commencing signal JJStart, stop signal JJStop _x

2. time parameter measurement system according to claim 1 characterized by further comprising:

One delay line calibration unit, the delay line calibration unit is comprised of two lag lines, an interconnection line and a scrambler;

Produce former and later two time interval signals SStart and SStop by a reference instrument, the time interval of this moment is T _x1, and T _x1＜t _L, tL is the time delay of wall scroll lag line, and time interval commencing signal SStart is from lag line 1 input, and time interval stop signal SStop latchs the output state of delay cell in lag line 1 and lag line 2, then obtains Output rusults N through decimal encoder _Cal-1In like manner, again produce two time interval signal SStart and SStop by reference instrument, the time interval of this moment is T _x2, and t _L＜T _x2＜2*t _L, in like manner obtain Output rusults N _Cal-2,, the t and t time delay of interconnection line time delay of delay cell _{Δ L}:

$\left\{\begin{array}{c}t=\frac{T_{x1}}{N_{\mathrm{cal}-1}}\\ t_{\mathrm{\&Delta;L}}=T_{x2}-N_{\mathrm{cal}-2}*\frac{T_{x1}}{N_{\mathrm{cal}-1}}\end{array}\right.$

T and t time delay of interconnection line time delay with delay cell _{Δ L}The substitution formula:

$T_x=N*t+\mathrm{ROUND}\left(\frac{N}{N_2}\right)*t_{\mathrm{\&Delta;L}},$

Proofreaied and correct time interval T thereby reach _x, i.e. the purpose of smart time measuring unit.

3. time parameter measurement system according to claim 1, is characterized in that, described time-interval-unit comprises two counters and an XOR gate, and the clock end CP of two counters connects respectively clock signal

And CLK, Enable Pin EN connects XOR gate output, and

With CLK 180 ° of phasic differences mutually;

The Output rusults of two counters is respectively CNT1 and CNT2, time interval T _xFor:

$T_x=\frac{\mathrm{CNT}1+\mathrm{CNT}2}{2}*T$

Wherein, T is the count pulse clk cycle of counter.

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