CN103676622B - A kind of high-precision positive and negative time interval measurement method and device - Google Patents
A kind of high-precision positive and negative time interval measurement method and device Download PDFInfo
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- CN103676622B CN103676622B CN201310512907.1A CN201310512907A CN103676622B CN 103676622 B CN103676622 B CN 103676622B CN 201310512907 A CN201310512907 A CN 201310512907A CN 103676622 B CN103676622 B CN 103676622B
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Abstract
The present invention provides a kind of high-precision positive and negative time interval measurement method and device, and wherein device includes signal shaping and measures gate extraction unit, synchronization and interpolation unit, clock count unit, memory element, data processing unit and be connected with each other and mutually communication；Described signal shaping and measurement gate extraction unit, according to the triggering level arranged, compare shaping to input signal, measured signal be converted into ECL level signal, extract, by ECL trigger, the signal strobe that measured signal is corresponding；Described synchronization and interpolation unit, two-way signal strobe is sampled by the counting clock of utilization.Use such scheme, be possible not only to realize the input of polytype signal, and wider input dynamic range can be supported；Channel circuit uses High Speed ECL device to realize, and bandwidth chahnel is big, it is possible to achieve burst pulse is measured, and I survey pulse width can reach 40ps up to 2.5ns, Measurement Resolution.
Description
Technical field
The invention belongs to positive and negative time interval measurement technical field, in particular a kind of high
The positive and negative time interval measurement method of precision and device.
Background technology
High-precision time interval measurement technology be widely used in satellite navigation, radar fix,
The fields such as laser ranging, nuclear physics detecting and time and frequency measurement.NAS is made
For one of important symbol of assessment country defense force, the most all can hold chronometer time and time
Between interval measurement technical conferences, and the science and technology must greatly developed as country it
One.Current wide variety of time interval measurement method have pulse counting method, analog interpolation,
Delay line interpolation, vernier method and time m-amplitude transformation approach.The measurement essence of pulse counting method
Degree is determined by step-by-step counting clock, and measurement error is ± 1 clock cycle, in order to improve survey
Accuracy of measurement needs correspondingly to improve counting clock frequency.For current mature technology level,
Counting clock frequency only up to work 2～3GHz, and such time resolution can only reach
To about 500ps, far from meeting at present in most cases to time interval measurement precision
Requirement.Analog interpolation is to improve certainty of measurement, pulse based on burst pulse expansion technique
Can cause the increase of measurement time after broadening, the single measurement time needs hundreds of nanosecond at least
Above, therefore the method is not suitable for the occasion higher to measuring speed requirement.The most high-precision
Degree time interval measurement field applies most common method to be latter three kinds, its time interval measurement
Precision can reach tens psecs.
Delay line can be divided into tapped delay line and differential delay line two kinds, and differential delay line is relatively
Tapped delay line can realize higher certainty of measurement, but it is the most more to consume resource.Have a large amount of
This kind of method is successfully realized in FPGA by research, utilizes the lookup within FPGA
Table, carry chain and cascade chain are as delay cell, it is possible to achieve the measurement essence of about 100ps
Degree.Delay unit within FPGA is affected relatively big by temperature and supply voltage, it
Environmental suitability is very poor, needs to compensate in a large number and calibrate to ensure it in practical process
Certainty of measurement, thus its commercial value is the most notable at present.Vernier method and time m-amplitude
Transformation approach has been successfully applied to the precedent of commercial test instrument, such as Agilent company and has developed
Universal frequency meter 53230A utilize vernier method to achieve the measure of time resolution of 20ps,
When the time interval tester SR620 that Stanford University develops utilizes, m-amplitude transformation approach is also
Reach the measure of time resolution of 20ps.In order to realize high measure of time resolution, this
Processing technique is required higher by two kinds of methods, and cost of manufacture the most costly, is to the time
The occasion that interval measurement index request is higher uses more.The present invention utilizes general integrated device
Devising a high-precision time interval measurement device, the time not only achieving 40ps surveys
Amount resolution, and cost of manufacture is relatively low, it is the highest to realize threshold, has higher reality
Promotional value.
Time interval is used to the neck describing an event relative to another Time To Event
First degree, measures by time value.When reference event occurs when first, gained time interval
Measured value is just；Otherwise, time interval measurement value is negative.Reference event is sent out with observation event
Raw sequencing is unknown sometimes, carries out this situation just needing during time interval measurement
Use positive and negative time interval measurement.There is the instrument of positive and negative time interval measurement function at present
Having a lot, on implementation, most representativeness is the frequency time compartment analysis of Hewlett-Packard
Instrument HP5370, its positive and negative time interval measurement realize theory diagram as shown in Figure 1.Assume
Event 1 is reference event, and relation between event 1 and event 2 is as in figure 2 it is shown, its work
Principle is as follows: owing to reference event occurs front, the detection polarity of extraction unit 101 output
For just, represent with high level；Produced by the rising edge synch of event 1 and event 2 and measure
Gate, measures the high impulse of gate in requisition for the time interval value measured；Signal strobe by
Clock count unit 102 carries out bigness scale, after interpolation unit 103 carries out accurate measurement, it is possible to
To the precise time value measuring gate high impulse；Combine with detection polarity number and can be obtained by
Need the positive and negative time interval measured.Utilize such scheme HP5370 achieve 200ps time
Between interval measurement resolution, time interval measurement scope has reached-4s～+4s.Its extraction
Unit 101 uses the integrated chip of customization with intellectual property to realize, interpolation unit 103
Using delay line to realize, the two unit is also the core place of whole scheme, has relatively
High technology realizes difficulty.
Shortcoming of the prior art is:
When 1, using single channel to complete positive and negative time interval measurement, when two event generation time phases
When close, such as when time interval is less than 50ps, for the response speed with current device
It is difficult to judge that event is leading, that event lags, pole during positive and negative time interval measurement
Can there is one section of dead band in property detection, so can reduce the accuracy of positive and negative time interval measurement.
2, with the above-mentioned condition of shortcoming 1, measure gate and extract circuit and burst pulse measuring circuit
All cannot realize the highest time interval measurement precision.Due to by device pulse recognition ability
Restriction, measuring gate can not be infinitely small；Additionally to mean that it has higher for burst pulse
Frequency component, this also will bring no small challenge to layout and the cabling of printed board, these
Factor can limit the further raising of positive and negative time interval measurement resolution and certainty of measurement.
3, have employed bigness scale in measure of time and implementation that accurate measurement combines, bigness scale unit
Must do synchronization process with accurate measurement unit, not so some measurement result can introduce ± 1 when measuring
The error in clock cycle.When event rising edge and rising edge clock adjacent to time, owing to pulse calculates
The response speed of unit and interpolation unit is inconsistent, and interpolation unit 103 may have identified that
Nearest clock edge, pulse computing unit is unsatisfactory for setting up the retention time and misses corresponding
Clock edge, so may result in measure of time result and-1 clocking error occurs；In like manner decline
Along there will be+1 clocking error.
4, employing look-up table, carry chain and cascade chain within FPGA is as delay line, it
Affected the most notable by supply voltage and temperature.Time delay can be along with the rising of temperature
Increase, it is assumed that when 25 degrees Celsius, time delay is 1, time delay during temperature 85 degrees Celsius
Will become 1.1, during temperature-40 degrees Celsius, time delay will become 0.9；Time delay
Along with the fluctuation of supply voltage also can change, it is assumed that when postponing when supply voltage is 3.3V
Between be 1, when supply voltage is 3.5V, time delay will become 0.95, and supply voltage is
During 3.1V, time delay is 1.05.Visible supply voltage and the temperature certainty of measurement to the method
There is significantly impact, which also limits the method application in Practical Project.
Therefore, prior art existing defects, need to improve.
Summary of the invention
The technical problem to be solved is for the deficiencies in the prior art, it is provided that a kind of
High-precision positive and negative time interval measurement method and device.
Technical scheme is as follows:
Employing such scheme:
1, the dual pathways is used to complete positive and negative time interval measurement, it is possible to achieve the highest measurement
Precision, simultaneously there is not dead-time problem.
2, high-speed comparator is used to complete input signal shaping, it is possible to achieve polytype
Signal input and wide input dynamic range.Channel circuit uses High Speed ECL device to realize,
Bandwidth chahnel is big, it is possible to achieve burst pulse is measured.
3, the extraction circuit design used is simple, is possible not only to realize the measurement gate without dead band
Extract, and broadening can be carried out to measuring gate, it is to avoid be inconvenient to the burst pulse processed.
4, use microstrip line as delay cell, it is possible to achieve the highest time interval measurement divides
Resolution, and time interval measurement resolution is affected by environment little, calibration process is the simplest.
5, using enumerator collocation form flexibly, resource consumption is few, it is possible to achieve the widest
Positive and negative time interval measurement scope.
6, using general integrated device to realize, technical threshold is less demanding, it is achieved low cost.
Accompanying drawing explanation
Fig. 1 be in prior art positive and negative time interval measurement realize schematic diagram.
Fig. 2 is event 1 and event 2 work schedule schematic diagram in Fig. 1.
Fig. 3 is the high-precision positive and negative time interval measurement device of the present invention.
Fig. 4 is event 1 and event 2 work schedule schematic diagram in Fig. 3.
Fig. 5 is shaping and extraction unit realizes theory diagram
Fig. 6 is that front interpolation unit realizes theory diagram
Fig. 7 is front interpolation unit work schedule schematic diagram
Fig. 8 is that clock count unit realizes theory diagram
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Embodiment 1
As shown in figures 3-8, the present invention positive and negative time interval measurement device includes following portion
Point:
Signal shaping and measurement gate extraction unit, according to the triggering level arranged, to input
Signal compares shaping, and measured signal unification is converted into the ECL letter being easy to subsequent treatment
Number, utilize trigger to extract the two-way signal strobe needing to measure.
Synchronize and interpolation unit, utilize counting clock to sample to measuring signal strobe,
To the signal strobe Tong Bu with counting clock, a road send clock count unit to enter measuring gate
Row bigness scale, another road is sent interpolation unit to carry out front interpolation measurement, is completed measuring gate forward position
The accurate measurement of inadequate clock cycle part.
Clock count unit, utilizes the signal strobe control counter synchronized, completes measurement
The number of cycles of gate is measured.
Storage and processing unit, complete clock count unit and interpolation unit measurement data
Storage, first goes out burr and processes, then according to coding rule by interior interpolation measurement data
Slotting data are converted into interpolation time value, finally calculate positive and negative time interval measurement value.
The basic functional principle of the present invention is as follows: as shown in work schedule Fig. 4, when needs are surveyed
When amount event 2 is relative to the positive and negative time interval of event 1, whether reference event 1, also
After being effective rising edge arrival of observation event 2, corresponding trigger all will be made to export
For high level, completing the labelling to event due in, specific works principle is with reference to Fig. 5.
After the effective edge edge of two events is all labeled, after FPGA detection and postponing a period of time,
Two triggers are resetted simultaneously.As shown in Figure 4, the difference in pulse width of two pulse signals
It is the positive and negative time interval needing to measure, therefore needs to measure the most respectively the arteries and veins of two pulse signals
Rush width.Have employed bigness scale in realization and add the mode that accurate measurement combines, utilize clock count list
Unit provides the bigness scale value of pulse width, and delay line interpolation unit provides the accurate measurement value of pulse width,
The positive and negative time interval value that may finally obtain measuring is:
± TI2 → 1=TG1-TG2
=IT1+IT11-IT12-(IT2+IT21-IT22)
=IT1+IT11-IT2-IT21
=Tclk × (N1-N2)+TD × (M1-M2)
Use the dual pathways to complete positive and negative time interval measurement, embody two by subtraction
Relativeness between event, when reference event changes, it is not necessary to changes hardware circuit and sets
Put, only need to change they positions in computing.Use twin-channel structure can gram
Take dead-time problem present in conventional positive and negative time interval measurement.Extraction circuit realiration is simple,
Improved the width measuring signal strobe by additional delay, setting of subsequent conditioning circuit can be reduced
Meter pressure.Use synchronization process technology, it is to avoid measured value appearance ± 1 clocking error.Adopt
With microstrip line as delay line, time delay is affected by environment little；Delay line uses difference knot
Structure is to improve time interval measurement resolution, and time interval measurement resolution will be no longer by device
The restriction of physical size.Implementation is simple, and key components used is generic set and grows up to be a useful person
Part, the technology of the present invention threshold requirement is the highest, it is achieved low cost, have promotional value widely.
The present invention can obtain following performance indications: positive and negative time interval measurement scope is permissible
Reaching-4s～+4s, positive and negative time interval measurement resolution can reach 40ps, and single is positive and negative
Time interval measurement precision is better than 100ps.
In order to extend the dynamic range of input signal, support that polytype signal inputs, this
Invention devises a high-speed comparator at input, completes the shaping to input signal and electricity
Flat turn is changed.The high-speed comparator selected is ADCMP582, and it can identify minimum pulse width
For 100ps, output level form is PECL, after high-speed comparator shaping, and input letter
Number unification is converted into the PECL signal with high speed rising and falling edges.The magnetic hysteresis district of comparator
Between adjustable, minimum judgement magnetic hysteresis interval can reach about 10mV, and these can be for realizing height
Precision Time interval measurement provides solid foundation.
PECL signal after shaping send the extraction unit being made up of trigger and FPGA, extracts
Measure signal strobe.The data termination ECL high level of trigger, the anti-phase output of trigger
Signal through ECL to TTL change after send FPGA, FPGA to detect two paths of signals is all low time,
After utilizing the internal 100MHz clock signal delay 40ns of FPGA, extract two simultaneously and trigger
Device resets.In design, model used by all of trigger is MC100EP51, maximum functional frequency
Rate is 100 picoseconds more than 3GHz, the foundation of needs and retention time, ECL to TTL
Transducer selects model to be MC100EP21.
Measurement gate send the data terminal of synchronizer trigger, and clock terminates the clock signal of 1GHz,
After 1GHz clock signal samples, the signal strobe with clock signal synchronization can be obtained,
It is called for short sync gate.Synchronous gate signal one tunnel send clock count unit, a road to send interpolation list
Unit.At clock count unit, synchronous gate signal is used as binary counter MC100EP016
Enable, the counting clock frequency of enumerator is 1GHz.Count during sync gate is height
Device works, and is to complete the storage of the data to enumerator between lowstand and reset at sync gate.
MC100EP016 is 8 binary counters, and time actually used, it is far from meeting counting
The design requirement of bit wide.In the present invention in FPGA indoor design one 24 digit counter,
Cascade forms 32 digit counters therewith, and maximum measuring time can reach 4 seconds, and this can
To meet demand to time interval measurement scope in most cases.Certainly, for improving
Time interval measurement scope, can be real flexibly by the bit wide configuring FPGA count internal
Existing.
In order to improve the measurement degree of stability of interpolation unit, the present invention selects microstrip line as delay
Unit, it has higher environmental stability.The microwave board that dielectric constant is little is selected in printed board
Material, to improve the transmission speed of microstrip line power on signal.1ps transmission delay pair in the present invention
The a length of 0.2217mm of microstrip line answered, a length of 20mm of delay line 1 correspondence, delay line 2
Corresponding a length of 28.868mm.Interpolation unit maximum measuring time is 1ns, and these needs prolong
The progression of chain is 25 late, and the total length that can extrapolate delay line 1 is 500mm, delay line
The total length of 2 is 721.7mm.According to the temperature of 1cm microstrip line under certain Document system room temperature condition
Coefficient is 0.014ps/ DEG C, when both temperature often raises 1 DEG C, and the total delay time of delay line 1
Increasing 0.7ps, the total delay time of delay line 2 increases 1ps, during differential delay line total delay
Between increase 0.3ps/ DEG C, it can be seen that the interpolation unit of the present invention has higher stability.
FPGA utilizes the rising edge of latch signal to latch interpolated value, utilizes trailing edge to latch counting
Value.Latch signal and 100MHz clock is utilized to generate a reseting pulse signal in FPGA,
Latch signal trailing edge postpones 10ns and produces reseting pulse signal, the pulse width of reset signal
For 10ns.
In FPGA interpolative data to go out burr rule as follows: the output valve of N position is equal to N-
1 with the logical "and" of N position input value；Primary output valve is identical with input value.
After above-mentioned process, it is 1000ps, interpolation unit every grade by the known clock cycle
Time delay is after 40ps substitutes into formula (1), it is possible to count out need to measure positive and negative time
Between spacing value (unit is ps):
± TI=1000 × (N1-N2)+40 × (M1-M2).
Embodiment two
On the basis of above-described embodiment, the method that the present embodiment provides is:
Step 1: peak value and valley according to input signal arrange comparative level, by height
Speed comparator converts input signals into ECL signal so that it is have less rising and falling edges
Time, to reduce trigger error.
Step 2: send D flip-flop by the ECL signal after high-speed comparator shaping
Clock port, the data termination high level of D flip-flop, after carrying out a rising edge, touches
Send out device and be output as height the most immediately.
Step 3: send FPGA, FPGA to detect the reversed-phase output signal of two-way D flip-flop
To two paths of signals be all low after, through time-delay, two triggers are entered simultaneously
Horizontal reset operates, and forces to draw as low by the output signal of two triggers, and such two triggers are defeated
Go out to be formed a pulse signal.Trigger positive output signal is for measuring gate, two drive tests
The rising edge of amount gate carries event 1 and the temporal information of event 2, and two drive tests respectively
The trailing edge of amount gate is completely superposed, thus the measurement time of two-way gate is done subtraction
Can be obtained by the most positive and negative time interval between two events, wherein with reference to the measurement of gate
Time is as minuend.
Step 4: measurement signal strobe is sent the data terminal of synchronizer trigger, when utilizing counting
Clock is sampled to measuring gate, obtains the signal strobe Tong Bu with counting clock, referred to as
Sync gate.Synchronous gate signal is divided into two-way, and clock calculation unit is sent on a road；Another road
Interpolation unit is together sent with measuring signal strobe.
Step 5: be sent to the synchronous gate signal of clock calculation unit, as binary computations
The use of device controls.During sync gate is height, clock signal is counted, obtain
Measure gate thick time measured value；It is between lowstand at sync gate, utilizes interpolation unit
Count value is latched by the latch signal provided, and declines at FPGA inner utilization latch signal
Along producing a reset signal after time delay, the state of binary counter is resetted.
Step 6: interpolation unit have employed the mode of differential delay line and realizes, measures gate
Signal is differential signal Zhong mono-tunnel, send the data terminal of corresponding trigger after classified delay,
Every grade of time delay is fixed as TD1；Synchronous gate signal is another road of differential signal, warp
Send the clock end of corresponding trigger after step delay, be fixed as TD2 every grade of time delay,
Time delay, TD1 40ps bigger than TD2, implemented principle as shown in Figure 6.
Step 7: the rising edge measuring gate in interpolation unit leads over sync gate, neck
The first time is zero to one clock cycle.After every grade of delay chain, measure the upper of gate
Rise and postpone 40ps along relative to sync gate.Assume between M level and M+1 level, measure lock
The rising edge of door overlaps with sync gate rising edge, then before the rising edge of sync gate arrives
After the clock end of M level trigger, the output of front M level trigger is all high level, from M+1
It is all low level that level starts to the output of afterbody trigger, and specific works sequential is shown in Fig. 7 institute
Show.
Step 8: trigger output signal is sent to FPGA, FPGA after level conversion and utilizes
Above-mentioned interpolative data is latched by latch signal as clock.
Step 9: after synchronous gate signal passes whole delay chain, through ECL to TTL electricity
Flat turn is sent to FPGA as latch signal, control count value and the latch of interpolated value after changing.Profit
Latch count value with the trailing edge of latch signal, utilize the rising edge of latch signal to latch interpolation
Value, implements principle as shown in Figure 8.
Step 10: produce multiple at FPGA inner utilization latch signal rising edge after time delay
Position signal, resets to the state of trigger each in interpolation unit.FPGA is used to produce multiple
Position signal, the so convenient sequential to reset signal is controlled.
The interpolative data that step 11:FPGA latches, after deburring and code conversion, is changed
Becoming binary system interpolated value, minima is 0, maximum is N(delay chain progression).Coding turns
Change rule as follows: start to calculate the number of output high level from interpolation unit first order delay chain,
If there being continuous N high level, conversion value is then M.
Step 12: utilize substitute into public affairs the time delay of known clock cycle and every grade of delay chain
Formula (1), it is possible to count out the positive and negative time interval value needing to measure.
The present invention has a following feature: use the dual pathways to complete positive and negative time interval measurement,
Relativeness between two events is embodied by subtraction, when reference event changes,
Arrange without changing hardware circuit, only need to change they positions in computing.Use
Twin-channel structure can overcome dead-time problem present in conventional positive and negative time interval measurement.
Extraction circuit realiration is simple, is improved the width measuring signal strobe by additional delay, can
To reduce the design pressure of subsequent conditioning circuit.Use synchronization process technology, it is to avoid measured value goes out
Existing ± 1 clocking error.Using microstrip line as delay line, time delay is affected by environment little；
Delay line uses differential configuration to improve time interval measurement resolution, and time interval measurement divides
Resolution will no longer be limited by device physical dimension.Implementation is simple, crucial unit used device
Part is general integrated device, it is achieved low cost.
It should be appreciated that for those of ordinary skills, can add according to the above description
To improve or conversion, and all these modifications and variations all should belong to right appended by the present invention and want
The protection domain asked.
Claims (9)
1. a high-precision positive and negative time interval measurement method, it is characterised in that comprise the following steps:
Step 1: comparative level is set according to input continuous wave or the peak value of pulse signal and valley, converts input signals into ECL signal by high-speed comparator, make ECL signal have the rising and falling edges time of about 40ps；
Step 2: ECL signal sends the clock port of two-way D flip-flop respectively, the high level of the data termination ECL signal of two-way D flip-flop, after the rising edge having an ECL signal arrives, D flip-flop output signal the most immediately is high；
Step 3: the reversed-phase output signal of two-way D flip-flop is sent to FPGA, after FPGA detects that the reversed-phase output signal of two-way D flip-flop is all low, postpone through 40ns, two-way D flip-flop is resetted simultaneously, forcing to draw as low by the output signal of two-way D flip-flop, now two-way D flip-flop will export a pulse signal respectively；Two-way D flip-flop positive output signal is for measuring gate, two-way measures the most corresponding event 1 of rising edge and the due in of event 2 of gate, and the trailing edge of two-way measurement gate is completely superposed, therefore the most positive and negative time interval between event 1 and event 2 can obtain by the measurement time during two-way gate height is done subtraction, and the gate time that wherein reference event is corresponding is minuend；
Step 4: send the data terminal to synchronizer trigger by measuring gate, utilizes counting clock to sample to measuring gate, obtains the signal strobe Tong Bu with counting clock, and synchronous gate signal is divided into two-way, and riches all the way delivers to clock calculation unit；Interpolation unit is together delivered to measuring gate in another road；
Step 5: send the synchronous gate signal to clock calculation unit, as the work enabling control counter chip；When synchronous gate signal is high, clock signal is counted to get the bigness scale time value measuring gate；When the signal strobe synchronized is low, the measured value of clock calculation unit is latched by the latch signal utilizing interpolation unit to provide；The trailing edge simultaneously utilizing latch signal in FPGA produces a reset signal after time delay, resets the state of enumerator；
Step 6: interpolation unit uses the mode of differential delay line to realize, measuring signal strobe is differential signal Zhong mono-tunnel, delivers to the data terminal of corresponding trigger, be fixed as TD1 every grade of time delay after postponing step by step；Synchronous gate signal is another road of differential signal, send the clock end of corresponding trigger, be fixed as TD2 every grade of time delay, arrange TD1 40ps bigger than TD2 time delay after postponing step by step；
Step 7: the rising edge measuring gate in interpolation unit leads over sync gate, lead time is zero to one clock cycle, and often after one-level delay chain, the rising edge measuring gate postpones 40ps relative to sync gate；When being arranged between M level and M+1 level, the rising edge measuring gate overlaps with sync gate rising edge, before then the rising edge of sync gate arrives after the clock end of M level trigger, the output of front M level trigger is all high level, and starting to export to afterbody trigger from M+1 level is all low level；
Step 8: two-way D flip-flop output signal sends after level conversion to FPGA, FPGA and utilizes latch signal to latch interpolative data as clock；
Step 9: after synchronous gate signal passes differential delay chain, send FPGA as latch signal after ECL signal to TTL signal level conversion, control count value and the latch of interpolated value, utilize the trailing edge of latch signal to latch count value, utilize the rising edge of latch signal to latch interpolated value；
Step 10: utilize latch signal rising edge to produce reset signal after time delay in FPGA, the state of trigger each in interpolation unit is resetted；
The interpolative data that step 11:FPGA latches is after deburring and code conversion, being converted into interpolated value, minima is 0, maximum is N, and code conversion rule is as follows: start to calculate the number of output high level from interpolation unit first order delay chain, if there being continuous N high level, conversion value is then M；
Step 12: utilize substitute into formula 1: ± TI1 → 2=TG1-TG2=IT1+IT11-IT12-(IT2+IT21-IT22)=IT1+IT11-IT2-IT21=Tclk × (N1-N2)+TD × (M1-M2) time delay of known clock cycle and every grade of delay chain
Wherein ± TI1 → 2 represent the measurement event 1 positive and negative time interval relative to event 2, IT1 represents the bigness scale time value measuring gate 1, IT11 represents the forward position remaining time value measuring gate 1 correspondence, IT12 represents the tailing edge remaining time value measuring gate 1 correspondence, Tclk represents counted clock cycle, M1 represents the front interpolated value measuring gate 1 correspondence, TD represents the temporal resolution of differential delay, the symbol definition measuring gate 2 is similar, just can be calculated the positive and negative time interval value needing to measure by above-mentioned formula.
High-precision positive and negative time interval measurement method the most as claimed in claim 1, it is characterized in that, including signal shaping with measure gate extraction unit, synchronization and interpolation unit, clock count unit, memory element, data processing unit and be connected with each other and mutually communication；Described signal shaping and measurement gate extraction unit, according to measured signal triggering level is set, continuous wave or pulse signal to input compare shaping, measured signal is converted into ECL signal, utilizes signal shaping and the trigger measured in gate extraction unit to extract the two-way signal strobe needing to measure；Described synchronization and interpolation unit, utilize the counting clock synchronized with in interpolation unit that two-way signal strobe is sampled, obtain the signal strobe Tong Bu with counting clock, riches all the way deliver to clock count unit to measure gate carry out bigness scale, another road sends and carries out front interpolation measurement to interpolation unit, completes the accurate measurement measuring gate forward position inadequate clock cycle part；Described clock count unit, utilizes the signal strobe synchronized to control the enumerator in clock count unit, completes the measurement measuring the whole counted clock cycle of gate；Described memory element, for storing clock count unit and interpolation unit measurement data；Described data processing unit processes for interpolation measurement data first goes out burr, then according to coding rule, interpolative data is converted into interpolation time value, finally calculates positive and negative time interval measurement value.
High-precision positive and negative time interval measurement method the most as claimed in claim 2, it is characterised in that the method that described burr processes is: the output valve of N position is equal to the logical "and" of N-1 position with N position input value；Primary output valve is identical with input value.
High-precision positive and negative time interval measurement method the most as claimed in claim 2, it is characterised in that described coding rule is: start to calculate the number of output high level from interpolation unit first order delay chain, if there being continuous N high level, conversion value is then M.
High-precision positive and negative time interval measurement method the most as claimed in claim 2, it is characterised in that described in calculate the formula of positive and negative time interval measurement value and be:
± TI1 → 2=TG1-TG2
=IT1+IT11-IT12-(IT2+IT21-IT22)
=IT1+IT11-IT2-IT21
=Tclk × (N1-N2)+TD × (M1-M2).
High-precision positive and negative time interval measurement method the most as claimed in claim 2, it is characterized in that, described shaping and measurement gate extraction unit include DA, High Speed ECL comparator, trigger and FPGA, by DA, comparative level is set, utilizing High Speed ECL comparator that input signal compares shaping, trigger extracts measurement signal strobe under FPGA control.
High-precision positive and negative time interval measurement method the most as claimed in claim 2, it is characterized in that, described synchronization and interpolation unit include ECL trigger, micro-strip delay line and FPGA, trigger is utilized to extract the measurement gate that original gate is Tong Bu with clock, utilize trigger and microstrip line composition difference interpolation unit, complete the accurate measurement to original gate residual time, utilize FPGA that the output of interpolation unit is carried out debounce and coded treatment simultaneously.
High-precision positive and negative time interval measurement method the most as claimed in claim 2, it is characterized in that, described clock count unit is cascaded by High Speed ECL enumerator and FPGA internal extended enumerator and constitutes, High Speed ECL enumerator uses as the low level of cascade enumerator, and it send the carry counting system signal of mono-low speed of FPGA after completing high-speed counting part.
High-precision positive and negative time interval measurement method the most as claimed in claim 2, it is characterized in that, described memory element and data processing unit are mainly realized by FPGA, FGPA utilizes the synchronous gate signal of input to produce various control signals, complete the storage to each functional unit measurement data, calculate the positive and negative time interval value needing to measure based on algorithm shown in formula 1.
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