CN104714137A - FPGA (Field Programmable Gate Array)-based measuring system and method for second signal delay time - Google Patents
FPGA (Field Programmable Gate Array)-based measuring system and method for second signal delay time Download PDFInfo
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Abstract
The invention discloses an FPGA (Field Programmable Gate Array)-based measuring system for second signal delay time. According to the system, the rising edges of a second signal to be detected and a reference second signal are detected, then the rising edges of clock signals in a fixed frequency in an FPGA are counted in the delay time of the second signal to be detected, and the delay time of the second signal to be detected is calculated through a count value and the frequency of the clock signals; a multichannel selector switch sub module is also provided, and after the delay time of a prior second signal to be detected is finished, the multichannel selector switch sub module is switched to a next second signal to be detected for measurement. According to the invention, automatic measurement of delay time of multichannel second signals is realized, and the automation of a production detection process is realized; compared with a traditional method of measuring the delay time by using an oscilloscope, the trouble of manual switchover is avoided, a measurement effect the same as that of the oscilloscope is reached, and besides, the cost of the system is much lower than the cost of the oscilloscope, so that the production cost is greatly lowered while the production measurement efficiency is improved.
Description
Technical field
The present invention relates to fields of measurement second signal delay time, more particularly, relate to a kind of measuring system and method signal delay time second based on FPGA.
Background technology
Military project system, financial sector, telecommunication system, electric system operationally all need to carry out synchronously to time, frequency, and the development of time and frequency standard is of great significance for the economy of country, science and technology and society and national defense safety.At present, the synchronous approach of the time service of time and frequency standard is developed by technological means navigation satellites such as shortwave, long wave, TVs.The cardinal principle utilizing Navsat to carry out time service synchronous is, by navigation satellite signal receiver module receiving satellite signal, realizes system time service and clock synchronization of ad according to 1PPS (pulse per second (PPS)) signal in the navigation satellite signal received.
Utilize the system of satellite navigation time service usually need in actual production to clock module export second signal time delay automatically test, traditional method of testing uses oscillograph to measure time delay, oscillographic passage 1 is received respectively by being exported by the 1PPS signal of the output of the 1PPS signal of Navsat receiver module and measured clock module, passage 2, when regulating oscillographic, base is to suitable value, and oscillograph is set to rising edge trigger state, be recorded in the spacing of synchronization two 1PPS signal rising edges, thus the measurement realized signal delay second, this measuring method can obtain accurate data, but operating process is loaded down with trivial details, particularly when measuring the time delay of multiple seconds signals, need the switching manually carrying out input signal, production efficiency can be reduced like this, and oscillographic cost is high, cause again production cost higher.
Summary of the invention
The object of the invention is to overcome above-mentioned defect of the prior art, a kind of measuring system and method signal delay time second based on FPGA is provided, main employing FPGA (Field Programmable Gate Array, field programmable gate array), automatically the time delay of multichannel signal second is measured, and precision is high, can enhances productivity, reduce costs.
For achieving the above object, technical scheme provided by the invention is as follows:
Based on measuring system signal delay time second of FPGA, comprise FPGA measurement module, benchmark signal processing module second and multiple second to be measured signal processing module; Described benchmark signal processing module second is connected FPGA measurement module respectively with signal processing module some seconds to be measured; Described benchmark signal processing module second and some seconds to be measured signal processing module be respectively used to receive benchmark signal second and second to be measured signal, and by Signal transmissions to FGPA measurement module;
Described FPGA measurement module comprises counting sub-block, calculates sub-block and clock sub-block, and described counting sub-block is connected with calculating sub-block and clock sub-block respectively;
Described clock sub-block is used for the clock signal to counting sub-block input fixed frequency;
Described counting sub-block comprises counter, counting sub-block to benchmark signal second received and second to be measured signal rising edge detect, when the rising edge of one of them second signal being detected first, start counter, counter starts to count the rising edge of clock signal, when the rising edge of another second signal being detected, stop counting;
Described calculating sub-block is used for when counting sub-block and the rising edge of one of them second signal being detected first, judge the classification of this second signal, and amount to the enumeration data of several sub-block and the frequency of clock signal, calculate signal and interval time of benchmark signal second two signal rising edges second to be measured, be the time delay of signal second to be measured.
As preferably, described FPGA measurement module also comprises a multi-channel switch sub-block, described multi-channel switch sub-block is connection count sub-block, calculating sub-block and described some measured signal processing modules respectively, after calculating sub-block and having calculated signal delay time second of signal processing module previous second to be measured, feedback information is to multi-channel switch sub-block, and multi-channel switch sub-block is switched to next second to be measured signal processing module and measures.
As preferably, also comprise a memory module, described memory module connects FGPA measurement module.
As preferably, described counting sub-block understands automatic clear before each counting.
As preferably, the frequency of described clock signal is 100MHZ-160MHZ.
As preferably, described benchmark signal receiving module second is navigation satellite signal receiver module, receives from the pps pulse per second signal in satellite-signal, and as benchmark signal second.
Adopt preceding claim system to carry out the method measured second signal delay time, comprise the following steps:
S1, start up system, multi-channel switch connect one second to be measured signaling module, FPGA measurement module receives signal and benchmark signal second second to be measured, the clock sub-block clock signal in FPGA measurement module;
S2, counter automatic clear, second to be measured signal and benchmark signal second time delay in, the rising edge of clock signal is counted, obtains count value N;
S3, calculate the time delay that sub-block goes out signal second to be measured by the frequency measurement of count value and clock signal and be:
T＝N*T
p
Wherein, T is the time delay of signal second to be measured, T
pfor the cycle of clock signal;
Store measurement result, multi-channel switch automatically switches to next second to be measured signaling module and measures, and enters step 2.
As preferably, described S2 comprises:
S201, counter automatic clear, counting sub-block to benchmark signal second received and second to be measured signal rising edge detect, when the rising edge of one of them second signal being detected first, start counter, counter starts to count the rising edge of clock signal;
S202, when the rising edge of another second signal being detected, stop counting.
As preferably, described S3 also comprises: when counting sub-block and the rising edge of one of them second signal being detected first, calculate the classification that sub-block judges this second signal.
Compared with prior art, beneficial effect of the present invention is: the automatic measurement achieving multichannel signal delay time second, and the autostore of data.Achieve the robotization of production test procedure, oscilloscope measurement time delay is utilized than traditional, the measurement effect same with oscillograph can be reached, but eliminate the trouble of manual switching, and the cost of this measuring system far below oscillographic cost, will greatly reduce production cost while raising production test efficiency.
Accompanying drawing explanation
Fig. 1 is the structural representation of system of the present invention;
Fig. 2 is the process flow diagram of measuring method of the present invention;
Fig. 3 is the particular flow sheet of step S2 in measuring method of the present invention;
Fig. 4 judges in measuring method of the present invention that signal was advanced or lagged behind the method schematic diagram of benchmark signal second second to be measured;
Fig. 5 is schematic diagram when second to be measured, signal PPS2 was ahead of benchmark signal second PPS1;
Fig. 6 is schematic diagram when second to be measured, signal PPS2 lagged behind benchmark signal second PPS1.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, technical scheme of the present invention is described in detail.
Embodiment
As shown in Figure 1, there is shown a kind of measuring system signal delay time second based on FPGA, comprise FPGA measurement module, benchmark signal processing module second and multiple second to be measured signal processing module, described FPGA measurement module comprises counting sub-block, calculate sub-block, clock sub-block and multi-channel switch sub-block, described counting sub-block is connected with calculating sub-block and clock sub-block respectively, described multi-channel switch sub-block is connection count sub-block respectively, calculate sub-block and described multiple second to be measured signal processing module, for multiple second to be measured, signal delay time measured time, calculate after sub-block calculated signal delay time second of signal processing module previous second to be measured, result of calculation is reached memory module and feedback information to multi-channel switch sub-block, multi-channel switch sub-block is switched to next second to be measured signal processing module and measures, described benchmark signal processing module second and some signal processing modules second to be measured connection count sub-block respectively, described benchmark signal processing module second and some seconds to be measured signal processing module be respectively used to receive benchmark signal second and second to be measured signal, and give counting sub-block by Signal transmissions.
In this enforcement, also comprise with memory module, described memory module connects calculating sub-block.
In this enforcement, described benchmark signal receiving module second is navigation satellite signal receiver module, receives from the pps pulse per second signal in satellite-signal, and as benchmark signal second.
In this enforcement, described counting sub-block comprises counter, counting sub-block to benchmark signal second received and second to be measured signal rising edge detect, when the rising edge of one of them second signal being detected first, start counter, counter starts to count the rising edge of clock signal, when the rising edge of another second signal being detected, stops counting.
Described calculating sub-block is used for when counting sub-block and the rising edge of one of them second signal being detected first, judge the classification of this second signal, and by carrying out the frequency of enumeration data and clock signal to the rising edge of clock signal, calculate signal and interval time of benchmark signal second two signal rising edges second to be measured, be the time delay of signal second to be measured, then result of calculation reached memory module and store.
Clock sub-block in the present embodiment is used for the clock signal to counting sub-block input fixed frequency, and the frequency of its clock signal is 100MHZ, i.e. its cycle T
p=10ns, therefore, the measuring accuracy of native system can reach 10ns.We are needed to signal second to be measured tested, mainly measure its under punctual state second signal time delay, measurement result is generally at hundreds of ns or more than 1us, so the measuring accuracy of 10ns meets our test request to module completely, therefore, the method is applicable in the middle of our production test.
Fig. 2 shows a kind of said system that adopts and carries out the method measured second signal delay time, comprises the following steps:
S1, start up system, input signal second to be measured, benchmark signal second and clock signal;
Multi-channel switch connect one second to be measured signaling module, FPGA measurement module receives 1PPS signal second to be measured and 1PPS benchmark signal second, the clock sub-block clock signal in FPGA measurement module;
S2, counter automatic clear, second to be measured signal and benchmark signal second time delay in, the rising edge of clock signal is counted, obtains count value N;
S3, calculate the time delay that sub-block goes out signal second to be measured by the frequency measurement of count value and clock signal and be:
T＝N*T
p
Wherein, T is the time delay of signal second to be measured, T
pfor the cycle of clock signal;
Store measurement result, multi-channel switch automatically switches to next second to be measured signaling module and measures, and enters step 2.
As shown in Figure 3, furthermore, described S2 comprises:
S201, counter automatic clear, counting sub-block to benchmark signal second received and second to be measured signal rising edge detect, when the rising edge of one of them second signal being detected first the rising edge of first PPS signal second (in the Fig. 3), start counter, counter starts to count the rising edge of clock signal;
S202, when the rising edge of another second signal being detected the rising edge of second PPS signal second (in the Fig. 3), stop counting.
In practice, time delay between two signals has advanced and delayed dividing, therefore, in measuring process, we are except needing to measure the time delay of signal second to be measured relative to benchmark signal second, measurement result also need to distinguish second to be measured signal and benchmark signal second before advanced or lagged relationship.In this enforcement, be that utilize measurement result positive and negative is distinguished second to be measured signal and be advanced or lag behind benchmark signal second.
As shown in Figure 4, S3 is further comprising the steps of: set benchmark signal second as PPS1, and second to be measured, signal was PPS2, and in measurement result, the most significant digit of measurement data is symbol position, and for time " 1 ", most significant digit represents that measured value is negative, then PPS2 is ahead of PPS1; Most significant digit is represent that measured value is just for " 0 ", then PPS2 lags behind PPS1.Such as: when PPS2 is ahead of PPS1 (as shown in Figure 5), time delay Δ T=20, time delay interval record Ying is – Δ T, and now the measurement result of system is recorded as: 10000020; When PPS2 lags behind PPS1 (as shown in Figure 6), time delay interval record should be+Δ T, and now measuring results is recorded as: 000000020.
In sum, compared with prior art, present invention achieves the automatic measurement of multichannel signal delay time second, and the autostore of data.Achieve the robotization of production test procedure, oscilloscope measurement time delay is utilized than traditional, the measurement effect same with oscillograph can be reached, but eliminate the trouble of manual switching, and the cost of this measuring system far below oscillographic cost, will greatly reduce production cost while raising production test efficiency.
The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (9)
1., based on measuring system signal delay time second of FPGA, it is characterized in that, comprise FPGA measurement module, benchmark signal processing module second and multiple second to be measured signal processing module; Described benchmark signal processing module second is connected FPGA measurement module respectively with signal processing module some seconds to be measured; Described benchmark signal processing module second and some seconds to be measured signal processing module be respectively used to receive benchmark signal second and second to be measured signal, and by Signal transmissions to FGPA measurement module;
Described FPGA measurement module comprises counting sub-block, calculates sub-block and clock sub-block, and described counting sub-block is connected with calculating sub-block and clock sub-block respectively;
Described clock sub-block is used for the clock signal to counting sub-block input fixed frequency;
Described counting sub-block comprises counter, counting sub-block to benchmark signal second received and second to be measured signal rising edge detect, when the rising edge of one of them second signal being detected first, start counter, counter starts to count the rising edge of clock signal, when the rising edge of another second signal being detected, stop counting;
Described calculating sub-block is used for when counting sub-block and the rising edge of one of them second signal being detected first, judge the classification of this second signal, and amount to the enumeration data of several sub-block and the frequency of clock signal, calculate signal and interval time of benchmark signal second two signal rising edges second to be measured, be the time delay of signal second to be measured.
2. measuring system signal delay time second based on FGPA according to claim 1, it is characterized in that, described FPGA measurement module also comprises a multi-channel switch sub-block, described multi-channel switch sub-block is connection count sub-block, calculating sub-block and described some measured signal processing modules respectively, after calculating sub-block and having calculated signal delay time second of signal processing module previous second to be measured, feedback information is to multi-channel switch sub-block, and multi-channel switch sub-block is switched to next second to be measured signal processing module and measures.
3. measuring system signal delay time second based on FGPA according to claim 1, is characterized in that, also comprise a memory module, and described memory module connects FGPA measurement module.
4. measuring system signal delay time second based on FGPA according to claim 1, is characterized in that, described counting sub-block can automatic clear before each counting.
5. measuring system signal delay time second based on FGPA according to claim 1, is characterized in that, the frequency of described clock signal is 100MHZ-160MHZ.
6. measuring system signal delay time second based on FGPA according to claim 1, is characterized in that, described benchmark signal receiving module second is navigation satellite signal receiver module, receives from the pps pulse per second signal in satellite-signal, and as benchmark signal second.
7. adopt the system described in any one of claim 1 to 6 to carry out the method measured second signal delay time, it is characterized in that, comprise the following steps:
S1, start up system, multi-channel switch connect one second to be measured signaling module, FPGA measurement module receives signal and benchmark signal second second to be measured, the clock sub-block clock signal in FPGA measurement module;
S2, counter automatic clear, second to be measured signal and benchmark signal second time delay in, the rising edge of clock signal is counted, obtains count value N;
S3, calculate the time delay that sub-block goes out signal second to be measured by the frequency measurement of count value and clock signal and be:
T＝N*T
p
Wherein, T is the time delay of signal second to be measured, T
pfor the cycle of clock signal;
Store measurement result, multi-channel switch automatically switches to next second to be measured signaling module and measures, and enters step 2.
8. method according to claim 7, is characterized in that, described S2 comprises:
S201, counter automatic clear, counting sub-block to benchmark signal second received and second to be measured signal rising edge detect, when the rising edge of one of them second signal being detected first, start counter, counter starts to count the rising edge of clock signal;
S202, when the rising edge of another second signal being detected, stop counting.
9. method according to claim 7, is characterized in that, described S3 also comprises: when counting sub-block and the rising edge of one of them second signal being detected first, calculates the classification that sub-block judges this second signal.
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