CN102215994A - 基于微电子制造技术制造键合线的方法及器件 - Google Patents

基于微电子制造技术制造键合线的方法及器件 Download PDF

Info

Publication number
CN102215994A
CN102215994A CN2009801463099A CN200980146309A CN102215994A CN 102215994 A CN102215994 A CN 102215994A CN 2009801463099 A CN2009801463099 A CN 2009801463099A CN 200980146309 A CN200980146309 A CN 200980146309A CN 102215994 A CN102215994 A CN 102215994A
Authority
CN
China
Prior art keywords
opening
template
substrate
diameter
bonding line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2009801463099A
Other languages
English (en)
Other versions
CN102215994B (zh
Inventor
M·莱尔
F·屈兴麦斯特
F·泽里格
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN102215994A publication Critical patent/CN102215994A/zh
Application granted granted Critical
Publication of CN102215994B publication Critical patent/CN102215994B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B21—MECHANICAL METAL-WORKING WITHOUT ESSENTIALLY REMOVING MATERIAL; PUNCHING METAL
    • B21C—MANUFACTURE OF METAL SHEETS, WIRE, RODS, TUBES OR PROFILES, OTHERWISE THAN BY ROLLING; AUXILIARY OPERATIONS USED IN CONNECTION WITH METAL-WORKING WITHOUT ESSENTIALLY REMOVING MATERIAL
    • B21C3/00—Profiling tools for metal drawing; Combinations of dies and mandrels
    • B21C3/02—Dies; Selection of material therefor; Cleaning thereof
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B21—MECHANICAL METAL-WORKING WITHOUT ESSENTIALLY REMOVING MATERIAL; PUNCHING METAL
    • B21C—MANUFACTURE OF METAL SHEETS, WIRE, RODS, TUBES OR PROFILES, OTHERWISE THAN BY ROLLING; AUXILIARY OPERATIONS USED IN CONNECTION WITH METAL-WORKING WITHOUT ESSENTIALLY REMOVING MATERIAL
    • B21C3/00—Profiling tools for metal drawing; Combinations of dies and mandrels
    • B21C3/02—Dies; Selection of material therefor; Cleaning thereof
    • B21C3/04—Dies; Selection of material therefor; Cleaning thereof with non-adjustable section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/745—Apparatus for manufacturing wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/432—Mechanical processes
    • H01L2224/4321—Pulling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/438—Post-treatment of the connector
    • H01L2224/4383—Reworking
    • H01L2224/43847—Reworking with a mechanical process, e.g. with flattening of the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48724—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/745—Apparatus for manufacturing wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)

Abstract

用于精密键合应用的键合线(252A)可基于相应的模板器件(200)而有效率地形成，该模板器件可基于例如硅的半导体材料(201)并结合例如光刻和蚀刻技术的相关制造技术而形成。所以，任何适当的直径和截面形状可以高度准确性和可靠性来获得。

Description

基于微电子制造技术制造键合线的方法及器件
技术领域
本发明大致上是有关线键合，更具体的是有关用于制造键合线的技术和器件。
背景技术
集成电路的制造牵涉许多复杂的工艺步骤以于适当的半导体材料中和半导体材料上形成例如晶体管、电容器、电阻器等电路组件。在最近几年，在提升集成电路的积体密度和整体功能性上已有巨大的进步。这些进步是通过将个别电路组件缩小至深次微米(deep sub-micrometer)范围的尺寸而达成，其中目前使用的关键尺寸(例如场效晶体管的闸极长度)为30nm和更小。所以，可在晶粒(die)中设置数百万个电路组件而使得可设计复杂的连接构造，其中，每个电路组件可电性地连接至一个或多个其它电路组件。这些互连结构典型是以类似多层印刷电路板(multi-level printed circuit board)的方式建立在包括一个或多个接线级(wiring level)的金属化***中，其中，适当的金属特征是依据所考虑的电路配置而形成，然而，该金属特征的尺寸必需适应半导体电路组件(例如晶体管等)的尺寸。
在制造集成电路的进阶阶段中，通常需要封装芯片并设置导线(lead)和接点(terminal)以将该芯片电路与周围连接。用于将芯片与封装件连接的广为接受的方法包含线键合(wire bonding)技术，该技术已经在过去数十年期间以铝为基础而成功地发展，并且仍然广为接受并代表了用于连接大多数主要半导体芯片至载体衬底的优势技术，其中，通常，是设置铝基(aluminum-based)键合垫，其通过由铝、铜、金等所制成的适当线所接触。在线键合工艺期间，该键合线与该键合垫接触，并且在施加压力、提高温度和超音波能量之后，该线会焊接至该键合垫以形成介金属(intermetallic)连接。
依照这个方法，在集成电路的金属化***与任何周围的组件(例如衬底封装件等)之间可建立可靠的电性连接。由于精密的半导体器件的特征尺寸持续缩小，集成电路的复杂度会持续增加，从而也需要增加I/O(输入/输出)能力，并因此导致需要增加设置在适当位置(如芯片周围)的键合垫的数目。所以，键合垫的尺寸以及节距(pitch)会缩减，从而需要精密的线键合技术用于置放及连接键合线至相应的键合垫。因此，键合线的直径也必需缩小以符合键合垫的缩减的侧向尺寸，并且也不会导致不当地浪费宝贵的原料，例如金等。典型上，键合线是通过将预处理的线拉穿过具有适当开口形成在其中的相应的钻石晶体而形成，该开口的宽度实质上决定该键合线的所需目标直径。
图1图示地说明用于提供具有所需目标直径的键合线的设备150的示意图。如图所示，是设置有材料源151以供应键合线的预制件(perform)152，例如金线、铜线、铝线等，然而该等线的直径可能没有相应所需要的直径152D。此外，该设备150包括配置成当预制件152被拉穿过开口102时作为模板的器件100，该开口102形成在由钻石晶体组成的主体101中。由于该开口102(其是作为模板)的互动，该预制件152可缩减至所需要的目标直径152D，从而获得可使用来连接至键合垫的键合线152A，如上所述。当缩减该目标直径152D时，亦必须形成具有个别开口102的相应的钻石晶体，该开口102典型通过在该钻石晶体主体钻出相应的洞而形成，因而需要精密的机械工具和技术。因此，精密的键合线的目标尺寸的精确控制是依据形成在钻石主体101中的相应模板洞102的精确度。因此，改变键合线的直径是与设置适当器件100所作的大量努力有关，其中该器件100是基于牵涉以机械方式将相应开口钻入结晶主体中的传统技术人员。
本发明是有关可以避免或至少缩减以上所述的一个或多个问题的影响的各种方法和器件。
发明内容
下文提出本发明的简单概述，以便提供本发明某些态样的基本了解。此概述并非本发明广泛的详尽综论。其无意用来识别本发明的关键或重要组件，或用来描绘本发明的范畴。其唯一目的是以简化形式呈现一些概念作为稍后更详细说明的引言。
一般而言，本发明是关于一种技术与器件，其可用来以对于选择键合线的所需目标尺寸的高度灵活性来提供精密的键合线，同时仍然提供有效率的制造工艺以设置个别的模板器件。为了这个目的，适当的半导体材料可使用来作为衬底以在其内形成适当的模板开口以定义键合线的所需目标直径。例如，结晶硅材料可有效率地使用来作为适当的基底，以在其中形成适当的开口，这可基于广为接受的微机械或微电子制造技术而完成，使得可对于选择所需的目标直径、相应的键合线的截面形状和其中形成有相应模板开口的基底或主体材料的整体机械和几何配置的适当调适提供高度的灵活性。就此而言，应该了解在此使用的名词“直径”应理解为开口或是键合线的截面尺寸，其中，该开口和该键合线的截面形状并非一定是圆形，而可以是由任何的适当形状所代表。在此例中，该“直径”可指称任何可能的截面尺寸中的最大一个。例如，对于相应开口的正方形截面形状，该“直径”可由该正方形的对角线来代表。
因此，通过应用广为接受的微机械或微电子制造技术，例如基于光刻(lithography)和相关的蚀刻技术等，相应的模板开口能以高度的准确性来设置，同时也可使用大范围的适当材料(例如硅)结合其它坚固和高度稳定的材料(例如氮化硅、二氧化硅等)。因此，不只是相应模板开口的截面形状和直径能以高度精确性及高度重制性来设置，同时也可例如通过选择衬底材料(例如硅衬底)的适当厚度来调整相应的模板开口的适当长度，而这可通过利用沉积来添加另外的材料、利用蚀刻和/或研磨技术来去除材料而完成，然而在其它例子中，除了上述技术外、或取代以上技术，可以使用适当的衬底键合工艺以结合各种衬底(例如半导体晶圆)，该晶圆可以在键合之前或之后加以处理以获得所需的模板开口。
一种用于制备在此揭露的键合线的示范模板器件包括由半导体材料组成的主体，以及延伸穿过该主体并具有直径的模板开口，在沿着该模板材料的深度方向的至少一区段，该直径是相应该键合线的目标直径。
一种用于形成键合线的示范设备是包括用于传送键合线的预制件的材料源。此外，该设备包括连接至该材料源且包括主体的该模板器件，该主体由半导体材料构成并具有形成在其中的模板开口延伸穿越该主体。该模板开口具有直径，在沿着该模板开口的深度方向的至少一区段，该直径是相应该键合线的目标直径。此外，该设备包括拉动机构，其是配置成将该材料源所供应的该预制件拉穿过该模板开口。
一种在此揭露的示范方法是包括形成穿过衬底的开口，该衬底包括半导体材料，其中，该开口具有直径，在沿着深度方向的至少一个位置，该直径是相应键合线的目标直径。此外，该方法包括将该键合线的预制件拉穿过该开口以获得具有由该开口所定义的直径的该键合线。
附图说明
本发明可通过参照上述描述并配合随附图式而了解，其中，相同的组件符号标示相同的组件，并且，其中：
图1图示说明用于基于使用包含相应的模板开口的钻石晶体的预制件供应键合线的传统设备，该相应的模板开口是用于定义该键合线的最终直径；
图2a至图2b依据一例示性实施例图示说明在形成穿孔的各种制造阶段期间的半导体衬底的截面图，该穿孔定义键合线的直径，其中，可使用蚀刻技术；
图2c依据一例示性实施例图示说明当调整半导体衬底的厚度以获得相应穿孔的所需长度以形成键合线时的半导体衬底的截面图；
图2d至图2e依据进一步的例示性实施例图示说明在调适衬底材料的厚度的不同的制造阶段期间的半导体衬底的截面图，其中，是通过沉积来进行上述调适以增加相应穿孔的长度，以定义适当的键合线直径；
图2f依据更进一步的例示性实施例图示说明在执行键合工艺以获得增加的衬底总厚度之前的两个半导体衬底的截面图，其中，在键合之前或之后，可依据需要形成个别的穿孔以用于设置用来形成键合线的模板器件；
图2g至图2j依据又另一个例示性实施例图示说明个别衬底部分的上视图，该衬底部分的中已形成相应的模板穿孔，用于调整键合线的相应的直径和截面形状；以及
图2k依据又另一个例示性实施例图示说明基于模板器件形成键合线的设备，该模板器件是基于半导体材料而形成。
虽然此处所揭示的标的内容容许各种修改和替代形式，然该等标的内容的特定实施例已通过图式中的实例显示并且予以详细说明。然而，应了解到此处特定实施例的说明并不欲限制本发明于所揭示的特定形式，反之，本发明将涵盖所有落于由所附的权利要求所界定的精神和范围内的所有的修饰、等效、和改变。
具体实施方式
以下叙述本发明的各种例示实施例。为求清楚，在此说明书中并未描述实际实作的所有特征。当然，将了解到在任何此种实际实施例的开发中，必须作出许多实作特定的决定以达成开发人的特定目标，譬如符合***相关或商业相关的限制，这些决定将依实作而变化。此外，将了解到，此种开发效果可能是复杂且耗时的，不过这对藉助于此揭露的该技术领域中具有通常知识人员而言是例行工作。
现将参考附图来说明本发明。各种结构、***和器件是示意地绘示于图式中仅为了说明的目的，以便不会由熟悉此项技术着已熟知的细部而模糊了本发明。不过，仍包含附图以说明与解释本发明的例示范例。应以熟悉该项技艺人员所认定的意义来了解与解释本文中的字汇与词。本文前后一致使用的术语以及词汇并无暗示特别的定义，特别定义是指与熟悉该项技艺人员认知的普通惯用的定义所不同的定义。如果一个术语或词汇具有特别定义，亦即非为熟悉该项技艺人员所了解的义意时，本说明书将会直接且明确的提供其定义。
一般而言，本发明是提供可基于广为接受的工艺技术而有效率地决定键合线的截面形状和直径的技术与器件，如同在制造微电子器件或微机械器件时所使用者。也就是说，与传统使用的钻石晶体相反，是使用例如硅、二氧化硅、氮化硅等其它适当的材料，并加以处理以获得相应的模板开口或穿孔，其中，相应的直径可基于广为接受的工艺技术而精确地调整。因此，能以有效方式产生所需数量的模板器件，例如，基于半导体晶圆来产生模板器件，其中，该晶圆可被分开以提供展示高度一致性的相应数量的器件。在其它例子中，多种不同的模板开口可在共同的制造顺序予以形成，这是因为这些开口的直径可基于具有相应需要的截面形状和直径的个别掩膜特征的光刻掩膜而有效率地定义。此外，也有制造技术可有效率地沿着相应穿孔的整个长度适当地调适截面直径，例如，通过适当调整蚀刻参数以在相应的蚀刻工艺期间提供不同的侧壁角度。此外，当基本衬底材料的厚度被视为不足时，相应穿孔的整个长度可通过广为接受的技术(例如材料层的沉积)有效率地调整。在其它例子中，基本的衬底材料可以例如通过蚀刻研磨等予以薄化，以获得用于相应穿孔的所需长度。此外，根据广为接受的技术，可使用晶圆键合技术以结合两个或更多个衬底材料，从而提供产生更厚的合成衬底材料的可能性，其中，相应的厚度可接着基于蚀刻技术、研磨技术等而细微调整。因此，通过使用适当的半导体材料，例如硅等，并可能结合相关且广为接受的材料组成，例如以二氧化硅、氮化硅、碳化硅等的形式，可以达成优良的机械特性，同时也典型地达成高温稳定性。因此，这些材料很适合用于形成相应的模板开口于其中，该模板开口是用于调整键合线的形状和尺寸，同时额外地，可针对该模板开口的截面形状和尺寸提供高度的灵活性，同时也达成高度的精确性和重制性。
参照图2a至图2k，现在加以描述进一步的说明实施例，其中，假如适当的话，也可参考图1。
图2a图标说明器件200，其也可被称为模板器件，因为其可使用作为“模板”，以基于相应的预制件形成键合线，该预制件例如为具有增加直径的线材料，其必需缩减成所需直径，该模板并可能用于调适该键合线的截面形状。该模板器件200可包括由例如硅、碳化硅、硅/锗等典型以晶体材料形式提供的半导体材料所形成的衬底201。例如，硅晶圆、碳化硅晶圆等可立即取得，并且可基于典型使用在半导体生产设施等的工艺工具和制造技术而加以处理。因此，衬底201具有定义完善的厚度201T以及定义完善的材料组成。应了解到，厚度201T可通过适当地切削相应的半导体晶体而加以调整，同时，在其它情况中，可使用相应的可取用的半导体衬底，其中，所需厚度201T可基于制造技术而予以调整，如稍后所详加解释。此外，衬底201具有定义完善的直径和形状，其中，在某些说明实施例中，可使用晶圆从而提供基于广为接受且可用的半导体制造工具而处理该器件200的可能性。然而，应该了解，在此揭露的原理也可应用至任何所需形式的衬底201。例如，该衬底201的直径可介于100至300mm的范围，其可代表也使用于半导体制造的广为接受的直径。同样地，对于可用的半导体衬底，该厚度201T的范围是从约100微米至数百微米，同时也可基于该衬底201的进一步处理而获得不同值的该厚度201T。此外，在所显示的制造阶段中，该器件200可在衬底201的上形成蚀刻掩膜210，例如光阻掩膜(resist mask)，并可能结合硬掩膜材料(未图示)，该硬掩膜材料是理解为可承受较高温度及与光阻材料相比具有较高蚀刻抵抗性的任何适当材料。例如，该蚀刻掩膜210包括例如二氧化硅、氮化硅等任何适当材料，依据整体工艺策略可能结合光阻材料。该蚀刻掩膜210包括复数个开口210A，其具有同样的截面形状及相同的直径，而在其它例子中，至少某些该开口210A具有不同的直径和/或不同的截面形状。应该要了解到，每个该开口210A代表将形成在该衬底201的特定部分中的相应模板开口，如有需要，该衬底201在稍后的制造阶段中可以分离，以提供具有基于该蚀刻掩膜210而形成的指定模板开口的个别模板器件的相应主体。例如，依据相应键合线的所需目标直径，该开口210A具有约30至150μm的直径。然而，应该要了解，可以选择任何其它的适当直径。
在图2a中所示范的器件200可基于以下工艺而形成。在例如以硅衬底等形式提供该衬底201之后，可以例如通过沉积例如二氧化硅、氮化硅、碳化硅等任何适当材料形成硬掩膜材料，接着沉积光阻材料，该光阻材料接着基于广为接受的光刻技术而曝光。之后，该光阻材料或该硬掩膜材料可依据广为接受的技术基于经曝光及显影(developed)的光阻材料而被图案化。之后，可将该器件200暴露于蚀刻环境204，该蚀刻环境204是基于适当的电浆环境和适当的先驱材料而建立，以获得用于相对于该蚀刻掩膜210选择性蚀刻该衬底201的材料的应的反应化学作用。为了这个目的，有复数个广为接受的工艺配方可用，例如基于含氟或含氯的蚀刻化学作用，以相对于光阻材料、二氧化硅、氮化硅等选择性地蚀刻硅材料。应了解到，用于蚀刻深开口至例如硅等半导体材料中的个别蚀刻工艺是广为接受的，因为相似的技术也可使用在沟槽蚀刻工艺以形成深电容器，同时，在其它例子中，相应的穿孔典型是设置在使用于堆栈芯片配置的半导体衬底中，其中，该相应的穿孔可填充导电性材料以提供互相堆栈的不同芯片之间的电性连接，从而形成三维芯片配置。因此，相应的蚀刻配方可用来形成相应的开口至衬底材料201中。此外，可以调整这些非等向性蚀刻技术的工艺参数以获得所需的蚀刻行为，也就是，可通过适当选择的工艺参数形成相应的锥形(tapered)开口，该工艺参数是例如典型可添加到反应性蚀刻环境的聚合物种的浓度，以控制侧向蚀刻率。因此，提供了沿着该衬底201的深度或厚度调整直径的高度灵活性，以适当地使该直径的变化适应于用以有效率地将键合线拉穿过相应开口的机械需求。
图2b图示说明在进一步进阶的制造阶段的器件200。如图所示，相应的开口202是穿过该衬底201而形成，其中，由该虚线所指示的相应锥形程度可以基于以上参照图2a所讨论的蚀刻工艺204的工艺参数而调整。应该要了解，假如需要的话，适当的蚀刻停止材料能以反向于蚀刻掩膜210(图2a)的方式形成在衬底201上。该相应的蚀刻停止材料可基于任何适当的选择性蚀刻配方而有效率地去除。相似地，该蚀刻掩膜210可基于广为接受的蚀刻配方而去除。所以，该衬底201可分离成个别主体201A、201B…(例如，通过广为接受的晶圆切割技术)，并且随后可使用作为用于形成所需的目标直径和截面形状的键合线的设备中的模板器件，如稍后的叙述。
图2c图示说明依据进一步的说明实施例的该器件200，其中，初始厚度201T可以例如通过去除工艺205而缩减，该工艺205包含机械研磨工艺。例如，化学机械研磨(CMP)是在半导体生产中广为接受的制造技术，并且可有效率地使用于去除衬底201的材料以获得缩减的厚度201R，该厚度201R可被视为适合于将形成在衬底201中的穿孔(例如基于如先前参照图2a至图2b所描述的相应制造技术)的相应长度。
图2d图示说明依据进一步的说明实施例的器件200，其中，该初始厚度201T可通过沉积适当材料203(例如可相应衬底201的材料的半导体材料，例如硅材料)而增加，沉积该材料203可通过外延生长技术、低压化学气相沉积(CVD)、电浆强化沉积技术等而达成。因此，增加的厚度201S可以通过额外层203而获得。在其它例子中，可提供该材料203以调整器件200关于后续作为用于形成键合线的模板器件的特定材料特性。例如，假如需要经调适的表面特性的话，该材料203可以特定成分沉积和/或可以执行该衬底201的个别表面处理。例如，碳化硅、氮化硅等可代表高温稳定性及高机械完整性的材料，其可有效率地用来提供特定的表面条件，以及也可用来作为用于获得器件200的所需增加的整体厚度的缓冲材料。
图2e图示说明在进一步的进阶制造阶段中的该器件200，其中，形成开口202以延伸穿过该层203以及该衬底201。为了这个目的，可以如上所述使用相似的工艺技术，其中，例如，第一蚀刻步骤会蚀刻穿越该层203，之后适当地应用蚀刻化学剂以蚀刻穿越该衬底201。同时，在这个例子中，假如需要的话，可以使用相应的蚀刻停止材料和硬掩膜材料。
图2f依据进一步的说明实施例图标说明器件200，其中，该衬底201由两个或更多个独立衬底201L、201U组成，其可基于广为接受的晶圆键合技术连结，以形成复合衬底。例如，硅晶圆可通过施加热和压力而有效率地键合。在其它例子中，该衬底201U、201L可以加以处理以获得适当的表面层，例如二氧化硅层，这可依据广为接受的工艺技术，通过将这些衬底暴露于氧化环境而达成。同时，在这个例子中，该衬底201U、201L可以基于广为接受的配方而键合。应该要了解，在键合工艺之前，其它材料可以设置在该衬底201U、201L的相应表面区域上。例如，氮化硅、碳化硅等也可使用作为键合表面。在某些说明实施例中，每个衬底201U、2011可能已经被处理过以容置相应的开口202，该开口202可基于以上描述的工艺技术而形成。尽管该衬底201L、201U可以分开处理，但由于非常精确的工艺技术，该开口202仍然可互相对齐(align)。在又另一个说明实施例中，该衬底201U、201L可以先键合，然后加以处理以获得开口202。例如，中间材料层，像二氧化硅层、氮化硅层等，可以有效地使用作为蚀刻停止材料，使得可以达成蚀刻工艺的强化控制性。在其它例子中，该蚀刻工艺可以从两面进行，例如假如需要的话，处理一面之后再处理另一面。同时，在这个例子中，高度的准确性可导致在不同的蚀刻步骤中所形成的相应开口的精确对齐。应该要了解，可以结合以上叙述用来修改该原始衬底201的厚度的每个技术，以获得所需的目标厚度。例如，假如需要非常厚的衬底，可将相应数目的个别衬底键合在一起，之后可以通过先前叙述的一种或多种工艺技术而完成细微调整，例如通过研磨复合衬底的表面或是通过沉积额外的材料层来完成细微调整。在其它情况中，个别衬底或衬底复合物可以在中间阶段进行处理，也就是，在将所有的衬底键合在一起之前避免处理非常厚的衬底，非常厚的衬底可能不兼容于目前可用的半导体工艺工具的衬底处理能力。
图2g至图2j图示说明该模板开口202的各种截面形状的上视图。图2g图示说明该模板开口202具有直径202D的实质圆形，该直径202D可依据用于形成该键合线的任何需求予以选择。图2h图示说明该模板开口202为六角形形状，其中，该直径202D可基于相应的目标值而调整。相似地，图2i与图2j说明该开口202的截面形状的进一步例子。然而，应该要了解，可以基于先前描述的光刻和蚀刻技术定义任何其它所需的截面形状。因此，可以达成调整相应键合线的直径和截面形状的高度灵活性，从而允许在键合程序期间将键合线的机械特性调整至某种程度。
图2k图示说明用于提供键合线252A的设备250，该键合线252A具有所需的目标直径252D和所需的截面形状。该设备250包括材料源251，该材料源251配置成供应键合线252A的预制件252。例如，该预制件252能以金材料、铝材料、铜材料或任何其它键合材料的形式提供。此外，包含主体201A的该模板器件200是机械地连接至该材料源251，该主体201A包括半导体材料，例如硅、碳化硅、硅/锗等。在一个说明实施例中，该主体201A是由晶体硅材料组成。如之前所指出的，该主体201A包括具有相应的截面形状与直径的模板开口202，其中，该直径会沿着主体201A的深度或厚度而改变，如先前所述。例如，该开口202可设置成锥形开口的形式，以适应于在将该预制件252拉穿过该模板开口202期间可能产生的机械应力。该相应的拉力可通过相应的拉动器件253供应，该器件253具有如本领域中已广为接受的任何适当的配置。因此，基于该模板器件200，可以将该预制件252拉穿过该模板开口202，从而获得具有所需目标直径252D的键合线252A，其中，该目标直径252D是由开口202决定。所以，由于用于形成器件200的高度有效和精确的制造技术，任何适当的截面形状和直径可以基于高效率和高重制性工艺而获得。
因此，本发明提供了用于形成键合线的设备、模板器件和相应方法，其中，广为接受的半导体制造技术可结合适当的半导体材料而使用，以提供适当的模板器件。因此，任何需要的目标尺寸和截面形状，可通过设置具有高度精确性和重制性的相应模板器件而产生。
以上所揭示的特定实施例仅作例示用，因为对于熟悉该技术领域人员而言，藉助此处的教示而能以不同但等效的方式修改及实施本发明是显而易见的。例如，以上所提出的工艺步骤可以不同顺序执行。再者，除了以下附加的权利要求所叙述之外，在此所示的架构或设计细节并非意欲限制。因此，很明显的是，可改变或修改以上所揭示的特定实施例，并且所有此等变化是视为在本发明的精神和范围内。由此，本发明所要求保护的是如以下权利要求所提出者。

Claims (15)

1.一种用于制备键合线的模板器件(200)，该模板器件包括：
主体，由半导体材料(201)构成；以及
模板开口(202)，延伸穿过该主体并具有直径，在沿着该模板开口(202)的深度方向的至少一区段，该直径是相应该键合线(252A)的目标直径。
2.如权利要求1所述的模板器件，其中，该模板开口(202)的该直径为约50μm或更小。
3.如权利要求1所述的模板器件，其中，该模板开口(202)具有非圆形的截面。
4.如权利要求1所述的模板器件，其中，该模板开口(202)的宽度沿着该深度方向增加。
5.如权利要求1所述的模板器件，其中，该模板开口(202)的深度是在约100至5000μm的范围中。
6.一种用于形成键合线的设备，该设备包括：
材料源，用于传送键合线(252A)的预制件(252)；
模板器件(200)，连接至该材料源，该模板器件(200)包括由半导体材料(201)构成的主体并具有形成在该主体中而延伸穿过该主体的模板开口(202)，该模板开口(202)具有直径，在沿着该模板开口的深度方向的至少一区段，该直径是相应该键合线(252A)的目标直径；以及
拉动机构(253)，配置成将该材料源所供应的该预制件(252)拉穿过该模板开口(202)。
7.如权利要求6所述的设备，其中，该模板开口的该直径是约50μm或更小。
8.如权利要求6所述的设备，其中，该模板开口具有非圆形的截面。
9.如权利要求6所述的设备，其中，该模板开口的宽度沿着该深度方向变化。
10.如权利要求6所述的设备，其中，该开口的深度是在约100至5000μm的范围中。
11.一种方法，包括：
形成穿过衬底的开口(202)，该衬底包括半导体材料(201)，该开口(202)具有直径，在沿着深度方向的至少一位置，该直径是相应键合线(252A)的目标直径；以及
将该键合线的预制件(252)拉穿过该开口(202)以获得具有由该开口(202)所定义的直径的该键合线。
12.如权利要求11所述的方法，其中，形成该开口是包括在该衬底之上形成蚀刻掩膜以及利用该蚀刻掩膜执行蚀刻工艺。
13.如权利要求11所述的方法，进一步包括通过在该衬底上沉积材料层和去除该衬底的材料的至少其中一个来调整该衬底的厚度。
14.如权利要求11所述的方法，进一步包括通过将第一衬底键合至至少另一个衬底以形成该衬底。
15.如权利要求14所述的方法，其中，形成该开口是包括在该第一衬底中形成第一开口和在该至少另一个衬底中形成第二开口，其中，该第一和第二开口互相对齐。
CN200980146309.9A 2008-10-31 2009-10-30 基于微电子制造技术制造键合线的方法及器件 Expired - Fee Related CN102215994B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102008054077.3A DE102008054077B4 (de) 2008-10-31 2008-10-31 Verfahren und Vorrichtung zur Herstellung von Bonddrähten auf der Grundlage mikroelektronischer Herstellungstechniken
DE102008054077.3 2008-10-31
US12/562,556 US8561446B2 (en) 2008-10-31 2009-09-18 Method and device for fabricating bonding wires on the basis of microelectronic manufacturing techniques
US12/562,556 2009-09-18
PCT/US2009/005894 WO2010062357A1 (en) 2008-10-31 2009-10-30 Method and device for fabricating bonding wires on the basis of microelectronic manufacturing techniques

Publications (2)

Publication Number Publication Date
CN102215994A true CN102215994A (zh) 2011-10-12
CN102215994B CN102215994B (zh) 2016-02-10

Family

ID=42096315

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200980146309.9A Expired - Fee Related CN102215994B (zh) 2008-10-31 2009-10-30 基于微电子制造技术制造键合线的方法及器件

Country Status (6)

Country Link
US (1) US8561446B2 (zh)
KR (1) KR101498174B1 (zh)
CN (1) CN102215994B (zh)
DE (1) DE102008054077B4 (zh)
TW (1) TWI492322B (zh)
WO (1) WO2010062357A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010031993B4 (de) * 2010-07-22 2015-03-12 Heraeus Materials Technology Gmbh & Co. Kg Verfahren zur Herstellung eines Bonddrahtes, Bonddraht und Baugruppe, die einen solchen Bonddraht aufweist.

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1115937B (de) 1952-08-19 1961-10-26 Standard Elektrik Lorenz Ag Verfahren zur plastischen Verformung von Germanium und Silicium
US3605476A (en) * 1969-02-17 1971-09-20 Battelle Development Corp Metal drawing method and apparatus
US4003369A (en) * 1975-04-22 1977-01-18 Medrad, Inc. Angiographic guidewire with safety core wire
US4464922A (en) * 1978-12-12 1984-08-14 Marshall Richards Barcro Limited Wire drawing method and apparatus
US4397080A (en) * 1980-11-10 1983-08-09 Me-U-Sea, Inc. Process for preparation of support tooling for extrusion dies
JPS57109519A (en) * 1980-12-27 1982-07-08 Ngk Spark Plug Co Ltd Die
DE3139796A1 (de) 1981-10-07 1983-04-21 Werner 6349 Hörbach Henrich Ziehstein
US4938244A (en) * 1987-10-05 1990-07-03 Murata Manufacturing Co., Ltd. Temperature difference detecting element using semiconductive ceramic material
US5636545A (en) * 1995-07-07 1997-06-10 General Electric Company Composite diamond wire die
US6479395B1 (en) * 1999-11-02 2002-11-12 Alien Technology Corporation Methods for forming openings in a substrate and apparatuses with these openings and methods for creating assemblies with openings
US6623579B1 (en) * 1999-11-02 2003-09-23 Alien Technology Corporation Methods and apparatus for fluidic self assembly
US7301199B2 (en) * 2000-08-22 2007-11-27 President And Fellows Of Harvard College Nanoscale wires and related devices
US6815736B2 (en) * 2001-02-09 2004-11-09 Midwest Research Institute Isoelectronic co-doping
JP4463482B2 (ja) * 2002-07-11 2010-05-19 パナソニック株式会社 Ｍｉｓｆｅｔ及びその製造方法
US6871523B2 (en) * 2003-03-31 2005-03-29 Matsushita Electric Industrial Co., Ltd. Method and apparatus for forming microchannels in a filament wire
US7131308B2 (en) * 2004-02-13 2006-11-07 3M Innovative Properties Company Method for making metal cladded metal matrix composite wire
US7319252B2 (en) * 2004-06-28 2008-01-15 Intel Corporation Methods for forming semiconductor wires and resulting devices
US7344961B2 (en) * 2004-07-07 2008-03-18 Nanosys, Inc. Methods for nanowire growth
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
US20060281321A1 (en) * 2005-06-13 2006-12-14 Conley John F Jr Nanowire sensor device structures
US20070090849A1 (en) * 2005-10-24 2007-04-26 Romi Mayder Method and apparatus for a DUT contactor
US20080008844A1 (en) * 2006-06-05 2008-01-10 Martin Bettge Method for growing arrays of aligned nanostructures on surfaces
US20080014689A1 (en) * 2006-07-07 2008-01-17 Texas Instruments Incorporated Method for making planar nanowire surround gate mosfet
FR2905197B1 (fr) * 2006-08-25 2008-12-19 Commissariat Energie Atomique Procede de realisation d'un dispositif comportant une structure dotee d'un ou plusieurs micro-fils ou nano-fils a base d'un compose de si et de ge, par condensation germanium.
US8247911B2 (en) * 2007-01-15 2012-08-21 Nippon Steel Materials Co., Ltd. Wire bonding structure and method for forming same
US8149564B2 (en) * 2009-02-23 2012-04-03 Freescale Semiconductor, Inc. MEMS capacitive device and method of forming same

Also Published As

Publication number Publication date
TWI492322B (zh) 2015-07-11
CN102215994B (zh) 2016-02-10
DE102008054077B4 (de) 2021-04-01
US8561446B2 (en) 2013-10-22
KR20110074792A (ko) 2011-07-01
KR101498174B1 (ko) 2015-03-03
US20100107717A1 (en) 2010-05-06
WO2010062357A1 (en) 2010-06-03
DE102008054077A1 (de) 2010-05-12
TW201036087A (en) 2010-10-01

Similar Documents

Publication Publication Date Title
TWI770072B (zh) 具有用於扇出縮放的柱和通孔連接之高密度互連層的封裝基板
CN105845636B (zh) 在用于接合管芯的中介层中的具有不同尺寸的tsv
JP3986575B2 (ja) ３次元集積回路の製造方法
US8970047B2 (en) Method for creating a 3D stacked multichip module
Lee et al. 3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling
CN103681618B (zh) 具有通孔的功能性玻璃处理晶片
TWI222168B (en) High density raised stud microjoining system and methods of fabricating the same
EP1432032A3 (en) Semiconductor chip stack and method for manufacturing the same
TW201101429A (en) Improving the formation for TSV backside interconnects by modifying carrier wafers
TW200952139A (en) Wafer-level integrated circuit package with top and bottom side electrical connections
CN102956613B (zh) 用于控制半导体芯片封装件相互作用的接合垫配置
US10134945B1 (en) Wafer to wafer bonding techniques for III-V wafers and CMOS wafers
TW201330183A (zh) 用於無凸塊增層（ｂｂｕｌ）封裝的具有無凸塊晶粒封裝介面之封裝半導體晶粒
CN103219272B (zh) 形成半导体装置的方法
CN108122789A (zh) 制造晶片级半导体封装的方法
CN114551385B (zh) 含有微流道散热结构的三维堆叠封装结构及其封装方法
JP2007005401A (ja) 半導体装置およびその製造方法
Christiaens et al. Embedding and assembly of ultrathin chips in multilayer flex boards
CN102215994A (zh) 基于微电子制造技术制造键合线的方法及器件
JPS62219954A (ja) 三次元ｉｃの製造方法
CN102623444A (zh) 集成电路装置及其制备方法
US20210225811A1 (en) Systems and methods for flash stacking
CN104538314B (zh) 三层封装基板及封装芯片的制作方法及三层封装基板
CN107293484A (zh) 一种转接板制造方法
US8202744B2 (en) Wafer through silicon via forming method and equipment therefor

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160210

Termination date: 20191030

CF01 Termination of patent right due to non-payment of annual fee