CN102148794B - Moving window summing circuit - Google Patents

Abstract

The invention discloses a moving window summing circuit, which comprises a first-in first-out data cache, a negating module, two summators, a register, and a data initialization control module. The moving window summing circuit can implement summation according to the input data in the moving window, avoids the use of a plurality of shifting registers, has simple circuit structure, reduces turning times of circuit nodes, effectively reduces circuit resources and power consumption, and can be applied to the synchronization of an OFDM (frequency division multiplexing) receiving system to realize maximum likelihood estimate.

Description

The Moving Window summing circuit

Technical field

The present invention relates to Digital Signal Processing and digital communication technology field, especially relate to the cumulative summing circuit of a kind of movement.

Background technology

The Moving Window summing circuit is widely used in Digital Signal Processing and the digital communication.In the systems such as orthogonal frequency division multiplexi (OFDM), through complicated wireless channel, shift phenomenon can occur in carrier signal, and this can cause the systematic function degradation.Because receiving terminal can't be learnt the initialization time that receives signal and the phase rotating that channel causes, need to come estimate symbol skew and frequency shift (FS) with maximal possibility estimation (ML-Maximum Likelihood).Maximal possibility estimation need to be the summation that adds up in real time of the data flow of m to continuous length, can realize maximal possibility estimation with Moving Window as shown in Figure 1.Among the figure, k represents data number, at current time, need to be to Din[K] to Din[K+m-1] the data summation that adds up, at next time beat, data move forward one to Din[K+1], then need Din[k+1] to Din[K+m] and the data summation that adds up.

In the prior art, the basic implementation method of maximal possibility estimation can adopt as shown in Figure 2 chain of registers and Wallace tree adder shown in Figure 3.Use accumulator as shown in Figure 4 to substitute Wallace tree, can effectively simplify add circuit.But still have the register group of large displacement in this circuit, circuit area and power consumption still have the space of further optimization.Comparatively speaking, the hardware resource consumption of SRAM memory cell is less than register, simultaneously, when shift register moves forward one, all there is the possibility of upset in all registers, and based on the FIFO of SRAM, only need more finish the read and write of a data memory cell.For further reducing area, circuit node upset, reduction power consumption, the present invention proposes to realize that with SRAM FIFO substitutes the shift register chain in the original structure.

The invention provides a kind of Moving Window summing circuit, overcome the above defective of prior art, so that the shift register chain rood to be simplifying, thereby effectively reduce chip area and power consumption.

Summary of the invention

The object of the present invention is to provide a kind of Moving Window summing circuit, be used for OFDM receiving terminal synchro system.Moving Window summing circuit of the present invention comprises:

The first in first out data buffer, its input incoming external data list entries;

Get the negative norm piece, its input is connected with the output of described first in first out data buffer;

Adder, its input is connected with the described output of getting the negative norm piece;

Adder, an one input is connected with the output of described adder, another input incoming external data list entries;

Register, its input is connected with the output of described adder; Its output output data accumulation and, described data accumulation and be input to the input of described adder;

Wherein, when k≤m, described output data accumulation and be continuously input k external data cumulative with:

When k＞m, described output data accumulation and be the external data of current input with the cumulative of continuous m-1 external data of before input with:

Wherein, k is continuously the number of the external data of input, and m is the storage depth of described first in first out data buffer.

Wherein, the storage depth of first in first out data buffer (m) equals the number of Moving Window Continuous accumulation data.

Wherein, when the data sequence number (n) of described external data list entries was less than or equal to described storage depth (m), described first in first out data buffer was output as 0; When described data sequence number (n) during greater than storage depth (m), described first in first out data buffer is output as described data sequence number (n) and deducts described storage depth (m), n-m.

Moving Window summing circuit of the present invention adopts the first in first out data buffer (FIFO) based on SRAM to substitute original shift register link, thereby simplified the shift register link, required hardware resource obtains Efficient Compression, thereby effectively reduces chip area and power consumption.The present invention has not only simplified circuit, remove shift register chain, avoided the structural data register link of prior art, and when each new data input, only need to carry out read and write operation one time to SRAM, thereby can reduce the power consumption of chip area and chip.

Description of drawings

Fig. 1 is the Moving Window summation work schematic diagram of maximal possibility estimation;

Fig. 2 is the circuit structure diagram that is used for the shift register of maximal possibility estimation in the prior art;

Fig. 3 is the circuit structure diagram that is used for the Wallace tree adder of maximal possibility estimation in the prior art;

Fig. 4 is the circuit structure diagram that is used for the mobile summer of maximal possibility estimation in the prior art;

Fig. 5 is the circuit structure diagram of Moving Window summing circuit of the present invention;

Fig. 6 is for as the data sequence number n of external data list entries during less than storage depth m, the equivalent circuit structure figure of Moving Window summing circuit of the present invention.

Embodiment

Further elaborate the present invention below in conjunction with drawings and Examples.Following examples are not limitation of the present invention.Under the spirit and scope that do not deviate from inventive concept, variation and advantage that those skilled in the art can expect all are included in the present invention.

The present embodiment Moving Window summing circuit comprises first in first out data buffer 1, gets negative norm piece 2, adder 3, adder 4, register 5.

Wherein, external data list entries Din[n] input from the input of first in first out data buffer 1; The input of getting negative norm piece 2 is connected with the output of first in first out data buffer 1; An input of adder 3 is connected with the output of getting negative norm piece 2; An input of adder 4 is connected with the output of getting adder 3, another input incoming external data list entries Din[n]; The input of register 5 is connected with the output of adder 4, its output output data accumulation and Delta[n], simultaneously, data accumulation is connected another input that inputs to adder 3 and is connected with Delta[n.

First in first out data buffer 1 in the present embodiment is the first in first out data buffer (FIFO) based on SRAM.

The function of getting negative norm piece 2 in the present embodiment can be expressed as: if it is input as A, and output-A then; The function of adder can be expressed as: if its input is respectively A and B, then be output as A+B;

The storage depth m of first in first out data buffer 1 is the size of Moving Window, can determine according to system requirements, and data bit width does not limit, and equals the number of Continuous accumulation data.As outside list entries Din[n] in data sequence number n when being less than or equal to storage depth m, first in first out data buffer 1 is output as 0; As data sequence number n during greater than storage depth m, first in first out data buffer 1 is output as n-m.

As external data list entries Din[n] in data sequence number n during less than storage depth m, the equivalent circuit structure of Moving Window summing circuit of the present invention is as shown in Figure 6.As shown in the figure, the output Din[n-m of first in first out data buffer 1] be 00, therefore get negative 2, adder 3 and be equivalent to inoperative.

When data number k≤m, output data accumulation and the Delta[n of Moving Window summing circuit] be first data Din[0] to k data Din[k] and cumulative and, can be expressed as:

,

When k＞m, the output data sequence Delta[n of Moving Window summing circuit] be present input data Din[n] with continuous m data of before input cumulative with, can be expressed as,

Embodiment 1:

Fig. 5 is the circuit structure diagram of the Moving Window summing circuit of Direct Digital Frequency Synthesizers of the present invention.As shown in Figure 5, the present embodiment Moving Window summing circuit comprises, based on the first in first out data buffer 1 of SRAM, gets negative norm piece 2, adder 3, adder 4, register 5.Identical part in the present embodiment Moving Window summing circuit and the above-mentioned specific implementation method repeats no more.Wherein, the operation principle of getting negative norm piece 4 is: when the signal of input was R, it was output as-R.

With reference to figure 5, the input of first in first out data buffer (FIFO) 1 connects external data list entries Din[n], first in first out data buffer 1 is output as Din[n-m].When n＜m, the output Din[n-m of first in first out data buffer 1] be 0.Adder 3 be output as 0 with output data sequence Delta[n] sum, therefore be Delta[n], and with Delta[n] deliver to adder 4, with the output data Din[n of newly arrived first in first out data buffer 1] sum deliver to register 5 lock obtain Delta[n+1].

When n=m, the output data sequence Delta[m of register 5 output] for first data in the first in first out data buffer (FIFO) 1 to m data cumulative with, can be expressed as,

When n=m+1,

Register cumulative and be,

When n=m+2,

Register cumulative and be,

The like, when n=m+k,

The Moving Window summing circuit is output as,

Comparatively speaking, the hardware resource consumption of SRAM memory cell is less than register, simultaneously, when shift register moves forward one, all there is the possibility of upset in all registers, and based on the FIFO of SRAM, only need more finish the read and write of a data memory cell.For further reducing area, reduction power consumption, the present invention proposes to realize that with SRAM FIFO substitutes the shift register chain in the original structure.

When n increased by 1 at every turn, FIFO was operating as: read Din[n-m], then write Din[n in identical SRAM address].Therefore when each data arrives, only need a read operation and write operation are carried out in the same address of SRAM.

If the employing shift register, then each register holds value all need be upgraded, and its circuit upset number of times will be much larger than FIFO, so the present invention can effectively reduce power consumption.The present invention realizes a memory cell simultaneously, and much larger than SRAM, so the present invention has further reduced circuit area and power consumption based on the required circuit area of the memory cell of shift register and power consumption.

Being preferred embodiment of the present invention only in sum, is not to limit practical range of the present invention.Be that all equivalences of doing according to the content of the present patent application claim change and modification, all should belong to technology category of the present invention.

Claims (1)

1. a Moving Window summing circuit is characterized in that, comprising:

First in first out data buffer (1), its input incoming external data list entries Din (n);

Get negative norm piece (2), its input is connected with the output of described first in first out data buffer (1);

First adder (3), its input is connected with the described output of getting negative norm piece (2);

Second adder (4), an one input is connected with the output of described first adder (3), and another input is inputted described external data list entries Din (n);

Register (5), its input is connected with the output of described second adder (4); Its output output data accumulation and Delta (n), and described data accumulation and Delta (n) are imported into the input of described first adder (3);

Wherein, when k≤m, described output data accumulation and be continuously input k external data cumulative with:

$\mathrm{Delta}\left(n\right)=\underset{n=0}{\overset{k}{\mathrm{\Σ}}}\mathrm{Din}\left(n\right);$

When k＞m, described output data accumulation and be the external data of current input with the cumulative of continuous m-1 external data of before input with: $\mathrm{Delta}\left(n\right)=\underset{n=k-m+1}{\overset{k}{\mathrm{\Σ}}}\mathrm{Din}\left(n\right);$

Wherein, k is continuously the number of the external data of input, and m is the storage depth of described first in first out data buffer (1);

Wherein, the storage depth m of described first in first out data buffer (1) equals the number of Moving Window Continuous accumulation data; Wherein, when the data sequence number n of described external data list entries was less than or equal to described storage depth m, described first in first out data buffer (1) was output as 0; As described data sequence number n during greater than storage depth m, described Moving Window summing circuit is output as n-m+1 data to n data sum.

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