CN103853524A - Multiplier device and multiplying method - Google Patents
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- CN103853524A CN103853524A CN201210509001.XA CN201210509001A CN103853524A CN 103853524 A CN103853524 A CN 103853524A CN 201210509001 A CN201210509001 A CN 201210509001A CN 103853524 A CN103853524 A CN 103853524A
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Abstract
The invention provides a multiplier device which comprises a comparator, a first selector, a second selector and a multiplication unit. The comparator is used for comparing a high-k bit of a first multiplier with 0, and if the high-k bit is unequal to 0, the multiplication unit outputs data of low-(c-a+k-1) bit of the first multiplier and a second multiplier after multiplication; if the high-k bit is equal to 0, the multiplication unit outputs data of low-(a-k) bit of the first multiplier and the second multiplier after multiplication; the bit width of the first multiplier is a while the bit width of the second multiplier is b, and the maximum value of the bit width of multiplication of the first multiplier and the second multiplier is c; when c>a+b and 2b>/=c are met, an optional natural number k can be selected within an open interval of (a-b, a+b-c+1) to form an aXs multiplier, and s can be guaranteed to be smaller than b. Therefore, the multiplier device is more modified in structure and small in occupation. The invention further provides a method for implementing multiplication.
Description
Technical field
The present invention relates to hardware design field, especially relate to a kind of multiplier device and the method that realizes multiplying.
Background technology
Multiplier is a kind of conventional logical device, realizes the multiplying to two numbers by hardware circuit.Along with the high speed development of hardware circuit with to the improving constantly of various terminal arithmetic capability demands, to the requirement of multiplier also in continuous raising.According to different application scenarios, the speed of deviser to multiplier, area, power consumption etc. have proposed different requirements, but, under many circumstances, may need the performance of sacrificing in a certain respect to obtain more excellent performance on the other hand, for example need to reach higher arithmetic speed time, the multiplier that space required is larger could be realized.In the prior art, the multiplier as Wallace Tree, the multiple multipliers such as Booth multiplier have been derived according to different application demands.Wherein, Synopsys company utilizes its advantage of accumulating aspect logic synthesis (logic synthesis), in its Designware product, in net table level, general purpose multipliers is carried out to good optimization, in the performance aspect the Area and Speed two of multiplier, all obtained larger advantage.
In these prior aries, design and the target of optimizing are all general purpose multipliers.So-called " general ", the meaning is that two multipliers of multiplier are completely irrelevant, once determine the bit wide of two multipliers, the span of multiplier is exactly any possibility value within the scope of bit wide.For example, be respectively two multipliers of a and b for bit wide, the structure of the general purpose multipliers of employing is a × b.In fact, in real world applications, a lot of situations are the relations between two multipliers with negative correlation, and when a multiplier increases, another multiplier must reduce, when a multiplier reduces, another multiplier must increase, and the bit wide of the product of two multipliers is less than the bit wide sum of two multipliers.At present, even when multiplier meets negative correlativing relation, also still adopt general purpose multipliers.But general purpose multipliers often area occupied is larger, and complex structure.
Summary of the invention
The technical matters that the present invention solves is to provide a kind of method that can reduce the multiplier device of multiplier area, optimization multiplier architecture and realize multiplying in the time that multiplier meets negative correlativing relation.
For this reason, the technical scheme of technical solution problem of the present invention is:
The invention provides a kind of multiplier device, described device comprises: comparer, first selector, second selector and multiplication unit;
Described comparer, for by the high k position of the first multiplier and 0 relatively, if unequal, send first and controls signal to first selector and second selector, if equated, sends second and controls signal to first selector and second selector;
The input data of the first input end of described first selector are the first multiplier, the input data of the second input end of first selector are the second multiplier, described first selector selects first input end as input end after being used for receiving the first control signal, after receiving the second control signal, select the second input end as input end, the input data of the input end after selecting are exported to the 5th input end of described multiplication unit by output terminal; Wherein, the bit wide of described the first multiplier is a, and the bit wide of the second multiplier is b, and the maximal value of the bit wide of the product of the first multiplier and the second multiplier is c, and (a+b) is greater than c, and a is not less than b, and 2b is not less than c;
The input data of the 3rd input end of described second selector are the low m bit data of the second multiplier, the input data of the four-input terminal of second selector are the low n bit data of the first multiplier, described second selector selects the 3rd input end as input end after being used for receiving the first control signal, after receiving the second control signal, select four-input terminal as input end, the input data of the input end after selecting are exported to the 6th input end of described multiplication unit by output terminal; Wherein, m=c-a+k-1 and n=a-k, k is the arbitrary natural number that is greater than a-b and is less than a+b-c+1;
Described multiplication unit is for carrying out the data of the 5th input end and the 6th input end to export after multiplying, and the bit wide of described the 5th input end is a, and the bit wide of the 6th input end is number maximum in m and n.
Preferably, wherein,
When described c is odd number, k=(2a-c+1)/2, the bit wide of described the 6th input end is (c-1)/2.
Preferably, wherein,
When described c is even number, k=(2a-c)/2+1 or (2a-c)/2, the bit wide of described the 6th input end is c/2-1.
Preferably, described device also comprises: the first register, the second register and the 3rd register;
Described the first register is sent to the first multiplier the first input end of first selector, the low n bit data of the first multiplier is sent to the four-input terminal of second selector and the high k bit data of the first multiplier is sent to described comparer for after the first multiplier is deposited;
Described the second register is for being sent to the second input end of described first selector by described the second multiplier after the second multiplier is deposited and the low m bit data of the second multiplier being sent to the 3rd input end of second selector;
Described comparer is for relatively comprising the high k position and 0 of the first multiplier: described comparer compares for the high k position and 0 of the first multiplier to the first register transmission;
Described multiplication unit export and is comprised after multiplying for the data of the 5th input end and the 6th input end are carried out: described multiplication unit is used for the data of the 5th input end and the 6th input end to carry out exporting described the 3rd register to after multiplying;
Described the 3rd register is for depositing rear output to the data after described multiplication unit multiplying.
Preferably, described device also comprises: the 4th register, the 5th register, the 6th register and the 3rd register;
Described the 4th register is for being sent to the first input end of first selector by the first multiplier after the first multiplier is deposited and the low n bit data of the first multiplier being sent to the four-input terminal of second selector;
Described the 5th register is for being sent to the second input end of described first selector by described the second multiplier after the second multiplier is deposited and the low m bit data of the second multiplier being sent to the 3rd input end of second selector;
Described comparer transmission first controls signal to first selector and second selector comprises:
Described comparer sends first and controls signal to the 6th register;
Described comparer transmission second controls signal to first selector and second selector comprises:
Described comparer sends second and controls signal to the 6th register;
Described the 6th register is deposited and the signal after depositing is sent to respectively to first selector and second selector for the signal that comparer is sent;
Described multiplication unit export and is comprised after multiplying for the data of the 5th input end and the 6th input end are carried out: described multiplication unit is used for the data of the 5th input end and the 6th input end to carry out exporting described the 3rd register to after multiplying;
Described the 3rd register is for depositing rear output to the data after described multiplication unit multiplying.
Preferably, described device also comprises: the 7th register, the 8th register and the 3rd register;
Described first selector comprises for the 5th input end that exports the input data of the input end after selecting to described multiplication unit by output terminal: described first selector is for exporting the input data of the input end after selecting to the 7th register by output terminal;
The 5th input end of described multiplication unit deposited and the data after depositing is sent to by the 7th register for the data that first selector is sent;
Described second selector comprises for the 6th input end that exports the input data of the input end after selecting to described multiplication unit by output terminal: described second selector is for exporting the input data of the input end after selecting to the 8th register by output terminal;
The 6th input end of described multiplication unit deposited and the data after depositing is sent to by the 8th register for the data that second selector is sent;
Described multiplication unit export and is comprised after multiplying for the data of the 5th input end and the 6th input end are carried out: described multiplication unit is used for the data of the 5th input end and the 6th input end to carry out exporting described the 3rd register to after multiplying;
Described the 3rd register is for depositing rear output to the data after described multiplication unit multiplying.
The present invention also provides a kind of method that realizes multiplying, and the bit wide of the first multiplier is a, and the bit wide of the second multiplier is b, and the maximal value of the bit wide of the product of the first multiplier and the second multiplier is c, and a+b is greater than c, and a is not less than b, and 2b is not less than c, and described method comprises:
By the high k position of the first multiplier and 0 relatively, if unequal, by multiplication unit, multiplying is done in the low m position of described the second multiplier and described the first multiplier, if equated, by described multiplication unit, multiplying is done in the low n position of described the first multiplier and described the second multiplier;
Wherein, m=c-a+k-1 and n=a-k, k is the arbitrary natural number that is greater than a-b and is less than a+b-c+1.
Preferably, wherein,
When described c is odd number, k=(2a-c+1)/2.
Preferably, wherein,
When described c is even number, k=(2a-c)/2+1 or k=(2a-c)/2.
Preferably, the described high k position and 0 by the first multiplier relatively comprises: by comparer by the high k position of the first multiplier and 0 relatively.
As seen through the above technical solutions, the bit wide of the first multiplier is a, the bit wide of the second multiplier is b, a is not less than b, the bit wide maximal value of the product of the first multiplier and the second multiplier is c, be greater than (a+b) when meeting c, and when 2b is not less than c, can be in open interval (a-b, a+b-c+1) an optional natural number k, the multiplier of composition one a × s, wherein s is number maximum in a-k and c-a+k-1, because k is positioned at open interval (a-b, a+b-c+1), therefore can guarantee that s is less than b.Thereby the logical organization of the critical piece multiplication unit of multiplier device of the present invention has been reduced to a × s by a × b of general purpose multipliers, and the comparer and two MUX that increase are all that area is little, the basic device that logical path is short, therefore the present invention has realized the multiplier device that structure is optimized more, area occupied is less.
Accompanying drawing explanation
Fig. 1 is the specific embodiment structural representation of multiplier device provided by the invention;
Fig. 2 is another specific embodiment structural representation of multiplier device provided by the invention;
Fig. 3 is another specific embodiment structural representation of multiplier device provided by the invention;
Fig. 4 is another specific embodiment structural representation of multiplier device provided by the invention;
Fig. 5 is another specific embodiment structural representation of multiplier device provided by the invention;
Fig. 6 is the schematic flow sheet of realizing multiplying method provided by the invention.
Embodiment
In real world applications, a lot of situations are the relations between two multipliers with negative correlation, when a multiplier increases, another multiplier must reduce, when a multiplier reduces, another multiplier must increase, and the bit wide of the product of two multipliers is less than the bit wide sum of two multipliers, this relation often can make the structure of multiplier and area have some specific spaces of optimizing.When the present invention has negative correlativing relation based on two multipliers exactly, provide a kind of can implementation structure and the multiplier device that is optimized of area occupied.
Refer to Fig. 1, the invention provides a kind of multiplier device, described device comprises: comparer 101, first selector 102, second selector 103 and multiplication unit 104.
Described comparer 101 is for comparing the high k position of the first multiplier and 0, if unequal, sending first controls signal to first selector 102 and sends and first control signal to second selector 103, if equated, send second and control signal to first selector 102 and send second and control signal to second selector 103.
The input data of the first input end of described first selector 102 are the first multiplier, the input data of the second input end of first selector 102 are the second multiplier, described first selector selects first input end as input end after being used for receiving the first control signal, after receiving the second control signal, select the second input end as input end, the input data of the input end after selecting are exported to the 5th input end of described multiplication unit 104 by output terminal; Wherein, the bit wide of described the first multiplier is a, and the bit wide of the second multiplier is b, and the maximal value of the bit wide of the product of the first multiplier and the second multiplier is c, and all possible bit wide of this product is all not more than c, and a+b is greater than c, and a is not less than b, and 2b is not less than c.
The input data of the 3rd input end of described second selector 103 are the low m bit data of the second multiplier, the input data of the four-input terminal of second selector 103 are the low n bit data of the first multiplier, described second selector 103 selects the 3rd input end as input end after receiving the first control signal, after receiving the second control signal, select four-input terminal as input end, the input data of the input end after selecting are exported to the 6th input end of described multiplication unit 104 by output terminal; Wherein, m=c-a+k-1 and n=a-k, k is the arbitrary natural number that is greater than a-b and is less than a+b-c+1.
Described multiplication unit 104 is for carrying out the data of the 5th input end and the 6th input end to export after multiplying, and the bit wide of described the 5th input end is a, and the bit wide of the 6th input end is several s maximum in m and n.
As seen through the above technical solutions, in this embodiment, the bit wide of the first multiplier is a, the bit wide of the second multiplier is b, a is not less than b, the bit wide maximal value of the product of the first multiplier and the second multiplier is c, be greater than (a+b) when meeting c, and 2b is while being not less than c, can be at open interval (a-b, a+b-c+1) an optional natural number k in, form the multiplier of one a × s, wherein s is number maximum in a-k and c-a+k-1, because k is positioned at open interval (a-b, a+b-c+1), in, therefore can guarantee that s is less than b.Thereby the logical organization of the critical piece multiplication unit of the multiplier device in this embodiment has been reduced to a × s by a × b of general purpose multipliers, and the comparer and two MUX that increase are all that area is little, the basic device that logical path is short, therefore the present invention has realized the multiplier device that structure is optimized more, area occupied is less.
When introducing respectively c below and being even number and odd number, the structure optimum of multiplication unit 104, the area occupied value of hour k.
When described c is even number, structure optimum, the area occupied minimum of multiplication unit 104 when k=(2a-c)/2 or k=(2a-c)/2+1, and, the bit wide that k=(2a-c)/2 o'clock meets described the 6th input end is c/2-1, and the bit wide that meets equally described the 6th input end when k=(2a-c)/2+1 is c/2-1.Now the result of multiplication unit 104 is a × (c/2-1).
When described c is odd number, structure optimum, the area occupied minimum of k=(2a-c+1)/2 o'clock multiplication unit 104, and now meet: the bit wide of described the 6th input end is (c-1)/2.Now the structure of multiplication unit 104 is a × [(c-1)/2].
When two multipliers introducing multiplier below have negative correlativing relation, the structure of the multiplier adopting realizes the derivation of optimizing.Because input, the output of multiplier are integer, the number therefore relating in the present invention is integer.
Between two multiplier X and Y, have the relation of negative correlation, when a multiplier increases, another multiplier must reduce, and when a multiplier reduces, another multiplier must increase, and the bit wide of the product of two multipliers is less than the bit wide sum of two multipliers.
The bit wide of the first multiplier X is a, and the bit wide of the second multiplier Y is b, might as well suppose a >=b.The maximal value of the product of the first multiplier X and the second multiplier Y is c, and c need to meet c < a+b, otherwise needs to use general purpose multipliers.
If X[a1] represent the numerical value of the binary number of the a1 bit of number X; X[a1:a2] represent the numerical value of the binary number that number X forms from a1 bit to a2 bit.
First using the higher bit of the first multiplier X whether as 0 as alternative condition.As X[a-1]=0 time, multiplier becomes X[a-2:0] × Y[b-1:0], be designated as (a-1) position and take advantage of the multiplier 1 of b position; As X[a-1]=1 time, represent that a bit of X is significance bit, the significance bit of Y mostly is c-a position most, be Y[c-a-1:0] be significance bit, higher figure place is invalid, and now multiplier becomes X[a-1] × Y[c-a-1:0], be designated as a position and take advantage of the multiplier 2 of (c-a) position.Use the same method and continue to derive, can learn, if with the highest 2 bits of a as alternative condition, multiplier 1 is for taking advantage of b position in (a-2) position, multiplier 2 is for taking advantage of (c-a+1) in a position.
Conclusion is derived to and used the highest k bit of X as alternative condition, and multiplier 1 is for taking advantage of b position in (a-k) position, and multiplier 2 is for taking advantage of (c-a+k-1) position in a position.As shown in table 1.
Table 1
Bit wide A and the B of two factors of note multiplier 1 are respectively A=a-k, B=b.
Bit wide C and the D of two factors of note multiplier 2 are respectively C=a, D=c-a+k-1.
Two bit wides of final multiplier are designated as respectively M and N, might as well suppose M >=N, have
M＝MAX(MAX(A，B)，MAX(C，D))＝MAX(A，B，C，D)
N＝MAX(MIN(A，B)，MIN(C，D))
Wherein, MAX (a1, a2) is number maximum in a1 and a2, and MIN (a1, a2) is number minimum in a1 and a2.Because a in the bit wide of four factors is always maximum, therefore always there is M=a, need to obtain N, make N < b, thereby make multiplier that the present invention realizes than the more optimized structure of general purpose multipliers.
N=MAX (MIN (A, B), MIN (C, D))=MAX (MIN (A, B), D), in the time of A >=B, N=MAX (B, D), therefore N >=B, i.e. N >=b, because of M=a, now multiplier M × N does not realize and more optimizing than general purpose multipliers a × b again.
Therefore need to meet A < B, now N=MAX (A, D).More optimize than general purpose multipliers in order to guarantee to realize, N < b, therefore A < b and D < b, i.e. (a-b) < k and k < (a+b-c+1).In order to guarantee the existence of k, there is (a-b) < (a+b-c+1), i.e. (c-1)/2 < b, due to b, c is integer, therefore only need meet 2b >=c.
To sum up, when meeting c < a+b and 2b >=c, wherein a >=b, whether the high k position of choosing a equates with 0 can the more excellent multiplier of implementation structure as alternative condition, wherein, (a-b) < k and k < (a+b-c+1).
Introduce the derivation of the k value of the structure optimum that can make multiplier below.
Thereby make N=MAX (A, D) in order to make the more optimized structure of multiplier need meet A < B, can find out, A+D=c-1 is constant value, obtain minimum N value, only need make A and D approach as far as possible.In positive integer territory, when c is odd number, need meet A=D, when c is even number, need meet A=D+1 or A=D-1, solution k value is out integer.
Due to A=a-k, D=c-a+k-1, can obtain c and be odd number time, k=(2a-c+1)/2, A=D=(c-1)/2, N=(c-1)/2.
When c is even number, k=(2a-c)/2, A=c/2, D=c/2-1, N=c/2-1;
Or when c is even number, k=(2a-c)/2+1, A=c/2-1, D=c/2, N=c/2-1.
Thus, we obtain the multiplier a × N of structure optimum in the time meeting c < a+b and 2b >=c, wherein a >=b, when c is odd number, k=(2a-c+1)/2 and N=(c-1)/2, when c is even number, k=(2a-c)/2 or (2a-c)/2+1, N=c/2-1.
Fig. 2 is the specific embodiment of a kind of multiplier device provided by the invention.In this embodiment, the bit wide of the first multiplier X is a=12, the bit wide b=10 of the second multiplier Y, and the first multiplier and the second multiplier meet negative correlativing relation, and the bit wide maximal value of the product of the first multiplier and the second multiplier is c, c=14.Can find out, a, b and c meet following relation: a+b is greater than c, and a is not less than b and 2b is not less than c.Because c is even number, therefore get k=(2a-c)/2=5.This device specifically comprises:
Comparer 101, first selector 102, second selector 103 and multiplication unit 104.
Described comparer 101 is for comparing with 0 high 5 of the first multiplier, if unequal, sending first controls signal to first selector 102 and sends and first control signal to second selector 103, if equated, send second and control signal to first selector 102 and send second and control signal to second selector 103.
The input data of 0 end of described first selector 102 are the first multiplier X, the input data of 1 end of first selector 102 are the second multiplier Y, described first selector selects 0 end as input end after being used for receiving the first control signal, after receiving the second control signal, select 1 end as input end, the input data of the input end after selecting are exported to the 5th input end of described multiplication unit 104 by output terminal.
The input data of 0 end of described second selector 103 are the low m bit data of the second multiplier, wherein m=c-a+k-1=6, the input data of 1 end of second selector 103 are the low n bit data of the first multiplier, wherein n=a-k=7, described second selector 103 selects 0 end as input end after receiving the first control signal, after receiving the second control signal, select 1 end as input end, the input data of the input end after selecting are exported to the 6th input end of described multiplication unit 104 by output terminal.
Described multiplication unit 104 is for the data of the 5th input end and the 6th input end are carried out exporting after multiplying, and the bit wide of described the 5th input end is that the bit wide of 12, the six input ends is in 6 and 7 maximum several 7.
In actual applications, can select the second selector 103 of 7 can meet the requirement of this embodiment.
In conjunction with the consideration of logical path timing path, for the logical path that makes every one-level approaches as far as possible, be often optimized by register pair sequential in actual applications.Introduce below at diverse location and add register and realize the embodiment that sequential is optimized.
Because multiplication unit logical path is long, therefore conventionally before multiplying each other, two multipliers are deposited with register, after multiplying each other, product register is deposited.Be illustrated below by an embodiment.
Fig. 3 is another specific embodiment of multiplier device provided by the invention, and in this embodiment, the bit wide of the first multiplier X is a=12, the bit wide b=10 of the second multiplier Y, and the maximal value of the bit wide of the product of the first multiplier and the second multiplier is c, c=14.Can find out, a, b and c meet following relation: a+b is greater than c, and a is not less than b and 2b is not less than c.Because c is even number, therefore get k=(2a-c)/2=5.This embodiment comprises: comparer 101, first selector 102, second selector 103, multiplication unit 104, the first register 301, the second register 302 and the 3rd register 303.
Described the first register 301 is for after the first multiplier X is deposited being sent to the first multiplier X 0 end of first selector, the low n bit data of the first multiplier X being sent to 1 end of second selector and the high k bit data of the first multiplier X is sent to comparer 101, wherein n=c-a=7, k=(2a-c)/2=5.
Described the second register 302 is for being sent to 1 end of described first selector 102 by described the second multiplier Y after the second multiplier Y is deposited and the low m bit data of the second multiplier Y being sent to 0 end of second selector 103, wherein, and m=c-a+k-1=6.
Described comparer 101 for the first multiplier X that the first register 301 is sent high 5 with 0 relatively, if unequal, send respectively first and control signal to first selector 102 and second selector 103, if equate, send respectively second and control signal to first selector 102 and second selector 103.
Described first selector 102 selects 0 end as input end after receiving the first control signal, after receiving the second control signal, select 1 end as input end, the input data of the input end after selecting are exported to the 5th input end of described multiplication unit 104 by output terminal.
Described second selector 103 selects 0 end as input end after receiving the first control signal, after receiving the second control signal, select 1 end as input end, the input data of the input end after selecting are exported to the 6th input end of described multiplication unit 104 by output terminal.
Described multiplication unit 104 exports the 3rd register 303 for the data of the 5th input end and the 6th input end are carried out to after multiplying, and the bit wide of described the 5th input end is that the bit wide of 12, the six input ends is in 6 and 7 maximum several 7.
Described the 3rd register 303 is for depositing rear output to the data after described multiplication unit 104 multiplyings.
In the time that the sequential of multiplication unit is more nervous, also comparer can be put into the previous cycle and shift to an earlier date computing, and deposit with register, optimize the logical path take comparer as starting point.Be illustrated below by an embodiment.
Fig. 4 is another specific embodiment of multiplier device provided by the invention, and in this embodiment, the bit wide of the first multiplier X is a=12, the bit wide b=10 of the second multiplier Y, and the maximal value of the bit wide of the product of the first multiplier and the second multiplier is c, c=14.Can find out, a, b and c meet following relation: a+b is greater than c, and a is not less than b and 2b is not less than c.Because c is even number, therefore get k=(2a-c)/2=5.This embodiment comprises: comparer 101, first selector 102, second selector 103, multiplication unit 104, the 3rd register 303, the 4th register 401, the 5th register 402 and the 6th register 403.
Described the 4th register 401 is for being sent to 0 end of first selector by the first multiplier X after the first multiplier X is deposited and the low n bit data of the first multiplier X being sent to 1 end of second selector, wherein n=c-a=7.
Described the 5th register 402 is for being sent to 1 end of described first selector 102 by described the second multiplier Y after the second multiplier Y is deposited and the low m bit data of the second multiplier Y being sent to 0 end of second selector 103, wherein, and m=c-a+k-1=6.
Described comparer 101, for by high 5 and 0 comparison of the first multiplier X, if unequal, send first and controls signal to the 6th register 403, if equated, sends second and controls signal to the 6th register 403.
Described the 6th register 403 is deposited for the signal that comparer 101 is sent and the signal after depositing is sent to respectively to first selector 102 and second selector 103.
Described first selector 102 selects 0 end as input end after receiving the first control signal, after receiving the second control signal, select 1 end as input end, the input data of the input end after selecting are exported to the 5th input end of described multiplication unit 104 by output terminal.
Described second selector 103 selects 0 end as input end after receiving the first control signal, after receiving the second control signal, select 1 end as input end, the input data of the input end after selecting are exported to the 6th input end of described multiplication unit 104 by output terminal.
Described multiplication unit 104 exports the 3rd register 303 for the data of the 5th input end and the 6th input end are carried out to after multiplying, and the bit wide of described the 5th input end is that the bit wide of 12, the six input ends is in 6 and 7 maximum several 7.
Described the 3rd register 303 is for depositing rear output to the data after described multiplication unit 104 multiplyings.
While not being very nervous, before the first and second selector switchs can also being placed on to prime register, allow rear class carry out specially multiplier logic computing in front end logic, further optimize the sequential of multiplier device.Specifically refer to the embodiment shown in Fig. 5.
Fig. 5 is another specific embodiment of multiplier device provided by the invention, in this embodiment, the bit wide of the first multiplier X is a=12, the bit wide b=10 of the second multiplier Y, the first multiplier and the second multiplier meet negative correlativing relation, the maximal value of the bit wide of the product of the first multiplier and the second multiplier is c, c=14.Can find out, a, b and c meet following relation: a+b is greater than c, and a is not less than b and 2b is not less than c.Because c is even number, therefore get k=(2a-c)/2=5.This embodiment comprises: comparer 101, first selector 102, second selector 103, multiplication unit 104, the 7th register 501, the 8th register 502 and the 3rd register 303.
Described comparer 101 is for comparing with 0 high 5 of the first multiplier, if unequal, sending first controls signal to first selector 102 and sends and first control signal to second selector 103, if equated, send second and control signal to first selector 102 and send second and control signal to second selector 103.
The input data of 0 end of described first selector 102 are the first multiplier X, the input data of 1 end of first selector 102 are the second multiplier Y, described first selector selects 0 end as input end after being used for receiving the first control signal, after receiving the second control signal, select 1 end as input end, export the input data of the input end after selecting to the 7th register 501 by output terminal.
The 5th input end of described multiplication unit 104 is deposited and the data after depositing are sent to the 7th register 501 for the data that first selector 102 is sended over.
The input data of 0 end of described second selector 103 are the low m bit data of the second multiplier, wherein m=c-a+k-1=6, the input data of 1 end of second selector 103 are the low n bit data of the first multiplier, wherein n=a-k=7, described second selector 103 selects 0 end as input end after receiving the first control signal, after receiving the second control signal, select 1 end as input end, export the input data of the input end after selecting to the 8th register 502 by output terminal.
The 6th input end of described multiplication unit is deposited and the data after depositing are sent to the 8th register 502 for the data that second selector 103 is sended over.
Described multiplication unit 104 exports the 3rd register 303 for the data of the 5th input end and the 6th input end are carried out to after multiplying, and the bit wide of described the 5th input end is that the bit wide of 12, the six input ends is in 6 and 7 maximum several 7.
Described the 3rd register 303 is for depositing rear output to the data after described multiplication unit 104 multiplyings.
Refer to Fig. 6, the present invention also provides a kind of method that realizes multiplying, and the bit wide of the first multiplier is a, the bit wide of the second multiplier is b, and the maximal value of the bit wide of the product of the first multiplier and the second multiplier is c, and a+b is greater than c, a is not less than b, and 2b is not less than c, and described method comprises:
S601: by the high k position of the first multiplier and 0 relatively, if unequal, carry out S602, if equated, carry out S603.
S602: multiplying is done in the low m position of described the second multiplier and described the first multiplier by multiplication unit.Wherein, m=c-a+k-1, k is the arbitrary natural number that is greater than a-b and is less than a+b-c+ 1.
S603: multiplying is done in the low n position of described the first multiplier and described the second multiplier by multiplication unit.Wherein, n=a-k.
In S601, can be by comparer by the high k position of the first multiplier and 0 relatively.
When described c is even number, structure optimum, the area occupied minimum of multiplication unit when k=(2a-c)/2 or k=(2a-c)/2+1.
When described c is odd number, structure optimum, the area occupied minimum of k=(2a-c+1)/2 o'clock multiplication unit.
Can adopt the specific embodiment of any one multiplier device that Fig. 1 to Fig. 5 of the present invention provides to realize the method.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. a multiplier device, is characterized in that, described device comprises: comparer, first selector, second selector and multiplication unit;
Described comparer, for by the high k position of the first multiplier and 0 relatively, if unequal, send first and controls signal to first selector and second selector, if equated, sends second and controls signal to first selector and second selector;
The input data of the first input end of described first selector are the first multiplier, the input data of the second input end of first selector are the second multiplier, described first selector selects first input end as input end after being used for receiving the first control signal, after receiving the second control signal, select the second input end as input end, the input data of the input end after selecting are exported to the 5th input end of described multiplication unit by output terminal; Wherein, the bit wide of described the first multiplier is a, and the bit wide of the second multiplier is b, and the maximal value of the bit wide of the product of the first multiplier and the second multiplier is c, and (a+b) is greater than c, and a is not less than b, and 2b is not less than c;
The input data of the 3rd input end of described second selector are the low m bit data of the second multiplier, the input data of the four-input terminal of second selector are the low n bit data of the first multiplier, described second selector selects the 3rd input end as input end after being used for receiving the first control signal, after receiving the second control signal, select four-input terminal as input end, the input data of the input end after selecting are exported to the 6th input end of described multiplication unit by output terminal; Wherein, m=c-a+k-1 and n=a-k, k is the arbitrary natural number that is greater than a-b and is less than a+b-c+1;
Described multiplication unit is for carrying out the data of the 5th input end and the 6th input end to export after multiplying, and the bit wide of described the 5th input end is a, and the bit wide of the 6th input end is number maximum in m and n.
2. device according to claim 1, is characterized in that, wherein,
When described c is odd number, k=(2a-c+1)/2, the bit wide of described the 6th input end is (c-1)/2.
3. device according to claim 1, is characterized in that, wherein,
When described c is even number, k=(2a-c)/2+1 or (2a-c)/2, the bit wide of described the 6th input end is c/2-1.
4. according to the device described in claims 1 to 3 any one, it is characterized in that, described device also comprises: the first register, the second register and the 3rd register;
Described the first register is sent to the first multiplier the first input end of first selector, the low n bit data of the first multiplier is sent to the four-input terminal of second selector and the high k bit data of the first multiplier is sent to described comparer for after the first multiplier is deposited;
Described the second register is for being sent to the second input end of described first selector by described the second multiplier after the second multiplier is deposited and the low m bit data of the second multiplier being sent to the 3rd input end of second selector;
Described comparer is for relatively comprising the high k position and 0 of the first multiplier: described comparer compares for the high k position and 0 of the first multiplier to the first register transmission;
Described multiplication unit export and is comprised after multiplying for the data of the 5th input end and the 6th input end are carried out: described multiplication unit is used for the data of the 5th input end and the 6th input end to carry out exporting described the 3rd register to after multiplying;
Described the 3rd register is for depositing rear output to the data after described multiplication unit multiplying.
5. according to the device described in claims 1 to 3 any one, it is characterized in that, described device also comprises: the 4th register, the 5th register, the 6th register and the 3rd register;
Described the 4th register is for being sent to the first input end of first selector by the first multiplier after the first multiplier is deposited and the low n bit data of the first multiplier being sent to the four-input terminal of second selector;
Described the 5th register is for being sent to the second input end of described first selector by described the second multiplier after the second multiplier is deposited and the low m bit data of the second multiplier being sent to the 3rd input end of second selector;
Described comparer transmission first controls signal to first selector and second selector comprises:
Described comparer sends first and controls signal to the 6th register;
Described comparer transmission second controls signal to first selector and second selector comprises:
Described comparer sends second and controls signal to the 6th register;
Described the 6th register is deposited and the signal after depositing is sent to respectively to first selector and second selector for the signal that comparer is sent;
Described multiplication unit export and is comprised after multiplying for the data of the 5th input end and the 6th input end are carried out: described multiplication unit is used for the data of the 5th input end and the 6th input end to carry out exporting described the 3rd register to after multiplying;
Described the 3rd register is for depositing rear output to the data after described multiplication unit multiplying.
6. according to the device described in claims 1 to 3 any one, it is characterized in that, described device also comprises: the 7th register, the 8th register and the 3rd register;
Described first selector comprises for the 5th input end that exports the input data of the input end after selecting to described multiplication unit by output terminal: described first selector is for exporting the input data of the input end after selecting to the 7th register by output terminal;
The 5th input end of described multiplication unit deposited and the data after depositing is sent to by the 7th register for the data that first selector is sent;
Described second selector comprises for the 6th input end that exports the input data of the input end after selecting to described multiplication unit by output terminal: described second selector is for exporting the input data of the input end after selecting to the 8th register by output terminal;
The 6th input end of described multiplication unit deposited and the data after depositing is sent to by the 8th register for the data that second selector is sent;
Described multiplication unit export and is comprised after multiplying for the data of the 5th input end and the 6th input end are carried out: described multiplication unit is used for the data of the 5th input end and the 6th input end to carry out exporting described the 3rd register to after multiplying;
Described the 3rd register is for depositing rear output to the data after described multiplication unit multiplying.
7. a method that realizes multiplying, is characterized in that, the bit wide of the first multiplier is a, and the bit wide of the second multiplier is b, and the maximal value of the bit wide of the product of the first multiplier and the second multiplier is c, and a+b is greater than c, and a is not less than b, and 2b is not less than c, and described method comprises:
By the high k position of the first multiplier and 0 relatively, if unequal, by multiplication unit, multiplying is done in the low m position of described the second multiplier and described the first multiplier, if equated, by described multiplication unit, multiplying is done in the low n position of described the first multiplier and described the second multiplier;
Wherein, m=c-a+k-1 and n=a-k, k is the arbitrary natural number that is greater than a-b and is less than a+b-c+1.
8. method according to claim 7, is characterized in that, wherein,
When described c is odd number, k=(2a-c+1)/2.
9. method according to claim 7, is characterized in that, wherein,
When described c is even number, k=(2a-c)/2+1 or k=(2a-c)/2.
10. according to the method described in claim 7 to 9 any one, it is characterized in that, the described high k position and 0 by the first multiplier relatively comprises: by comparer by the high k position of the first multiplier and 0 relatively.
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| CN112286490A (en) * | 2020-11-11 | 2021-01-29 | 南京大学 | Hardware architecture and method for loop iteration multiply-add operation |
| WO2022247194A1 (en) * | 2021-05-22 | 2022-12-01 | 上海阵量智能科技有限公司 | Multiplier, data processing method, chip, computer device and storage medium |
| CN116820387A (en) * | 2023-08-28 | 2023-09-29 | 深圳比特微电子科技有限公司 | Multiplier, multiply-accumulate circuit and convolution operation unit |
| CN117555515A (en) * | 2024-01-11 | 2024-02-13 | 成都市晶蓉微电子有限公司 | Digital ASIC serial-parallel combined multiplier for balancing performance and area |
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| CN117555515B (en) * | 2024-01-11 | 2024-04-02 | 成都市晶蓉微电子有限公司 | Digital ASIC serial-parallel combined multiplier for balancing performance and area |
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