CN103457573A

CN103457573A - Gaussian filter with self-adaptive data rate

Info

Publication number: CN103457573A
Application number: CN201310394219XA
Authority: CN
Inventors: 张一�; 时琦; 时锴
Original assignee: SUZHOU PANCHIP MICROELECTRONICS CO Ltd
Current assignee: SUZHOU PANCHIP MICROELECTRONICS CO Ltd
Priority date: 2013-09-03
Filing date: 2013-09-03
Publication date: 2013-12-18
Anticipated expiration: 2033-09-03
Also published as: CN103457573B

Abstract

The invention discloses a Gaussian filter with the self-adaptive data rate. The Gaussian filter with the self-adaptive data rate is a digital Gaussian filter based on an application look-up table method and formed by an N-system counter, an M-N decoder, a Gaussian ROM and a parallel recombiner. Particularly, according to the Gaussian filter with the self-adaptive data rate, the input end of the N-system counter is connected with output of a self-adaptive frequency divider, input of the self-adaptive frequency divider is a bit rate of a clock signal and an input signal, frequency division is performed on the clock signal to make the clock signal be N times of the bit rate, output of the self-adaptive frequency divider and a base band signal are jointly connected into synchronization frequency, a phase and the starting and stopping time of a synchronizer, and output of the synchronizer and output of the N-system counter are jointly connected into a caching device; output of three continuous code elements of the caching device is connected into the Gaussian ROM, and meanwhile the middle code element output of the caching device is connected into the parallel recombiner. When the digital Gaussian filter is applied for performing modulation, the number of sampling points, the counter, the decoder and the like can be kept unchanged according to the input signals of different bit rates, and the digital Gaussian filter has universality and is small in amount of stored data.

Description

The adaptive Gaussian filter of a kind of data transfer rate

Technical field

The present invention relates to a kind of minimum shift keying modulation technique, relate in particular to a kind of gaussian filtering modulation technique of energy adaptive input signal bit rate, belong to field of signal modulation.

Background technology

The Gaussian-filtered minimum shift keying modulation technique is a kind of digital modulation mode that the basis from MSK modulation grows up, be characterized in first by a Gauss filter, carrying out premodulated filtering before data flow is delivered frequency modulator, saltus step energy while switching with the carrier wave that reduces two different frequencies, make channel spacings when identical message transmission rate can become tightr.Carried out the filtering of Gauss premodulated before modulation due to digital signal, more zero point, not only phase place was continuous in friendship for modulation signal, and level and smooth the filtration, so signal spectrum compactness, the bit error performance of GSMK modulation are good.

The structure of the sliding window convolution of Gaussian filter application discretization window commonly used on market.Y (n) is the output of Gaussian filter, and h (n) is the transfer function of Gaussian filter, and x (n) is the input of Gaussian filter, and the discretization window limits the N value, and y (n) is by x (n) and h (n) convolution (1).

When the discretization window becomes large, that corresponding accumulative frequency is just more, and amount of calculation is larger, takies resource more, and power consumption is higher.

But also have at present a kind of digital Gaussian filter structure that look-up table is made of applying, as shown in Figure 1, mainly formed by N system Counter 1,

M-N decoder

2,3 bit shift register 3, Gauss ROM4 and parallel composition device 5.Its operation principle is that the clock signal of input is through a N(integer) a M(integer of output after system Counter) binary data of position.3 bit shift register are to input binary signal a _m-1a _ma _m+1sealed in and go out to be shifted, the highest order that its clock is the N system Counter (after Fractional-N frequency, the transmission rate of this clock and baseband signal is consistent).Have four groups of N Z bit data in ROM, this Z bit data is sampled to four curves of Fig. 2 top with clock signal, and does that the Z+1 position quantizes to get, and this quantization digit is variable, but wants can guarantee with all sampled values of integer expressed intact.Three output signals of shift register have determined to select where organize data, and the gating signal that the M-N decoder produces is for determining which byte of selecting this group.The interposition a of three continuous input signals that as shown in Figure 2, four of below curves are corresponding _mbe 0, and the interposition a of top correspondence _mbe 1, therefore work as a _m7 outputs that are 1 o'clock ROM remain unchanged, and work as a _mbe 7 whole negates of output of 0 o'clock ROM.Finally add a _m8 outputs of Gaussian filter have just been determined as the highest sign bit.

Can find out that by above-mentioned Gaussian filter structure and operation principle thereof look-up table is for summation, avoid taking of complex calculations operation and ample resources, efficient, simple, low-power consumption, but be not suitable for the outer baseband signal of binary signal.

Consider the Gaussian filter of Fig. 1, still there are many shortcomings: the sampling number difference that (1) different bit rates is corresponding, because input clock signal immobilizes, Gaussian filter curve of output sampling number changes along with the change of input signal bit rate.(2) the input signal bit rate is unique, when the bit rate of input signal changes, N system Counter and M-N decoder are also no longer applicable, and these two elements of needs change of having to, therefore determined the N value, and the Gaussian filter structure of M-N value is only applicable to the input signal of well-determined bit rate.(3) code element is asynchronous, and because the transmission rate of input signal and the clock frequency of filter there are differences, input signal keeps synchronizeing with clock.(4) requirement of Gauss ROM memory space is larger, takies resource many, and due to the sampling number difference of different bit rates, the coefficient of storing in Gauss ROM will increase because of the difference of bit rate.

Summary of the invention

Consider the many-sided deficiency of above-mentioned existing Gaussian filter and demand, the present invention proposes the adaptive Gaussian filter of a kind of data transfer rate, solve the adaptive problem of input signal different bit rates.

The adaptive Gaussian filter of a kind of data transfer rate, based on the application look-up table and by the N system Counter, the M-N decoder, the digital Gaussian filter that Gauss ROM and parallel composition device form, it is characterized in that: the adaptive Gaussian filter of described data transfer rate connects the output of adaptive frequency divider at the input of N system Counter, the bit rate that is input as clock signal and input signal of described adaptive frequency divider, by the clock signal frequency division to the N of bit rate doubly, and the output of adaptive frequency divider and baseband signal access the synchronizer synchronizing frequency in the lump, phase place, beginning and ending time, the output of the output of described synchronizer and N system Counter is the access cache device in the lump, three continuous code element output access Gauss ROM of described buffer, intermediate symbol output accesses the parallel composition device simultaneously.

Further, doubly, and divide ratio and N are integer to the N that the divide ratio of described adaptive frequency divider is clock signal frequency and bit rate ratio.

The development of Gaussian filter of the present invention and application, compare to traditional Gaussian filter, and the input signal for different bit rates when being modulated can keep sampling number, counter, decoder etc. constant, has universality, and the storage data volume is little.。

The accompanying drawing explanation

Fig. 1 is the circuit diagram of the digital Gaussian filter of existing application look-up table.

Fig. 2 is the Gaussian filter response function curve chart that BT is 0.5 o'clock.

Fig. 3 is the circuit diagram of the adaptive Gaussian filter of data transfer rate of the present invention.

Embodiment

The present invention's numeral Gaussian filter circuit is the further improvement of doing on the look-up table Gaussian filter, has sampling number and fixes, and the input signal bit rate is variable, the advantages such as bit synchronization.

At first by reference to the accompanying drawings understand the present invention from circuit structure.As shown in Figure 3, this Gaussian filter is the traditional Gaussian filter based on as shown in Figure 1 generally, has certain similitude on circuit structure.As the basic composition of circuit, it also has N system Counter 1, M-N decoder 2, Gauss ROM4 and parallel composition device 5.But obviously distinguish: removed 3 original bit shift register, introduced adaptive frequency divider at N system Counter input, and added synchronizer and buffer two parts in circuit.

Specifically: the adaptive Gaussian filter of this data transfer rate connects the output of adaptive frequency divider 6 at the input of N system Counter 1, and the bit rate that is input as clock signal and input signal of this adaptive frequency divider 6, by the clock signal frequency division to the N of bit rate doubly, and the output of adaptive frequency divider 6 and baseband signal access synchronizer 7 synchronizing frequencies in the lump, phase place, beginning and ending time, the output of the output of this synchronizer 7 and N system Counter 1 is access cache device 8 in the lump, three continuous code element output access Gauss ROM4 of this buffer 8, intermediate symbol output accesses parallel composition device 5 simultaneously, the annexation of other circuit part and traditional Gaussian filter are consistent.The feature unit refinement of foregoing circuit innovation is as follows.

The bit rate that 6: two inputs of adaptive frequency divider are respectively clock signal, input signal.Sef-adapting filter carries out corresponding frequency division to clock signal, its corresponding divide ratio=input clock signal frequency/bit rate * N according to the bit rate of input.Here divide ratio must be integer.Output clock frequency after frequency division always is controlled as N times of current baseband signal bit rate.

Gauss ROM: due to four corresponding functions of curve of top and the bit rate of current baseband signal in Fig. 2, it doesn't matter, and in this Gaussian filter, the sampling number of output response curve keeps again constant, so only need four curves above storage map 2 in Gauss ROM, totally four groups of N 7 bit data, need not store again in addition more unnecessary data, saving resource because of the difference of bit rate, sampled point.

Synchronizer: make clock signal and baseband signal code element keep strictly synchronizeing, constantly align mainly for frequency, phase place, the start-stop of clock signal and code element.

Buffer: capture successively three code elements with the clock frequency after the N system Counter from input signal and deposit buffer in, often go out a code element in buffer, correspondingly just enter a code element, thereby form three new continuous code elements, then with these three continuous code elements, the data in Gauss ROM are selected.

Operation principle, according to the bit rate of baseband signal, the clock signal of input is carried out the self adaptation frequency division, N times (N is integer) by the clock signal frequency division of input to bit rate, obtain a new clock signal, input signal is done to synchronous processing simultaneously.This new clock signal is exported the M(integer after a N system Counter) bit binary data.Buffer memory is for storing the binary signal a of 3 current inputs _m-1a _ma _m+1, the highest order that its clock is the N system Counter (after Fractional-N frequency, the transmission rate of this clock and input signal is consistent).Have four groups of N Z bit data in Gauss ROM, this Z bit data is sampled to four curves of Fig. 2 top with new clock signal, and does that the Z+1 position quantizes to get, and this quantization digit is variable, but wants can guarantee with all sampled values of integer expressed intact.Three outputs of buffer have determined to select where organize data, and the gating signal that the M-N decoder produces is for determining which byte of selecting this group.The interposition a of three continuous input signals that as shown in Figure 2, four of below curves are corresponding _mbe 0 and four interposition a that curve is corresponding of top _mbe 1, therefore work as a _m7 outputs that are 1 o'clock Gauss ROM remain unchanged, and work as a _mbe 7 whole negates of output of 0 o'clock Gauss ROM.Finally add a _m8 outputs of Gaussian filter have just been determined as the highest sign bit.

Detailed description by above structure and principle is visible, and the present invention has following major advantage: (1) sampling number is fixed, and the sampling number of the Gaussian filter input curve that the input signal of different bit rates is corresponding keeps immobilizing.(2) N system Counter and M-N decoder are no longer because the change of bit rate changes, the N that remains the current input signal transmission rate because of the cause of adaptive frequency divider due to the input clock frequency of N system Counter doubly, the M bit binary data produced by the N system Counter accordingly is also constant, so just needn't change N system Counter and M-N decoder because the transfer rate of baseband signal is inconsistent again.(3) bit synchronization, the clock signal of the baseband signal of input after with the N system Counter on frequency, time reference may and inconsistent, removing this drawback after synchronous the processing.(4) Gaussian filter ROM space requirement is little, only needs four groups of N of storage, 7 bit data in Gauss ROM, needn't store respectively the coefficient of corresponding different bit rates in Gauss ROM because of the difference of baseband signal bit rate.

Below embodiment by reference to the accompanying drawings describes, and is intended to be convenient to understand innovation essence of the present invention, but not with this, limits the claim protection range of the multifarious execution mode of the present invention and requirement.In every case understand the present invention, and the equivalent structure carried out according to above-described embodiment changes or member is replaced, and can realize the design of identical purpose and effect, all should be considered as the infringement to present patent application protection content.

Claims

1. the adaptive Gaussian filter of data transfer rate, based on the application look-up table and by the N system Counter, the M-N decoder, the digital Gaussian filter that Gauss ROM and parallel composition device form, it is characterized in that: the adaptive Gaussian filter of described data transfer rate connects the output of adaptive frequency divider at the input of N system Counter, the bit rate that is input as clock signal and input signal of described adaptive frequency divider, by the clock signal frequency division to the N of bit rate doubly, and the output of adaptive frequency divider and baseband signal access the synchronizer synchronizing frequency in the lump, phase place, beginning and ending time, the output of the output of described synchronizer and N system Counter is the access cache device in the lump, three continuous code element output access Gauss ROM of described buffer, intermediate symbol output accesses the parallel composition device simultaneously.

2. the adaptive Gaussian filter of data transfer rate according to claim 1 is characterized in that: doubly, and divide ratio and N are integer to the N that the divide ratio of described adaptive frequency divider is clock signal frequency and bit rate ratio.