CN101996902B - 半导体器件的制造方法 - Google Patents
半导体器件的制造方法 Download PDFInfo
- Publication number
- CN101996902B CN101996902B CN201010229575.2A CN201010229575A CN101996902B CN 101996902 B CN101996902 B CN 101996902B CN 201010229575 A CN201010229575 A CN 201010229575A CN 101996902 B CN101996902 B CN 101996902B
- Authority
- CN
- China
- Prior art keywords
- circuit board
- pad
- semiconductor chip
- upside
- down mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3485—Applying solder paste, slurry or powder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75743—Suction holding means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
- H01L2224/81011—Chemical cleaning, e.g. etching, flux
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8102—Applying permanent coating to the bump connector in the bonding apparatus, e.g. in-situ coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81909—Post-treatment of the bump connector or bonding area
- H01L2224/8191—Cleaning, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
- H01L2224/83907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/0415—Small preforms other than balls, e.g. discs, cylinders or pillars
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
本发明提供了一种半导体器件的制造方法。其目的在于:提高倒装连接型半导体器件的可靠性。在倒装连接型BGA的组装过程中,在利用倒装连接对半导体芯片(1)进行焊接连接时,通过在布线基板(2)下表面(2b)一侧的焊盘(2j)的表面形成焊接预涂层(3),焊盘(2j)就与作为外部端子的焊球成为焊接连接,因此,能够提高焊盘(2j)与所述焊球的连接部的耐冲击性,从而可提高所述BGA的可靠性。
Description
技术领域
本发明涉及一种半导体器件的制造方法。特别涉及一种适用于提高半导体芯片倒装连接在布线基板上而形成的半导体器件的可靠性的有效的技术。
背景技术
例如,在专利文献1中公开了以下发明内容:在球阵列封装(BGA:BallGridArray)型半导体器件中,基板的电极垫由铜(Cu)形成,为在铜的表面施加了镀镍及镀金的结构及其组装的技术。
专利文献1:日本特开2002-26073号公报
发明内容
作为多引脚半导体封装体的一例,被称为BGA的半导体器件已为众所周知。为了使BGA中的信号的传送速度更加高速化,在多引脚高散热封装体中,以倒装连接的方式将半导体芯片搭载于布线基板(也称为BGA基板)上的封装技术已广为人知。
本案申请发明人对在倒装芯片BGA的组装过程中所用布线基板的端子(如焊盘等电极垫)的表面处理进行了研究,结果发现了以下问题。
被称为BGA基板等的布线基板的端子的表面处理,一般较多地采用化学镀镍-金处理。这是因为:通过采用化学镀,便能够解决采用电解电镀时所产生的问题。
也就是说,在对如倒装芯片BGA那样多引脚且设有高密度布线的布线基板采用电解电镀的情况下,必须设置镀层引线。由于镀层引线的影响,存在如下的问题:布线基板中的布线的设计自由度下降的问题以及传送路径信号质量恶化的问题。
但是,这些问题都是电解电镀所特有的问题,通过采用化学镀便无需镀层引线,因此大多情况下都采用化学镀。也就是说,由于采用化学镀便可以省去镀层引线,所以可提高布线设计的自由度以及消除因镀层引线造成的传送路径信号质量恶化的问题。
但是,另一方面,由于化学镀镍金的耐冲击性不好,结果又出现了如下问题:在布线基板的焊球搭载用焊盘与焊球的接合部的界面处很容易遭到破坏(断裂)。这是因为,在进行化学镀镍金时,一般都要混合上磷(P),但是在化学镀镍金过程中会在磷浓缩层产生微小的空洞而变脆,这是造成耐冲击性不良的主要原因。
此外,在上述专利文献1所述的BGA型半导体器件之组装过程中,对布线基板的焊盘(电极垫)表面也进行镀镍-金处理,所以就会产生焊盘和焊球的接合部的耐冲击性恶化的问题。
为解决上述课题而进行了本发明研究。目的在于:提供一种可提高倒装连接有半导体芯片的半导体器件的可靠性的技术。
本发明的另一个目的在于:提供一种可提高倒装连接有半导体芯片的半导体器件的质量稳定性的技术。
本发明的所述内容及所述内容以外的目的和新特征在本说明书的描述及附图说明中写明。
下面简要说明关于本专利申请书中所公开的发明中具有代表性的实施方式的概要。
也就是说,本发明涉及一种半导体器件的制造方法,所述半导体器件是一种半导体芯片面朝下焊接连接在具有上表面和下表面的布线基板的所述上表面一侧,并在所述布线基板的所述下表面一侧具有可与安装基板连接的焊球的半导体器件,其中,所述下表面位于所述上表面的相反一侧。所述半导体器件的制造方法包括:工序a,即进行所述焊接连接将所述半导体芯片面朝下连接到所述布线基板的所述上表面上的工序,且在对所述半导体芯片进行所述焊接连接时,在连接着所述焊球的所述布线基板的所述下表面一侧的焊盘表面上形成有焊接预涂层,其中,所述焊盘以铜为主要成分。
本发明涉及一种半导体器件的制造方法,所述半导体器件是一种半导体芯片面朝下焊接连接在具有上表面和下表面的布线基板的所述上表面一侧,并在所述布线基板的所述下表面一侧具有可与安装基板连接的焊球的半导体器件,其中,所述下表面位于所述上边面的相反一侧。所述半导体器件的制造方法包括以下工序:工序a,将焊膏或焊球布置在所述布线基板的所述上表面一侧的多个倒装用电极上,再对所述布线基板的所述下表面一侧的多个焊盘涂敷焊膏的工序;工序b,在所述工序a后,利用回流焊将所述上表面一侧的所述焊膏或焊球和所述下表面一侧的所述焊膏熔化,以在所述多个焊盘的表面上形成焊接预涂层的工序;工序c,将所述半导体芯片的主面和所述布线基板的所述上表面相向布置的工序;工序d,在所述工序c后,在所述焊接预涂层已形成在所述布线基板的所述下表面一侧的所述多个焊盘的表面上的状态下,用第一头部件对所述半导体芯片的背面进行加热后,再用第二头部件对所述布线基板的所述下表面进行加热,进行所述焊接连接以将所述半导体芯片连接到所述布线基板上。
下面简要说明关于本专利申请书中所公开的发明中根据具有代表性的实施方式所得到的效果。
即,在倒装连接型半导体器件的组装过程中,能够提高焊盘和焊球的连接部的耐冲击性,从而可提高半导体器件的可靠性。
通过在突起连接部采用植球法(ballmountingmethod),可提高半导体器件的质量稳定性。
附图说明
图1所示的是对本发明实施方式中的半导体器件构造之一例进行部分剖切后的透视立体图。
图2所示的是图1中的半导体器件的构造之一例的剖面图。
图3所示的是图1中的半导体器件的组装步骤之一例的制造流程图。
图4所示的是在图1所示的半导体器件的组装过程中所用的布线基板的构造之一例的剖面图。
图5所示的是将图4中的A部的构造之一例的部分放大后的剖面图。
图6所示的是在图1所示的半导体器件的组装过程中所用的布线基板的焊接预涂层的形成方法之一例的剖面图。
图7所示的是图6的焊接预涂层的形成方法之详细一例的部分剖面图。
图8所示的是在图1所示的半导体器件的组装过程中,倒装连接步骤之一例的部分剖面图。
图9所示的是在图1所示的半导体器件的组装过程中,植球步骤之一例的部分剖面图。
图10所示的是在图1所示的半导体器件组装过程中,所用的布线基板的第1变形例中的焊接预涂层形成方法的部分剖面图。
图11所示的是在图1所示的半导体器件的组装过程中,所用的布线基板的第2变形例中的焊接预涂层形成方法的部分剖面图。
图12所示的是在图1所示的半导体器件的组装过程中,第3变形例中的倒装连接步骤的部分剖面图。
符号说明
1半导体芯片
1a主面
1b背面
1c电极垫
1d焊料突起
1e助焊剂
2布线基板
2a上表面
2b下表面
2c倒装用电极
2d通孔布线
2e内部布线
2f堆焊层
2g阻焊膜(绝缘膜)
2h核心层
2i导通孔
2j焊盘
2k填孔树脂
2m焊料突起
2n焊膏
2p焊球
2q焊料突起
3焊接预涂层
3a焊膏
4散热片
5焊球(外部端子)
5a焊膏
6底部填充树脂
7加强环
7a环状胶带
7b粘接材
8焊料突起
9BGA(半导体器件)
10焊接印刷掩膜
10a开口部
11芯片侧头(第一头部件)
12基板侧头(第二头部件)
13散热树脂
具体实施方式
在以下实施方式中,除了需要特别说明的以外,对具有同一或同样的部分原则上不进行重复说明。
以下实施方式中,为了便于叙述,在必要时将几个部分或将实施方式分割来说明,除了需要特别说明的以外,这些都不是彼此独立且无关系的,而是与其它一部分或者全部的变形例、详细内容及补充说明等相互关联的。
另外,在以下实施方式中提及要素数等(包括个数、数值、量、范围等)时,除了特别说明及原理上已经明确限定了特定的数量等除外,所述的特定数并非指固定的数量,而是可大于等于该特定数或可小于等于该特定数。
而且,在以下实施方式中,除了特别说明及原理上已经明确了是必要时除外,所述的构成要素(包括要素步骤等)也并非是必须的要素。
在实施形态等的叙述上,对于构成要素方面的叙述等方面,除了特别说明及从前后文的叙述上来看已经明确了并非如此等除外,在“由A构成”、“由A形成”、“具有A”、“包括A”等的表述还指主要构成要素除了A以外还有其他的主要要素。同样地,对于构成要素等形状及位置关系的叙述方面,除了特别说明的及原理上已经明确了并非如此等除外,实际上还包括与该形状相近及类似的。同理,在数值及范围的叙述方面也一样。
以下根据附图详细说明本发明的实施方式。为了说明实施方式的所有图中,原则上对具有同一功能的构件采用同一符号,省略掉重复的说明。
(实施方式)
图1所示的是对本发明实施方式中的半导体器件构造之一例进行部分剖切后的立体图。图2所示的是图1的半导体器件的构造之一例的剖面图。图3所示的是图1的半导体器件的组装步骤之一例的制造流程图。图4所示的是在图1的半导体器件的组装过程中所用的布线基板的构造之一例的剖面图。图5所示的是将图4中的A部的构造之一例的部分放大后的剖面图。图6所示的是在图1所示的半导体器件的组装过程中所用的布线基板的焊接预涂层的形成方法之一例的剖面图。图7所示的是图6所示的焊接预涂层的形成方法之详细一例的部分剖面图。图8所示的是在图1所示的半导体器件的组装过程中,倒装连接步骤之一例的部分剖面图。图9所示的是在图1所示的半导体器件的组装过程中,植球步骤之一例的部分剖面图。图10所示的是在图1所示的半导体器件的组装过程中,所用的布线基板的第1变形例中的焊接预涂层的形成方法的部分剖面图。图11所示的是在图1所示的半导体器件的组装过程中,所用的布线基板的第2变形例中的焊接预涂层的形成方法的部分剖面图。图12所示的是在图1所示的半导体器件的组装过程中,第3变形例中的倒装连接步骤的部分剖面图。
图1及图2所示的本实施方式中的半导体器件,是一种半导体芯片1以倒装安装的方式被焊接连接在布线基板2的上表面2a上而形成的半导体封装体。在本实施方式中,以BGA9作为所述半导体器件之一例进行说明,所述的BGA9由多个外部端子即焊球5以栅状设在布线基板2的下表面2b上而形成。
以下对BGA9的详细结构进行说明。BGA9具有布线基板(也称为BGA基板)2、半导体芯片1以及作为外部端子的焊球5。其中,布线基板2具有:上表面2a、图5所示的形成在上表面2a上多个倒装用电极2c、位于上表面2a相反一侧的下表面2b以及形成在下表面2b上的多个焊盘2j;半导体芯片1具有主面1a及形成在主面1a上的多个电极垫1c,且被倒装连接在布线基板2的上表面2a上;多个外部端子即焊球5分别设置在布线基板2的下表面2b的多个焊盘2j上。
也就是说,BGA9的结构为半导体芯片1面朝下安装在布线基板2上的倒装连接结构。在所述半导体芯片1的主面1a和布线基板2的上表面2a相向的状态下将半导体芯片1搭载于布线基板2上。此时,半导体芯片1通过焊接连接与布线基板2电连接,通过多个焊料突起8倒装连接。
此外,在位于布线基板2和半导体芯片1之间的倒装连接部及其周围填充有底部填充树脂6,以固定和保护倒装连接部。
在布线基板2的上表面2a的周边部安装有加强环(StiffenerRing)7,所述加强环7呈包围半导体芯片1的状态。加强环7利用环状胶带7a粘接在布线基板2上。在加强环7的上部设有散热片4。散热片4通过半导体芯片1上的散热树脂13和环/散热片4之间的粘接材(例如胶带材)7b接合在加强环7及半导体芯片1的背面1b上。
由此,从半导体芯片1散发出的热便经过散热树脂13传递给散热片4,再从散热片4散发到外部,同时,还经焊料突起8并通过布线基板2从焊球5传给安装基板。而且,热还从散热片4经粘接材7b和加强环7传给布线基板2,再经过布线基板2从焊球5传给安装基板而散发出去。
如图5所示,布线基板2具有:基材层即核心层2h、形成在核心层2h上下的堆焊(build-up)层2f、形成在堆焊层2f表面一侧的面(布线基板2的上表面2a)上的多个倒装用电极2c以及形成在堆焊层2f背面一侧的面(布线基板2的下表面2b)上的多个焊盘2j。
此外,在各个倒装用电极2c的周围及多个焊盘2j的周围形成有作为绝缘膜的阻焊膜2g。
如图5所示,上表面2a一侧的倒装用电极2c和与所述倒装用电极2c相对应的下表面2b一侧的焊盘2j,经由形成在核心层2c上的通孔布线2d、形成在堆焊层2f上的导通孔2i及内部布线2e电连接。此外,填孔树脂2k填充在通孔布线2d内。
在这里,半导体芯片1例如由硅形成。底部填充树脂6例如为环氧系列树脂。加强环7和散热片4等由导热率较高的金属形成,而且,倒装连接的焊料突起8及作为外部端子的焊球5由无铅焊料等焊料材形成,例如由锡-银-铜系列无铅焊料形成。
布线基板2的倒装用电极2c、导通孔2i、内部布线2e以及通孔布线2d等,例如由纯铜或者铜里添加了少量(不超过1%)铝、硅(Si)等杂质的铜合金形成。
此外,在本实施方式的BGA9中,在布线基板2的上表面2a一侧的多个倒装用电极2c的各个表面、下表面2b一侧的多个焊盘2j的各个表面,都没形成有化学镍金镀层等化学镀层或电解镀层。也就是说,在未对多个倒装用电极2c中的各个表面进行化学镀镍金等化学镀和电解电镀等的状态下形成了多个焊料突起8。另一方面,在未对多个焊盘2j的各个表面进行化学镀镍金等化学镀和电解电镀等的状态下形成了多个焊球5。
接下来,按照图3所示的组装步骤对本实施方式中的BGA(半导体器件)9的制造方法进行说明。本实施方式中的BGA9的制造方法,是一种半导体芯片1面朝下焊接连接在具有上表面2a和下表面2b的布线基板2的上表面2a一侧,且具有能够在布线基板2的下表面2b一侧与安装基板连接的焊球5的BGA9的制造方法,其中,所述下表面2b位于所述上表面2a的相反一侧。
首先,进行图3所示的工序S1,即准备基板的工序。在这里是指备好图4及图5所示的布线基板(也称作BGA基板或者封装基板等)2。如图5所示,布线基板2是由焊料突起2m分别连接在其上表面2a上的多个倒装用电极2c中的每个倒装用电极2c上,且焊接预涂层3形成在下表面2b上的多个焊盘2j中的每个焊盘2j上。
下面参考图6及图7,说明上表面2a一侧的焊料突起2m及下表面2b一侧的焊接预涂层3的形成方法。
首先,进行图6所述的工序S11,即形成开口的工序。这里,在覆盖上表面2a一侧的多个倒装用电极2c中的各个倒装用电极2c的阻焊膜2g上形成开口,且在覆盖下表面2b一侧的多个焊盘2j中的各个焊盘2j的阻焊膜2g上形成开口。这些开口例如通过光蚀刻等处理形成。由此可使多个倒装用电极2c在布线基板2的上表面2a一侧露出,同时也可使多个焊盘2j在下表面2b一侧露出。
多个倒装用电极2c和焊盘2j例如由纯铜或者铜里添加了少量(不超过1%)铝、硅(Si)等杂质的铜合金形成。例如可以对多个倒装用电极2c和焊盘2j进行镀锡处理或者防锈处理。通过进行所述镀锡处理或者防锈处理,便可防止多个倒装用电极2c和焊盘2j氧化。
之后,进行图6所示的工序S12,即进行焊膏印刷/焊膏印刷。这里,通过所述焊膏印刷分别在多个倒装用电极2c上涂敷焊膏2n,且分别对多个焊盘2j上涂敷焊膏3a。此外,如图7焊膏印刷工序即工序S12所示,在往各个焊盘2j上印刷焊膏3a时,将焊接印刷掩膜10的开口部10a的位置与焊盘2j的位置对齐设置,并以将焊膏3a填埋在所述开口部10a的方式进行印刷。此时,为保证所形成的焊接预涂层3的高度不会过高,优选使用焊接印刷掩膜10的开口部10a的大小比焊盘2j小的阻止膜。
之后,进行如图6所示的工序S13和图7所示的工序S13,即进行回流焊/助焊剂清洗。此时,利用回流焊使各焊膏2n和各焊膏3a熔化而在各个倒装用电极2c上形成焊料突起2m,并且在各个焊盘2j上形成焊接预涂层3。在各个焊盘2j中,由于阻焊膜2g的开口宽大,所以当焊膏3a由于回流焊而熔化时,阻焊膜2g的形状就会变成带R形,这就成为焊接预涂层3。也就是说,由于纯铜或者铜里添加了少量(不超过1%)铝、硅(Si)等杂质的铜合金的焊盘2j和焊料的相互热扩散,而在焊盘2j上形成了锡铜系列或者锡银铜系列合金层。
此外,当在各个焊盘2j上形成焊接预涂层3时,使焊接预涂层3形成为在其厚度方向上比覆盖焊盘2j的周边部的阻焊膜2g下凹的状态。
由此,在以后的倒装连接工序中,当由第二头部件吸附支撑布线基板2时,便可防止焊接预涂层3与所述第二头部件接触,从而能够阻止第二头部件被沾污,并且能够防止其他焊接预涂层3的污物附着到焊接预涂层3的表面上。结果,可抑制BGA9的质量下降。
如上所述,在布线基板2的各个倒装用电极2c上形成了焊料突起2m,并且在各个焊盘2j上形成了焊接预涂层3。进行完回流焊后,进行助焊剂的清洗。
之后,进行图3中的工序S2,即进行倒装连接。也就是说,如图8所示,利用倒装连接将半导体芯片1搭载于布线基板2上。这里,将半导体芯片1面朝下焊接连接在布线基板2的上表面2a上。
首先,准备布线基板2,在所述布线基板2的下表面2b一侧的多个焊盘2j的表面上形成有焊接预涂层3,其中,所述多个焊盘2j由纯铜或者铜里添加了少量(不超过1%)铝、硅(Si)等杂质的铜合金形成。
另一方面,准备半导体芯片1,并利用第一头部件即芯片一侧的头11真空吸附所述半导体芯片1的背面1b,其中,所述半导体芯片1的主面1a上的多个电极垫1c(参照图2)连接有焊料突起1d。由于在芯片一侧的头11上设有加热部件(例如加热器等),所以如图8中的芯片加热即工序S21所示,半导体芯片1在被真空吸附的状态下由芯片一侧的头11加热。此时的加热温度例如在200-350℃左右。
此外,连接在半导体芯片1的主面1a上的多个电极垫1c(参照图2)上的多个焊料突起1d例如由锡-银-铜形成。而且,即使在倒装连接后的热处理工序(底部填充树脂6的固化工序、安装上散热片4后的烘烤工序等)中,也可通过对布线基板2的下表面2b的焊盘2j上形成焊接预涂层3,以抑制焊盘2j被氧化。
之后,进行图8中的工序S22,即对基板加热。此时,由第二头部件即基板侧头(也称为加热台或者加热块)12利用真空吸附来支撑布线基板2的下表面2b。由于在基板侧头12也设有加热部件(例如加热器等),所以布线基板2在被真空吸附的状态下由基板侧头12加热。此时的加热温度例如为150-250℃左右。
在所述状态下(使由基板侧头12真空吸附的布线基板2的上表面2a和由芯片侧头11真空吸附的半导体芯片1的主面1a相向的状态下)进行倒装连接即图8的工序S23。此外,在进行倒装连接时,在所述布线基板2的下表面2b一侧的多个焊盘2j的表面上形成焊接预涂层3,其中,所述多个焊盘2j由纯铜或者铜里添加了少量(不超过1%)铝、硅(Si)等杂质的铜合金形成。所述焊接预涂层3优选无铅焊料,例如锡-铜系列焊料。
例如与Sn63/Pb37系列的共晶焊料涂层相比,通过采用锡-铜系列无铅焊料作为形成在焊盘2j的表面上的焊接预涂层3的焊料,那么,即使在倒装连接等热处理工序中对焊接预涂层3施加了热历史,焊接预涂层3也难以熔化。
在利用回流焊熔化焊接预涂层3时,也需要事先使焊接预涂层3形成为高度不超出阻焊膜2g的高度。通过使焊接预涂层3的高度不超出阻焊膜2g的高度,可防止在焊接预涂层3熔化时,由此焊接预涂层3的焊料异物附着在基板侧头12上,从而能够防止基板侧头12被沾污。
焊接预涂层3形成在布线基板2的下表面2b的多个焊盘2j的表面上,由此,可防止在倒装连接时的热历史施加在焊盘2j上时,焊盘2j出现氧化而导致之后的焊球形成工序中焊球5无法附着。也就是说,通过在各个焊盘2j的表面上形成焊接预涂层3,便能够在之后的焊球形成工序中将焊球5连接在焊盘2j上。
在进行倒装连接时,通过芯片侧头11对半导体芯片1加热的加热温度(如为200-350℃)比通过基板侧头12对布线基板2加热的加热温度(如为150-250℃)高。
如上所述,通过使由基板侧头12进行的加热温度低于由芯片侧头11进行的加热温度,便能够减少带给布线基板2的热应力,从而能够减少对布线基板2造成的损伤。
在倒装连接时,在布线基板2被真空吸附在已加热的基板侧头12上的状态下,从半导体芯片1的背面1b一侧(上侧)推压由已被加热的芯片侧头11真空吸附的半导体芯片1进行倒装连接。由此,便可在各个平坦性一致的状态下,使设在半导体芯片1上的多个焊料突起1d和连接在布线基板2的倒装用电极2c的多个焊料突起2m进行倒装连接。
结果可提高倒装连接部的连接可靠性。
此外,在倒装连接时对布线基板2的加热过程中,也采用锡-铜系列无铅焊料作为焊接预涂层3的焊料,因此,即使倒装连接时的热历史被施加在焊接预涂层3上,焊接预涂层3也难以熔化。
因此就能够抑制自焊接预涂层3产生焊料异物,从而能够抑制焊料异物附着在基板侧头12上。结果,能够降低焊料异物吸附在随后搬送来的下一个布线基板2上,并且能够抑制布线基板2的平坦性恶化及基板侧头12的吸附性恶化。
最后,如图8中的工序S23所示,将半导体芯片1上的多个焊料突起1d和与其相对应的布线基板2的多个焊料突起2m分别连接至此,便完成了倒装连接。
完成倒装连接后,进行底部填充注入即图3中的工序S3。这里,将底部填充树脂6填充在布线基板2和半导体芯片1之间,并在半导体芯片1的侧面周围涂敷底部填充树脂6。由此可使底部填充树脂6设置在倒装连接部的周围,倒装连接部便得到保护。底部填充树脂6填充完之后,再进行底部填充树脂6的固化处理。
接下来,进行图3所示的工序S4即搭载散热片。首先,如图2所示,以包围半导体芯片1的方式,经由环状胶带7a将加强环7贴在布线基板2的上表面2a的周边部。之后,将散热树脂13涂敷在半导体芯片1的背面1b,再经由所述散热树脂13将散热片4安装在半导体芯片1上。在加强环7和散热片4之间装有粘接材(例如胶带材)7b。也就是说,散热片4经由散热树脂13与半导体芯片1接触,经由粘接材7b与加强环7接触。结果,半导体芯片1成为在布线基板2的上表面上被加强环7和散热片4覆盖的状态。
布置好散热片4后,对散热树脂13进行烘烤处理,以完成散热片4的安装。
此外,采用由锡-银-铜等制成的无铅焊料形成倒装连接部的焊料突起1d及焊料突起2m,采用锡-铜系列无铅焊料形成布线基板2的下表面2b的焊盘2j上的焊接预涂层3。
之后,进行植球即图3中的工序S5。也就是说,对布线基板2的下表面2b的焊盘2j上的焊接预涂层3施加热,将作为外部端子的多个焊球5与布线基板2的焊盘2j电连接。
首先,如图9中的工序S31所示,将焊膏5a印刷在布线基板2的各个焊盘2j的焊接预涂层3上。此时,也可以涂敷助溶剂来代替焊膏5a。之后,进行工序S32所示的植球。在这里,暂时将焊球5固定在焊膏5a上。之后,进行工序S33所示的回流焊/清洗处理。首先,通过回流焊对焊球5和焊膏5a加热并使其熔化。之后,进行清洗,并通过焊接连接将焊球5与多个焊盘2j电连接。
此外,用于焊球5的焊料中,如为含铅焊料的情况下,可为63Sn37Pb等;为无铅焊料的情况下,可为Sn3Ag0.5Cu等。
通过采用锡-银-铜等制成的无铅焊料形成倒装连接部的焊料突起1d及焊料突起2m,再采用锡-铜系列无铅焊料形成布线基板2的下表面2b的焊盘2j上的焊接预涂层3,则即使连接焊球5时的回流焊的热历史施加在焊料突起1d、焊料突起2m以及焊接预涂层3上,结果也与以上述一样,由于这些焊料的熔点很高,所以焊料突起1d、焊料突起2m以及焊接预涂层3将难以熔化。
如上所述,便完成了图1及图2所示的BGA9的组装。
在本实施方式的半导体器件的制造方法中,通过倒装连接将半导体芯片1进行焊接连接时,焊接预涂层3形成在布线基板2的下表面2b一侧的焊盘2j的表面上,由于焊盘2j和作为外部端子的焊球5的连接便成为焊接连接。因此,可提高焊盘2j和焊球5的连接部的耐冲击性。也就是说,由于在焊盘2j和焊球5的连接部例如是通过化学镍金镀层等方式而不含磷(P),所以将不产生富磷(P)层而导致出现微小空洞,从而能够提高焊盘2j和焊球5的连接部的耐冲击性。
由此便可提高BGA9的可靠性。
此外,在布线基板2的多个焊盘2j的表面上未形成有焊接预涂层3的情况下,由于焊盘2j的纯铜或者铜里添加了少量(不超过1%)铝、硅等杂质的铜合金露出来了,所以在植球工序之前还有各种施加热历史的工序,虽然也存在因焊盘2j的表面氧化而导致在植球工序中无法将焊球5连接在焊盘2j上的可能性。但是在本实施方式的BGA9的安装过程中,由于在焊盘2j的表面已形成有焊接预涂层3,所以能够抑制焊盘2j的表面氧化,从而能够在植球工序中将焊球5连接在焊盘2j上。
在进行倒装连接的布线基板2的倒装用电极2c和半导体芯片1的焊料突起1d的连接过程中,由于无需经由镍金镀层等就能进行焊接连接,所以可提高倒装用电极2c和焊料突起1d的连接部的耐冲击性。
由于不使用电解电镀,所以无需在布线基板2上设置镀层引线,因而能够提高布线设计的自由度,并且能够解决镀层引线引起的传送路径信号质量恶化的问题。
形成在布线基板2的焊盘2j的表面上的焊接预涂层3采用无铅焊料,由于无铅焊料的熔点高,所以即使在进行烘烤处理、固化处理等过程中在焊接预涂层3上施加了热历史,所述焊接预涂层3也难以熔化。而且,也不会在倒装连接时沾污基板侧头12(台),从而能够维持BGA9的品质。
而且,通过采用无铅焊料即锡-铜系列焊料作焊接预涂层3的焊料,那么,不管作为外部端子而被连接的焊球5是共晶(有铅)焊料还是无铅焊料,都可提高焊球5的连接强度。结果,可应用于共晶(有铅)焊料及无铅焊料,从而能够谋求布线基板2的共通化。由此,可降低布线基板2的成本,即可降低BGA9的成本。
此外,也可用化学镀镍-钯-金来代替焊接预涂层3的技术,但由于镀液的管理/膜厚-膜质的管理都很难,而且很难应用于共晶(含铅)/无铅二者的表面技术,所以,如本实施方式所述的易用于制造的焊接预涂技术是最为有效的。
接下来,对本实施方式的变形例进行说明。
图10所示的第1变形例的内容是:在进行了布线基板2的倒装连接的倒装用电极2c上形成焊料突起2m时,采用了搭载焊球2p而不是搭载焊料膏2n的植球法。
首先,进行图10所示的工序S41即形成开口。也就是说,在布线基板2的上表面2a一侧的阻焊膜2g上形成开口,及在下表面2b一侧的阻焊膜2g上形成开口,且使上表面2a一侧的多个倒装用电极2c和下表面2b一侧的多个焊盘2j露出。
之后,进行图10所示的工序S42,即进行焊膏印刷/搭载焊球。焊膏2n可为助焊剂。首先,在布线基板2的上表面2a一侧,通过印刷将焊膏2n涂敷在多个倒装用电极2c中的各个倒装用电极2c上,涂敷后,再将焊球2p搭载在(布置在)各个焊膏2n上。另一方面,在布线基板2的下表面2b一侧,通过印刷将焊膏3a涂敷在多个焊盘2j中的各个焊盘2j上。其中,焊膏3a可为助焊剂。
之后,进行如图10所示的工序S43,即进行回流焊/助焊剂清洗。这里,利用回流焊分别熔化焊膏2n和焊球2p、焊膏3a,并在各个倒装用电极2c上形成焊料突起2m,同时在各个焊盘2j的表面上形成焊接预涂层3。在各个焊盘2j中,由于阻焊膜2g的开口宽大,所以当焊膏3a由于回流焊而熔化时,阻焊膜2g的形状就会变为带R形,因而成为焊接预涂层3。也就是说,由于纯铜或者铜里添加了少量(不超过1%)铝、硅等杂质的铜合金的焊盘2j和焊料的相互热扩散作用,而在各焊盘2j上形成了锡铜系列合金层。
此外,当在各个焊盘2j上形成焊接预涂层3时,使焊接预涂层3形成为在其厚度方向上比覆盖焊盘2j的周边部的阻焊膜2g下凹的状态。
在回流焊之后,进行助焊剂清洗,完成助焊剂清洗后,再进行倒装连接。
如上所述,通过采用搭载焊球2p来形成突起(球)连接部(焊料突起2m)的植球法,便能够谋求窄间隙且多突起的连接质量的稳定,从而能够谋求倒装连接型BGA(半导体器件)9的质量稳定。
通过在倒装连接部采用植球法,便能够使球的高度均匀,从而能够提高半导体芯片1的平坦性。而且,解决了膏印刷时的下垂(sagging)的问题,从而使突起的高度形成得均匀且很高。
图11所示的第2变形例是采用与对所述布线基板2的植球法相同的植球法在半导体芯片1上形成突起。也就是说,即使是在芯片一侧采用植球法和而在基板一侧采用印刷法,也能够改善突起的平坦性,从而可提高接合的稳定性。
具体地说就是,首先,进行图11中的工序S51,即搭载焊球。这里,利用植球法在半导体芯片1的主面1a上设置多个焊料突起(焊球)1d。
接着,进行图11所示的工序S51,即进行回流焊。也就是说,以超过突起熔点的温度进行回流焊,以此来进行图11所示的工序S53即进行倒装连接。
此外,芯片一侧/基板一侧双方可以组合采用植球法。
之后,如图9中的工序S31所示,将焊膏5a印刷在布线基板2的各个焊盘2j的焊接预涂层3上。此外,可以涂敷助焊剂用以代替焊膏5a。进一步进行工序S32所示的植球。这里,暂时将焊球5固定在焊膏5a上。
之后,进行工序S33所示的回流焊/清洗。首先,利用回流焊对焊球5和焊膏5a加热并使其熔化。然后在进行清洗后,进行焊接连接将焊球5连接在多个焊盘2j上以完成电连接。
如上所述,在所述第2变形例中也可提高窄间隙且多突起的连接质量的稳定性,从而能够谋求倒装连接型BGA(半导体器件)9质量的稳定。还能够进一步使球的高度均匀一致,从而可提高半导体芯片1的平坦性。
接下来,图12所示的第3变形例为倒装连接方法的变形例。首先,进行图12所示的工序S61即暂时固定突起。这里,将助焊剂1e转印到设在半导体芯片1的主面1a的多个焊料突起1d上,转印后,再将连接有利用颤动等压印的焊料突起2q的状态下的布线基板2和半导体芯片1倒装连接在各个倒装用电极2c上。此时,首先,对连接在布线基板2的各个倒装用电极2c的多个焊料突起2q和半导体芯片1的多个焊料突起1d暂时进行固定。
之后,进行图12中的工序S62,即回流焊。也就是说,以超过突起熔点的温度进行回流焊,由此进行倒装连接即图12所示的工序S63。
此时,回流焊后有可能需要对布线基板2和半导体芯片1的间隙部分进行助焊剂清洗。但是如果使用无清洗型助焊剂或者利用等离子体处理等除去助焊剂时则可以略去清洗工序。
如上所述,可以采取不用头部件推压半导体芯片1和布线基板2的方法进行倒装连接。此时,通过在布线基板2的下表面2b一侧的焊盘2j形成焊接预涂层3便可防止焊盘2j被氧化。
以上按照实施方式具体地说明了本案发明人所作的发明,但是本发明并不受到所述实施方式的限定,在不超出其要旨的范围下能够进行种种变更,在此无需赘言。
例如,在上述实施方式中,以安装了加强环7的BGA9作为半导体器件为例进行了说明,但是也可以不设加强环7。但此时,散热片4通过散热树脂13仅与半导体芯片1的背面1b接合。
产业上的可利用性
本发明可广泛应用于倒装连接型电子器件。
Claims (2)
1.一种半导体器件的制造方法,包括如下工序:
工序a,准备布线基板,所述布线基板具有上表面、形成在所述上表面上的倒装芯片用电极、与所述上表面相反一侧的下表面、形成在所述下表面上的焊盘、形成在所述焊盘的表面上的焊接预涂层、以及覆盖所述焊盘的周缘部的绝缘膜,其中,所述焊盘由以铜为主要成份的材料形成,所述焊接预涂层是锡-铜类或者锡-银-铜类的无铅焊料,在所述焊接预涂层的厚度方向上,所述焊接预涂层比所述绝缘膜更下凹;
工序b,在所述工序a之后,将半导体芯片以所述半导体芯片的主面与所述布线基板的所述上表面相对的方式搭载在所述布线基板的上表面上,并将所述半导体芯片的突起和所述布线基板的所述倒装芯片用电极电连接起来,其中,所述半导体芯片具有所述主面、形成在所述主面上的电极垫、与所述电极垫连接的所述突起、以及与所述主面相反一侧的背面,在所述工序b中,通过使第一头部件与所述半导体芯片的背面接触来对所述半导体芯片进行加热,再通过使第二头部件与在所述布线基板的所述下表面设置的所述绝缘膜接触来对所述布线基板进行加热,其中,用所述第一头部件对所述半导体芯片加热时的加热温度比用所述第二头部件对所述布线基板加热时的加热温度高;以及
工序c,在所述工序b之后,将焊球布置在所述布线基板的所述焊盘上的所述焊接预涂层上,通过对所述焊球加热,在所述焊盘的所述表面上形成由所述焊球形成的外部端子。
2.如权利要求1所述的半导体器件的制造方法,其特征在于,
所述突起是由锡-银-铜形成的焊料突起。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009-187281 | 2009-08-12 | ||
JP2009187281A JP5649805B2 (ja) | 2009-08-12 | 2009-08-12 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101996902A CN101996902A (zh) | 2011-03-30 |
CN101996902B true CN101996902B (zh) | 2016-03-02 |
Family
ID=43588818
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201010229575.2A Active CN101996902B (zh) | 2009-08-12 | 2010-07-13 | 半导体器件的制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8580620B2 (zh) |
JP (1) | JP5649805B2 (zh) |
CN (1) | CN101996902B (zh) |
TW (1) | TWI549204B (zh) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8624323B2 (en) | 2011-05-31 | 2014-01-07 | International Business Machines Corporation | BEOL structures incorporating active devices and mechanical strength |
JP2013030712A (ja) * | 2011-07-29 | 2013-02-07 | Toshiba Corp | 半導体モジュールおよび半導体モジュールの製造方法 |
JP5800674B2 (ja) * | 2011-10-25 | 2015-10-28 | 日本特殊陶業株式会社 | 配線基板及びその製造方法 |
US9881898B2 (en) * | 2011-11-07 | 2018-01-30 | Taiwan Semiconductor Manufacturing Co.,Ltd. | System in package process flow |
JP5943065B2 (ja) * | 2012-03-05 | 2016-06-29 | 株式会社村田製作所 | 接合方法、電子装置の製造方法、および電子部品 |
JP6021441B2 (ja) | 2012-05-25 | 2016-11-09 | ラピスセミコンダクタ株式会社 | 半導体装置 |
CN109637995B (zh) * | 2013-09-03 | 2022-11-22 | 日月光半导体制造股份有限公司 | 基板结构、封装结构及其制造方法 |
US9282649B2 (en) * | 2013-10-08 | 2016-03-08 | Cisco Technology, Inc. | Stand-off block |
JP2015144188A (ja) * | 2014-01-31 | 2015-08-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
US9674940B2 (en) * | 2014-08-14 | 2017-06-06 | Samsung Electronics Co., Ltd. | Electronic device and semiconductor package with thermally conductive via |
CN104599978B (zh) * | 2014-12-31 | 2017-08-01 | 广州兴森快捷电路科技有限公司 | 一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法 |
JP6513950B2 (ja) * | 2015-01-07 | 2019-05-15 | ナミックス株式会社 | 無洗浄フラックス、および半導体パッケージの製造方法 |
US10515884B2 (en) | 2015-02-17 | 2019-12-24 | Advanced Semiconductor Engineering, Inc. | Substrate having a conductive structure within photo-sensitive resin |
CN105895539B (zh) * | 2016-06-08 | 2018-08-10 | 华进半导体封装先导技术研发中心有限公司 | 芯片倒装封装中间结构和倒装封装结构及倒装封装方法 |
CN106145026B (zh) * | 2016-06-30 | 2018-03-27 | 清华大学 | 用于mems的气密性封装结构和封装方法 |
JP2019052355A (ja) | 2017-09-15 | 2019-04-04 | 上村工業株式会社 | 電解Sn又はSn合金めっき液及びSn又はSn合金めっき物の製造方法 |
CN108091621A (zh) * | 2017-12-21 | 2018-05-29 | 乐健科技(珠海)有限公司 | 内嵌开关芯片的器件模组及其制作方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101286456A (zh) * | 2007-04-13 | 2008-10-15 | 新光电气工业株式会社 | 布线板制造方法、半导体器件制造方法以及布线板 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002026073A (ja) | 2000-07-07 | 2002-01-25 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP4105409B2 (ja) * | 2001-06-22 | 2008-06-25 | 株式会社ルネサステクノロジ | マルチチップモジュールの製造方法 |
JP2003258156A (ja) * | 2002-03-05 | 2003-09-12 | Ngk Spark Plug Co Ltd | 配線基板 |
JP2005159102A (ja) * | 2003-11-27 | 2005-06-16 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
JP2005191122A (ja) * | 2003-12-24 | 2005-07-14 | Kyocera Corp | 配線基板およびその製造方法 |
-
2009
- 2009-08-12 JP JP2009187281A patent/JP5649805B2/ja active Active
-
2010
- 2010-07-13 CN CN201010229575.2A patent/CN101996902B/zh active Active
- 2010-08-09 TW TW099126510A patent/TWI549204B/zh active
- 2010-08-10 US US12/853,817 patent/US8580620B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101286456A (zh) * | 2007-04-13 | 2008-10-15 | 新光电气工业株式会社 | 布线板制造方法、半导体器件制造方法以及布线板 |
Also Published As
Publication number | Publication date |
---|---|
JP5649805B2 (ja) | 2015-01-07 |
TW201106434A (en) | 2011-02-16 |
US8580620B2 (en) | 2013-11-12 |
US20110039375A1 (en) | 2011-02-17 |
JP2011040606A (ja) | 2011-02-24 |
TWI549204B (zh) | 2016-09-11 |
CN101996902A (zh) | 2011-03-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101996902B (zh) | 半导体器件的制造方法 | |
JP4660643B2 (ja) | プリ半田構造を形成するための半導体パッケージ基板及びプリ半田構造が形成された半導体パッケージ基板、並びにこれらの製法 | |
TWI534915B (zh) | 引線上凸塊之倒裝晶片互連 | |
CN102856220B (zh) | 半导体器件的制造方法 | |
US20130335931A1 (en) | Surface mount interconnection system for modular circuit board and method | |
KR20030067590A (ko) | 반도체소자와 그 제조방법 및 반도체장치와 그 제조방법 | |
JP2009105139A (ja) | 配線基板及びその製造方法と半導体装置 | |
KR20140073419A (ko) | 전자 부품, 전자 장치의 제조 방법 및 전자 장치 | |
US20110133332A1 (en) | Package substrate and method of fabricating the same | |
US20090041981A1 (en) | Packaging substrate having electrical connection structure and method for fabricating the same | |
JP2008288489A (ja) | チップ内蔵基板の製造方法 | |
JP2015115419A (ja) | 半導体パッケージ及びその製造方法 | |
JP4051570B2 (ja) | 半導体装置の製造方法 | |
US9572294B2 (en) | Circuit device and method for manufacturing same | |
JP3972209B2 (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
KR100808746B1 (ko) | 회로 장치의 제조 방법 | |
JP5560713B2 (ja) | 電子部品の実装方法等 | |
JP2870533B1 (ja) | 半導体装置およびその製造方法 | |
CN100483699C (zh) | 使用自傲互连材料的半导体器件封装 | |
TWI476844B (zh) | 導電凸塊的製造方法及具有導電凸塊的電路板結構 | |
US8115109B2 (en) | Circuit board and method for jointing circuit board | |
JP4561969B2 (ja) | 半導体装置 | |
JP4591715B2 (ja) | 半導体装置の製造方法 | |
JP2007266640A (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
JP2000151086A (ja) | プリント回路ユニット及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: Tokyo, Japan, Japan Applicant after: Renesas Electronics Corporation Address before: Kanagawa Applicant before: Renesas Electronics Corporation |
|
COR | Change of bibliographic data | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |