CN101969081A - Manufacturing method of photodiode device - Google Patents
Manufacturing method of photodiode device Download PDFInfo
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- CN101969081A CN101969081A CN2009101647003A CN200910164700A CN101969081A CN 101969081 A CN101969081 A CN 101969081A CN 2009101647003 A CN2009101647003 A CN 2009101647003A CN 200910164700 A CN200910164700 A CN 200910164700A CN 101969081 A CN101969081 A CN 101969081A
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- conductive layer
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Abstract
The invention provides a manufacturing method of a photodiode device. The method comprises the following steps of: providing a chip comprising a substrate and an epitaxial layer, wherein the substrate comprises a first surface and a second surface, and the epitaxial layer is formed on the first surface; forming a first conducting layer on the second surface of the substrate; forming a patterned conducting layer on the epitaxial layer; and etching the patterned conducting layer through the reactive ion etching process and by using argon gas and helium gas as etching agents.
Description
Technical field
The present invention relates to a kind of manufacture method of photodiode, particularly, about a kind of photodiode manufacture method that improves photoelectric conversion efficiency, promotes the technology reliability and reduce cost of manufacture.
Background technology
Along with the energy starved problem is serious day by day, the exploitation of energy savings and new forms of energy, for example wind-force, waterpower, solar energy etc. are paid attention to by people all gradually.Solar cell extensively is used on every product now owing to have long or the like advantage of pollution-free, easy to use, life-span.Solar cell is to utilize the photovoltaic special efficacy should be with the photodiode of transform light energy for electric energy, and it generally is to use to tie without the formed P-N of semi-conducting material and absorbs sunlight.
Figure 1A and 1B are for making the flow process profile of known photodiode.With reference to Figure 1A, the wafer 100 that comprises substrate 110 and epitaxial loayer 120 at first is provided, then form first conductive layer 130, for the usefulness of follow-up electrical connection in the bottom of wafer 100.Then, use first mask, form first patterned conductive layer 140 on epitaxial loayer 120 with technologies such as known metal deposition, photoetching and etchings, its thickness is about 5000
Then, with reference to Figure 1B, be mask with first patterned conductive layer 140, etching epitaxial loayer 120 is to form a plurality of epitaxial structures 125.Then, use second mask, form second patterned conductive layer 150 on first patterned conductive layer 140, to increase the thickness of monolithic conductive layer in the mode of electroplating.In general, the thickness of second patterned conductive layer 150 is about 5 μ m.At last, can on wafer 100, cover the conformal anti-reflecting layer of one deck, and use this anti-reflecting layer of the 3rd mask patterning, be total to the usefulness of follow-up electrical connection with second patterned conductive layer 150 that exposes part.
Fig. 2 A and 2B are the flow process profile of the another kind of method of the known photodiode of making.With reference to figure 2A, the wafer 200 that comprises substrate 210 and epitaxial loayer 220 at first is provided, then form first conductive layer 230, for the usefulness of follow-up electrical connection in the bottom of wafer 200.Then, use first mask, form patterning photoresist layer 240 on epitaxial loayer 220.
Then, be mask with patterning photoresist layer 240, etching epitaxial loayer 220 is to form a plurality of epitaxial structures 225, shown in Fig. 2 B.Then, use second mask, form patterned conductive layer 250 in the mode of evaporation, it covers a plurality of epitaxial structures 225 at least, and thickness is about 5 μ m.At last, can on wafer 200, cover the conformal anti-reflecting layer of one deck, and use this anti-reflecting layer of the 3rd mask patterning, be total to the usefulness of follow-up electrical connection with second patterned conductive layer 250 that exposes part.Note that being attached with thickness in patterned conductive layer 250 two bottom sides is about 1000
To about 3000
Width is the foot structure 260 of about 1 μ m to about 2 μ m.In general, technology such as known evaporation, etching will produce foot structure 260 inevitably at the metal wire edge.Because foot structure 260 has quite high resistance value, therefore the conductivity to metal wire there is no help.In addition, foot structure 260 will be blocked the incident ray of part, and then reduce photoelectric conversion efficiency, and may cause unnecessary characteristic electron and the technology reliability is had adverse influence.On the other hand, above-mentioned two kinds of known methods all need be used at least three road masks, and cost is higher relatively.
Therefore, be necessary to provide a kind of manufacture method that can further improve the photoelectric conversion efficiency of photodiode and can lower cost of manufacture.
Summary of the invention
In view of the existing problem of prior art, the invention provides a kind of photodiode manufacture method that improves photoelectric conversion efficiency, promotes technology reliability and reduction cost of manufacture.
An aspect of of the present present invention is to provide a kind of manufacture method of photoelectric diode device.Method of the present invention comprises: the wafer that comprises substrate and epitaxial loayer is provided, and wherein substrate comprises first surface and second surface, and epitaxial loayer is formed on the first surface; Form the second surface of first conductive layer in substrate; Form patterned conductive layer on epitaxial loayer; And with reactive ion etch process and use argon gas (Ar) and helium (He) as etchant and the etched pattern conductive layer, to remove the foot structure of patterned conductive layer two bottom sides.
In one embodiment, method of the present invention more is mask and etching epitaxial loayer with the patterned conductive layer after the step of etched pattern conductive layer, to expose the first surface of substrate.This embodiment can reduce the use of one mask compared to known processing step.
In another embodiment, method of the present invention before forming the step of patterned conductive layer, first patterning epitaxial loayer, to form a plurality of epitaxial structures, wherein patterned conductive layer covers a plurality of at least epitaxial structures.
Others of the present invention, part will be stated in follow-up explanation, and part can be learnt in illustrating easily, or can be learnt by enforcement of the present invention.Each side of the present invention can be utilized specifically noted element and combination in the accompanying Claim and understand and reach.Need to understand, general remark of stating earlier and following detailed description are all only made usefulness for example, are not in order to restriction the present invention.
Description of drawings
Figure 1A and 1B are for making the flow process profile of known photodiode;
Fig. 2 A and 2B are the flow process profile of the another kind of method of the known photodiode of making;
Fig. 3 A to Fig. 3 F is according to one embodiment of the invention, and illustrates the flow process profile of making photodiode; And
Fig. 4 A to Fig. 4 E is according to another embodiment of the present invention, and illustrates the flow process profile of making photodiode.
Description of reference numerals
100,200,300,400 wafers
110,210,310,410 substrates
120,220,320,420 epitaxial loayers
125,224,325,425 epitaxial structures
130,230,330,430 first conductive layers
140 first patterned conductive layers
150 second patterned conductive layers
240,440 patterning photoresist layers
250,340,450 patterned conductive layers
260,350,460 foot structure
312,412 first surfaces
314,414 second surfaces
360 anti-reflecting layers
470 patterning anti-reflecting layers
Embodiment
The present invention discloses a kind of manufacture method of photodiode, can improve the conversion efficiency of photodiode, and can reduce required number of masks, and then reduces cost of manufacture.In order to make narration of the present invention more detailed and complete, can be with reference to the diagram of following description and cooperation Fig. 3 A to Fig. 4 E.Device, element and method step described in right following examples in order to explanation the present invention, is not in order to limit the scope of the invention only.It should be noted that to clear to present the present invention, each element in the accompanying drawing is not the scale according to material object, and for avoiding fuzzy content of the present invention, below known secondary structure, associated materials and correlation processing technique thereof are also omitted in explanation.
In method of the present invention, be based upon each layer material on the substrate, can carry out via method well-known to those skilled in the art, sedimentation (deposition) for example, chemical vapour deposition technique (chemical vapor deposition), plasma enhanced chemical vapor deposition method (plasma enhanced chemical vapor deposition (PECVD)) or atomic layer deposition method (atomic layer deposition (ALD)) etc.
Fig. 3 A to Fig. 3 F is according to one embodiment of the invention, and illustrates the flow process profile of making photodiode.With reference to figure 3A, in one embodiment of this invention, provide wafer 300, it comprises substrate 310 and is formed at epitaxial loayer 320 on the first surface 312 of substrate 310.Substrate 310 can be any suitable semiconductor substrate, for example silicon substrate, germanium substrate, GaAs substrate etc.Epitaxial loayer 320 is for comprising the sandwich construction of at least one P-N knot, and its material can be the combination of the various semi-conducting materials that meet lattice match and energy level demand.Epitaxial loayer 320 can for example use Metalorganic chemical vapor deposition method technology such as (MOCVD) known film and form.In addition, epitaxial loayer 320 can also comprise a plurality of transparency conducting layers respectively between each P-N knot, in order to strengthen the collection of photoelectric current.
In general, a plurality of P-N knots that epitaxial loayer 320 is comprised are to use different semi-conducting materials made, and it has different energy gaps, in order to absorb the sunlight of different wave length.For instance, epitaxial loayer 320 can comprise GaInP layer, GaAs layer and GaInAs layer.In one embodiment, the P-N knot near substrate has more little energy gap more, in order to the long more sunlight of absorbing wavelength.Utilize the P-N knot of the different energy gaps of a plurality of tools, can improve the absorption region of optical wavelength, and then promote photoelectric conversion efficiency.
Then, form first conductive layer 330 at the second surface 314 of substrate 310, its material can be any suitable conducting metal, for example the alloy that titanium, silver, platinum, gold, tin, nickel, copper or its constituted etc. or other suitable electric conducting material.The method that forms first conductive layer 330 can for example be printing or various vacuum coating technology.
With reference to figure 3B, form patterned conductive layer 340 on epitaxial loayer 320.The material of patterned conductive layer 340 can be various suitable electric conducting materials, and as metal or metal alloy, its thickness is about 4 μ m to about 6 μ m, and is so not subject to the limits.Patterned conductive layer 340 can use known metal deposition process (as evaporation) and etch process and form.For instance, can be prior to forming patterning photoresist layer (figure does not show) on the epitaxial loayer 320, then the mode with evaporation forms second conductive layer (figure does not show), utilize again at last and peel off (lift-off) technology and remove patterning photoresist layer and be positioned at part second conductive layer on the patterning photoresist layer, and form the patterned conductive layer 340 shown in Fig. 3 B.Two side bottoms of patterned conductive layer 340 may form foot structure (footing) 350 because of the restriction of evaporation, photoetching or etch process.Generally speaking, the thickness of foot structure 350 is about 1000
To about 3000
Width is that about 1 μ m is to about 2 μ m.
Then,, for example use reactive ion etching dry etching methods such as (RIE) that wafer 300 is carried out comprehensive etching, to remove foot structure 350 with reference to figure 3C.In an embodiment of the present invention, removing foot structure 350 employed etching conditions is under the Dc bias of pressure, 100-500Watt and 300-600V at 10-30mTorr, uses the inert gas argon (Ar) of 15-25sccm flow and helium (He) that wafer 300 is carried out RIE technology.Because this etching step can be implemented entire wafer 300, therefore need not use any mask.Yet; in other embodiment of the present invention; also can use the material (for example nickel (Ni), tungsten (W), molybdenum (Mo), titanium (Ti) or tantalum (Ta) etc.) that inert gas is had very low rate of etch; form protective layer (figure does not show) earlier at patterned conductive layer 340 tops, carry out RIE technology again to remove foot structure 350.
With reference to figure 3D, be mask with patterned conductive layer 340, etching epitaxial loayer 320, to form a plurality of epitaxial structures 325, its etch depth can arrive the first surface 312 of substrate 310.The method of etching epitaxial loayer 320 can for example be known wet etching process, for instance, can use NH
4OH solution or by H
3PO
4, H
2O
2, H
2O mixes formed solution as etching solution according to special ratios.
With reference to figure 3E, be conformally formed anti-reflecting layer 360, to reduce the chance of incident light reflection, improve the efficient of opto-electronic conversion.The material of anti-reflecting layer 360 can be the various transparent materials that refractive index is lower than substrate 310, for example silicon dioxide (SiO
2), silicon nitride (Si
3N
4), titanium dioxide (TiO
2), aluminium oxide (Al
2O
3) or comprising formed individual layer of one or more above-mentioned materials or double-decker, its thickness can or be used required and adjusts according to the different of material refractive index.The formation method of anti-reflecting layer 360 can for example be known various deposition techniques, as evaporation, sputter, chemical vapour deposition (CVD) etc.
Then,, use known exposure photoetching technology, remove the anti-reflecting layer 360 of part, with the patterned conductive layer 340 under exposing, as the usefulness of follow-up electrical connection with reference to figure 3F.The step that part anti-reflecting layer 360 is removed can for example be that first painting photoresist layer (figure does not show) is on anti-reflecting layer 360, utilize design transfer technology such as exposure imaging the photoresist layer patternization to be defined the position of the patterned conductive layer 340 that institute's desire exposes again, again with this patterning photoresist layer as mask, etching anti-reflecting layer 360 and obtain structure shown in Fig. 3 F.
In the embodiment shown in Fig. 3 A to 3F, not only can remove has dysgenic foot structure to photoelectric conversion efficiency, and manufacture process only need use 2 road masks, therefore can reduce cost of manufacture effectively.
Fig. 4 A to Fig. 4 E is according to another embodiment of the present invention, and illustrates the flow process profile of making photodiode.With reference to figure 4A, in an embodiment of the present invention, provide wafer 400, it comprises substrate 410 and is formed at epitaxial loayer 420 on the first surface 412 of substrate 410.The structure of substrate 410 and epitaxial loayer 420 and material can be with reference to above stated specification.Then, form first conductive layer 430 with for example methods such as printing or vacuum coating technology at the second surface 414 of substrate 410.Then, form patterning photoresist layer 440 on epitaxial loayer 420, the etched position of desire to define.The formation method of patterning photoresist layer 440 can for example be that elder generation's comprehensive ground painting photoresist layer (figure does not show) is on epitaxial loayer 420, utilize design transfer technology patterning photoresist layers such as exposure imaging again, and form the patterning photoresist layer 440 shown in Fig. 4 A.
With reference to figure 4B, be mask with patterning photoresist layer 440, etching epitaxial loayer 420 is to form a plurality of epitaxial structures 425.The method of etching epitaxial loayer 420 can be with reference to aforementioned related description.Then, with reference to figure 4C, remove patterning photoresist layer 440 after, form patterned conductive layer 450 to cover a plurality of epitaxial structures 425 at least.The method that forms patterned conductive layer 450 can comprise: on substrate 410, wherein patterning photoresist layer does not cover epitaxial structure 425 to form patterning photoresist layer (figure does not show) with photoetching techniques such as rotary coating, exposure and developments; Form second conductive layer (figure does not show) with overlay pattern photoresist layer and all epitaxial structures 425 with known metal deposition process such as for example evaporations comprehensively; Remove patterning photoresist layer and be arranged in part second conductive layer on the patterning photoresist layer and obtain the patterned conductive layer 450 of Fig. 4 C to peel off (lift-off) technology again.In general, when forming patterned conductive layer 450, it is about 1000 that its two side bottom may can't form thickness because of the restriction of technology with avoiding
To about 3000
Width is the foot structure 460 of about 1 μ m to about 2 μ m.The material of patterned conductive layer 450 can be various suitable electric conducting materials, and thickness is about 4 μ m to about 6 μ m, and is so not subject to the limits.
Then,, for example use reactive ion etching dry etching methods such as (RIE) that wafer 400 is carried out comprehensive etching, to remove foot structure 450 with reference to figure 4D.In an embodiment of the present invention, remove foot structure 450 employed RIE technologies and be with inert gas argon (Ar) and helium (He) as etchant, under the Dc bias of flow 15-25sccm, pressure 10-30mTorr, 100-500Watt and 300-600V, wafer 400 is carried out.Because this etching step can be implemented entire wafer 400, therefore need not use any mask.Yet; in other embodiment of the present invention; also can use the material (for example nickel (Ni), tungsten (W), molybdenum (Mo), titanium (Ti) or tantalum (Ta) etc.) that inert gas is had very low rate of etch; form protective layer (figure does not show) earlier at patterned conductive layer 450 tops, carry out RIE technology again to remove foot structure 460.
With reference to figure 4E, form patterning anti-reflecting layer 470 on substrate 410, the patterned conductive layer 450 of its expose portion is with the usefulness as follow-up electrical connection.The formation method of pattern reflecting layer 470 can for example comprise following steps: form conformal anti-reflecting layer (figure does not show) with known depositing operation, its material and other details can be with reference to above stated specification comprehensively; Then, form patterning photoresist layer on conformal anti-reflecting layer, the position of the patterned conductive layer 450 that desire exposes to define; Be mask with this patterning photoresist layer more at last, the conformal anti-reflecting layer of etching, and obtain patterning anti-reflecting layer 470 shown in Fig. 4 E.
Compared to known photoelectric diode device manufacture method, method provided by the present invention can be under the quantity that does not increase the required mask of (even minimizing) technology, remove the foot structure of patterned conductive layer two bottom sides, avoid reducing photoelectric conversion efficiency, also can promote the technology reliability and reduce cost of manufacture simultaneously because produce the shading phenomenon.
The above is the preferred embodiments of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included within the scope of patent protection of the present invention.
Claims (12)
1. the manufacture method of a photoelectric diode device comprises:
Wafer is provided, comprises substrate and epitaxial loayer, wherein this substrate comprises first surface and second surface, and this epitaxial loayer is formed on this first surface;
Form first conductive layer this second surface in this substrate;
Form patterned conductive layer on this epitaxial loayer; And
With reactive ion etch process and use argon gas and helium as etchant and this patterned conductive layer of etching.
2. manufacture method as claimed in claim 1, wherein this reactive ion etch process is to implement under 10 to 30mTorr pressure limit.
3. manufacture method as claimed in claim 2, wherein this reactive ion etch process is to use flow at 15 to 25sccm argon gas and helium.
4. manufacture method as claimed in claim 3, wherein this reactive ion etch process is to be that 100 to 500 watts, Dc bias are to carry out under 300 to 600 volts at power.
5. manufacture method as claimed in claim 1 wherein after the step of this patterned conductive layer of etching, also comprises:
With this patterned conductive layer is mask, and this epitaxial loayer of etching is to expose this first surface of this substrate.
6. manufacture method as claimed in claim 1 wherein before the step that forms this patterned conductive layer, also comprises:
This epitaxial loayer of patterning, to form a plurality of epitaxial structures, wherein this patterned conductive layer covers these a plurality of epitaxial structures.
7. as claim 5 or 6 described manufacture methods, also comprise:
Be conformally formed anti-reflecting layer on this patterned conductive layer; And
This anti-reflecting layer of patterning is to expose this patterned conductive layer of part.
8. manufacture method as claimed in claim 1, wherein this epitaxial loayer comprises a plurality of P-N knot and a plurality of transparency conducting layers between these a plurality of P-N knots respectively.
9. manufacture method as claimed in claim 8, wherein this a plurality of P-N knot has different energy levels respectively, and has more little energy level near the P-N knot of this substrate more.
10. manufacture method as claimed in claim 9, wherein these a plurality of P-N knots comprise GaInP layer, GaAs layer and GaInAs layer.
11. manufacture method as claimed in claim 1, wherein this substrate is selected from silicon substrate, germanium substrate or GaAs substrate, and wherein this anti-reflecting layer material comprises silicon dioxide, silicon nitride, titanium dioxide or aluminium oxide.
12. manufacture method as claimed in claim 1, wherein the step of this this patterned conductive layer of formation comprises:
Form patterning photoresist layer on this epitaxial loayer;
Deposit second conductive layer on this patterning photoresist layer; And
Use stripping technology to remove this patterning photoresist layer and be positioned at this second conductive layer of part on this patterning photoresist layer, to form this patterned conductive layer, wherein the thickness of this patterned conductive layer is that about 4 μ m are to about 6 μ m.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101647003A CN101969081A (en) | 2009-07-27 | 2009-07-27 | Manufacturing method of photodiode device |
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|---|---|---|---|
| CN2009101647003A CN101969081A (en) | 2009-07-27 | 2009-07-27 | Manufacturing method of photodiode device |
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| CN101969081A true CN101969081A (en) | 2011-02-09 |
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| CN2009101647003A Pending CN101969081A (en) | 2009-07-27 | 2009-07-27 | Manufacturing method of photodiode device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110880540A (en) * | 2018-09-06 | 2020-03-13 | 鼎元光电科技股份有限公司 | Photodiode and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060138474A1 (en) * | 2004-12-29 | 2006-06-29 | Jae-Seon Yu | Recess gate and method for fabricating semiconductor device with the same |
| CN1914744A (en) * | 2004-01-29 | 2007-02-14 | Rwe太空太阳能有限责任公司 | Semiconductor structure comprising active zones |
| CN101359607A (en) * | 2007-08-01 | 2009-02-04 | 福葆电子股份有限公司 | Method for forming metal film on surface of elastic lug |
-
2009
- 2009-07-27 CN CN2009101647003A patent/CN101969081A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1914744A (en) * | 2004-01-29 | 2007-02-14 | Rwe太空太阳能有限责任公司 | Semiconductor structure comprising active zones |
| US20060138474A1 (en) * | 2004-12-29 | 2006-06-29 | Jae-Seon Yu | Recess gate and method for fabricating semiconductor device with the same |
| CN101359607A (en) * | 2007-08-01 | 2009-02-04 | 福葆电子股份有限公司 | Method for forming metal film on surface of elastic lug |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110880540A (en) * | 2018-09-06 | 2020-03-13 | 鼎元光电科技股份有限公司 | Photodiode and method for manufacturing the same |
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Application publication date: 20110209 |