CN101842887B - 接触电子器件的方法、用其制造的装置和相应的设备 - Google Patents

接触电子器件的方法、用其制造的装置和相应的设备 Download PDF

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Publication number
CN101842887B
CN101842887B CN2008801137606A CN200880113760A CN101842887B CN 101842887 B CN101842887 B CN 101842887B CN 2008801137606 A CN2008801137606 A CN 2008801137606A CN 200880113760 A CN200880113760 A CN 200880113760A CN 101842887 B CN101842887 B CN 101842887B
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joint face
downside
pieces
substrate
carrier film
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CN101842887A (zh
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A·卡尔滕巴克
R·韦因克
M·卡斯帕
G·希梅塔
K·韦德纳
J·扎普弗
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Siemens AG
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Siemens AG
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Abstract

本发明涉及一种接触至少一个未装壳体的电子器件的方法，所述电子器件具有至少一个分别布置在上侧和/或下侧的用于固定和/或电接触的连接面。将提供一种对至少一个未装壳体的电子器件进行的低成本的电接触，所述电子器件具有用于在上侧和/或下侧进行固定和/或电接触的连接面。器件利用其下侧在连接面的范围内分别与衬底、尤其是DCB陶瓷衬底上的相对的连接面相固定和/或电接触；并且在连接面的范围之外并且超出下侧，在衬底朝向器件的侧产生电隔离的载体膜；上侧(3)的接触面(7)分别与形成预成形的三维结构的、延伸超出上侧的面的导电导体件相固定和/或电接触，其中在载体膜与导体件的三维结构之间产生有电隔离的块件。

Description

接触电子器件的方法、用其制造的装置和相应的设备
技术领域
本发明涉及一种接触至少一个未装壳体的电子器件的方法，其中所述电子器件具有至少一个分别布置在上侧和/或下侧的用于固定和/或电接触的连接面，以及涉及一种根据该方法制造的装置和相应的设备。
背景技术
尤其是在功率电子装置中电接触一个或多个未装壳体的芯片和/或无源器件时，***坦地焊接到DCB陶瓷衬底板上。所述接触可以根据WO 03030247借助于粗线接合或者可选地借助于所谓的平面接触来实施。所述公开的内容明确地属于本申请的公开。与粗线接合不同，平面接触通过如下方式进行：将绝缘膜层压到所述电子器件上；尤其是借助于激光烧蚀打开接触孔；以及借助于电镀沉积的金属层产生平面连接。
发明内容
本发明的任务是提供一种对至少一个未装壳体的电子器件进行的低成本的电接触，该电子器件尤其是大于1000伏的高压范围的、尤其是功率器件或者半导体功率器件，其具有在上侧和/或下侧进行固定和/或电接触的连接面。另外，还将提供所述接触的高集成度、低电感特性、高电流承载能力、有效的冷却、和/或在电和热循环载荷方面的高度可靠性。
电循环载荷是指以一定的负荷变化次数交替地经受低电功率和高电功率。热循环载荷是指以一定的温度变化次数(例如100至1000次循环)交替地经受低温(例如-40℃)和高温(例如+125℃)。
导体件是具有高电导率和大的电流承载能力的电导体，其中所述导体可以容易地、例如借助于冲压、和/或弯曲以及塑性预成形来机械加工。这样的导体件同样可以被称为冲弯件(Stanzbiegteil)。例如，导体件可以是引线框架、尤其是铜引线框架。
连接弯形体是所述导体件的用于将所述导体件电接触和/或固定在衬底的连接面上的弯曲段。
***坦地焊接。“DCB”是指“直接铜接合”。在产生DCB陶瓷时，铜板被轧制在陶瓷的上侧和下侧，并且在大约1080℃下与陶瓷形状配合地相连接。接着，两个铜面之中至少之一以湿化学方式被结构化。这样的陶瓷的著名制造商之一叫做“Curamik”。
该任务通过以下所述的方法来解决。也即，根据本发明的接触至少一个未装壳体的电子器件的方法，所述电子器件具有至少一个分别布置在上侧和/或下侧的用于固定和/或电接触的连接面。将所述器件利用其下侧固定到超出下侧的面的电隔离载体膜上；将上侧的连接面分别与形成预成形的三维结构的、延伸超出上侧的面的导电导体件相固定和/或电接触；在载体膜与导体件的三维结构之间产生电隔离的块件；在连接面的范围内从下侧去除载体膜；将下侧的连接面分别与衬底上的同该连接面相对的连接面相固定和/或电接触。
借助于所提出的解决方案，可以低成本地实施未装壳体的器件在衬底上、尤其是在DCB陶瓷上的涂敷和接线，其中作为绝缘材料将易于制造的经过注塑的塑料用作绝缘材料。借助于所提出的解决方案，可以提供器件的低电感的接触。
根据本发明的借助于所述的方法制造的装置，包括至少一个未装壳体的电子器件，其具有至少一个分别布置在上侧和/或下侧的用于固定和/或电接触的连接面，其中所述器件利用其下侧在连接面的范围内分别与衬底上的相对的连接面相固定和/或电接触；在连接面的范围之外并超出下侧，在衬底朝向器件的侧产生电隔离的载体膜；上侧的连接面分别与形成预成形的三维结构的、延伸超出上侧的面的导电导体件相固定和/或电接触；其中在载体膜与导体件的三维结构之间产生有电隔离的块件。本发明还提供一种相应的设备，包括至少一个未装壳体的电子器件，其具有至少一个分别布置在上侧和/或下侧的用于固定和/或电接触的连接面，其中所述器件利用其下侧固定在延伸超出下侧的面的电隔离载体膜上；上侧的连接面分别与形成预成形的三维结构的、延伸超出上侧的面的导电导体件相固定和/或电接触；其中在载体膜与导体件的三维结构之间产生有电隔离的块件。根据一个有利的扩展方案，所述导体件形成至少一个延伸到膜平面上的连接弯形体。同样，在连接弯形体范围内实施对载体膜的去除。所述连接弯形体与衬底板上的相对的连接面相固定和/或电接触。通过这种方式，可以通过由电学上高电导率的材料构成的粗连接提供高的电流承载能力。所述导体件是由电学上高电导率的材料构成的电连接的一个实施例，其中所述电连接具有高电流承载能力以及简单的机械可加工性(例如通过冲压和/或弯曲)。所述材料可以被塑性成形。
根据另一有利地扩展方案，在导体件延伸到膜平面上的情况下，在连接弯形体范围内实施对载体膜的去除，并且将连接弯形体与衬底上的相对的连接面相固定和/或电接触。
根据另一有利的扩展方案，所述导体件借助于焊接被固定和/或电接触。通过这种方式，该导体件可以容易地通过常规方式来加工。被涂敷在膜上的电子器件在裸露的上侧与相应的预成形的例如具有铜的导体件焊接在一起。
根据另一有利的扩展方案，借助于注塑来产生电隔离的块件，其中在所述注塑中，在绝缘材料的情况下，一个端接侧是膜，并且另一端接侧是对应于冲弯件的构造的相应预成形的三维注塑模。
根据另一有利的扩展方案，载体膜为光敏的，使得可以通过简单的方式借助于曝光实施对载体膜的去除。去除载体膜的另一有利的和简单的可能性借助于烧蚀、尤其是激光烧蚀进行。通过这种方式，借助于曝光或者借助于烧蚀法(激光等)对电子器件的下侧、以及向下引导的连接弯形体清除膜材料。根据该扩展方案可以在后面的步骤在适当的位置打开载体膜。在烧蚀的情况下，载体膜不能是光敏的。
根据另一有利的扩展方案，借助于焊接和/或粘合实施下侧的连接面和/或连接弯形体与衬底板的相应连接面的固定和/或电接触。通过这种方式，所述固定和/或电接触是简单的。最后的焊接或粘合法将所提供的DCB衬底板与电接触的裸露的面电连接。
根据另一有利的扩展方案，根据要产生的装置的一定的功能构造将所述器件固定在载体膜上的一定位置处。也就是说，在第一步骤，在电隔离的载体膜上，在一定位置的下侧通过粘接而装上电子器件。由此可以特别早地实施装置的设计。
根据另一有利的扩展方案，在电隔离的块件中和/或在衬底板上定位有用于冷却的具有高冷却能力的单元、尤其是冷却通道、散热器、或者热管。通过这种方式，可以提供具有高冷却能力的冷却。同样可以在两侧、即既在DCB衬底的下侧又在电子器件的上侧构造冷却。
根据另一有利的扩展方案，所述导体件具有电学上高电导率的材料、比如铜。
根据另一有利的扩展方案，导体件和电隔离材料的膨胀系数为了产生高的热机械和电循环坚固性而彼此适配。
根据另一有利的扩展方案，提供一种固定地存留在载体膜上的设备。
附图说明
结合附图根据实施例来进一步说明本发明。附图：
图1示出了根据本发明的装置的实施例；
图2示出了用于制造本发明装置的本发明方法的实施例。
具体实施方式
图1示出了两个未装壳体的电子器件1、更确切地说为两个绝缘栅双极型晶体管(IGBT)。
在上侧3分别产生连接面7。在下侧5分别产生两个连接面7。所有连接面7都被用于固定和/或电接触电子器件1。电子器件1例如是功率半导体器件、并且尤其是用于1000伏以上电压的电子器件。器件1利用其下侧5被固定在延伸超出下侧5的面的电隔离载体膜13上。利用上侧3的连接面7，作为导电导体件15的预成形的三维结构被固定并且被电接触，其中导体件15延伸超出上侧3的面。在载体膜13与导体件15的三维结构之间产生电隔离的块件(Masse)17。例如，电隔离的块件17可以借助于注塑来产生。在此，尤其是可以使用常规的注塑模来成形电隔离的块件17。根据图1，导体件15产生延伸到载体膜13的平面上的连接弯形体(Anschlussbügel)16。在器件1的下侧5的连接面7上产生具有开口21的载体膜13。同样，载体膜13在连接弯形体16范围内被去除，并且相应地具有开口21。
在载体膜13之下产生衬底11，所述衬底11特别有利地为直接铜接合陶瓷衬底。在衬底11的上侧预先结构化有印制导线，在所述印制导线上产生衬底11的连接面9。这样的连接面9与器件1的一侧的连接面7相对。器件1利用其下侧5在两个连接面7的范围内与衬底11上的两个相对的连接面9相固定并且电接触。所述接触特别简单地借助于焊剂19进行。在导体件15延伸到载体膜13的平面上的情况下，载体膜13在连接弯形体16范围内被去除并且具有开口21。连接弯形体16与衬底11上的相对的连接面9相固定并且电接触。根据图1的三个下面的指向远离衬底方向的箭头指向用于冷却根据本发明的装置的散热器23。可替换地，可以在导体件15上、在电隔离的块件17中、和/或在衬底11上定位或产生用于冷却的单元、尤其是冷却通道、散热器23和/或热管。图1中的指向上方的箭头指示具有连接面9的衬底11和具有连接面7的电子器件1的固定和电接触。
图2示出了根据本发明的用于接触至少一个未装壳体的电子器件1、尤其是功率器件或半导体功率器件的方法的实施例，其中所述电子器件1具有至少一个分别被布置在上侧3和/或下侧5的用于固定和/或电接触的连接面7。
在步骤S1，将器件1利用其下侧5固定到超出下侧5的面的电隔离载体膜13上。借助于步骤S2，将上侧3的连接面7分别与形成预成形的三维结构的、延伸超出上侧3的面的导电导体件15相固定和/或电接触。借助于步骤S3，在载体膜13与导体件15的三维结构之间产生电隔离的块件17。在此，可以应用常规的注塑法。尤其是可以使用常规的工件来限制电隔离的块件17。利用步骤S4，在连接面7的范围内从下侧5去除载体膜13。最后，利用步骤S5，将下侧5的连接面7与衬底11上的印制导线25上的同相应连接面7相对的连接面9相固定以及电接触，其中特别有利地使用直接铜接合(DCB)陶瓷衬底板11。
在此指出，根据图1的装置仅仅是本发明的实施例。原则上可以使用任意的未装壳体的电子器件1。本发明尤其是适用于高于1000伏的高压范围内的器件。所述器件可以根据一定的功能构造而被固定和/或电接触在载体膜13上的一定位置处。电子器件1的另外的例子是二极管、晶闸管、晶体管等。同样可以使用许多连接弯形体16。原则上，连接弯形体16不是必需的。附图标记25标出衬底11上的印制导线结构，在DCB衬底的情况下，印制导线25尤其是具有铜。
原则上，没有衬底板11的本发明装置作为设备同样被涵盖在保护范围之内。

Claims (18)

1.一种接触至少一个未装壳体的电子器件(1)的方法，所述电子器件具有至少一个分别布置在上侧(3)和/或下侧(5)的用于固定和/或电接触的连接面(7)，其特征在于，
-将所述器件(1)利用其下侧(5)固定到超出下侧(5)的面的电隔离载体膜(13)上；
-将上侧(3)的连接面(7)分别与形成预成形的三维结构的、延伸超出上侧(3)的面的导电导体件(15)相固定和/或电接触；
-在载体膜(13)与导体件(15)的三维结构之间产生电隔离的块件(17)；
-在连接面(7)的范围内从下侧(5)去除载体膜(13)；
-将下侧(5)的连接面(7)分别与衬底(11)上的同该连接面(7)相对的连接面(9)相固定和/或电接触。
2.根据权利要求1所述的方法，
其特征在于
从导体件(15)产生至少一个延伸到膜平面上的连接弯形体(16)。
3.根据权利要求2所述的方法，
其特征在于
在连接弯形体(16)范围内实施对载体膜(13)的去除，并且将连接弯形体(16)与衬底(11)上的相对的连接面(9)相固定和/或电接触。
4.根据权利要求1、2或3所述的方法，其特征在于
借助于焊接或借助于焊剂(19)实施具有铜的导体件(15)和/或器件(1)的连接面(7)到衬底(11)的固定和/或电接触。
5.根据权利要求1、2或3所述的方法，
其特征在于
借助于注塑来产生电隔离的块件(17)，和/或使用注塑模来成形该块件(17)。
6.根据权利要求1至3之一所述的方法，
其特征在于
载体膜(13)为光敏的，并且借助于曝光和/或烧蚀来去除载体膜(13)或产生载体膜(13)中的开口(21)。 
7.根据权利要求1至3之一所述的方法，
其特征在于
借助于焊接和/或粘合实施下侧(5)的连接面(7)和/或连接弯形体(16)与衬底(11)的相应连接面(9)的固定和/或电接触。
8.根据权利要求1至3之一所述的方法，
其特征在于
将下侧(5)的连接面(7)分别与作为所述衬底(11)的DCB陶瓷衬底上的同该连接面(7)相对的连接面(9)相固定和/或电接触。
9.根据权利要求1至3之一所述的方法，
其特征在于
在导体件(15)上、在电隔离的块件(17)中、和/或在衬底(11)上定位有用于冷却的冷却通道、散热器(23)、和/或热管。
10.一种借助于根据权利要求1至9之一所述的方法制造的装置，
其特征在于
-至少一个未装壳体的电子器件(1)，其具有至少一个分别布置在上侧(3)和/或下侧(5)的用于固定和/或电接触的连接面(7)，其中
-所述器件(1)利用其下侧(5)在连接面(7)的范围内分别与衬底(11)上的相对的连接面(9)相固定和/或电接触；
-在连接面(7)的范围之外并超出下侧(5)，在衬底(11)朝向器件(1)的侧产生电隔离的载体膜(13)；
-上侧(3)的连接面(7)分别与形成预成形的三维结构的、延伸超出上侧(3)的面的导电导体件(15)相固定和/或电接触；其中
-在载体膜(13)与导体件(15)的三维结构之间产生有电隔离的块件(17)。
11.根据权利要求10所述的装置，
其特征在于
从导体件(15)产生至少一个延伸到膜平面上的连接弯形体(16)。
12.根据权利要求11所述的装置，
其特征在于
载体膜(13)在连接弯形体(16)范围内被去除并且产生开口(21)，并且连接弯形体(16)与衬底(11)上的相对的连接面(9)相固定和 /或电接触。
13.根据权利要求10、11或12所述的装置，
其特征在于
导体件(15)具有铜。
14.根据权利要求10至12之一所述的装置，
其特征在于
所述衬底(11)是DCB陶瓷衬底。
15.根据权利要求10至12之一所述的装置，
其特征在于
在导体件(15)上、在电隔离的块件(17)中、和/或在衬底(11)上定位有用于冷却的冷却通道、散热器(23)、和/或热管。
16.根据权利要求10至12之一所述的装置，
其特征在于
导体件(15)和电隔离的块件(17)的膨胀系数彼此适配。
17.一种设备，
其特征在于
-至少一个未装壳体的电子器件(1)，其具有至少一个分别布置在上侧(3)和/或下侧(5)的用于固定和/或电接触的连接面(7)，其中
-所述器件(1)利用其下侧(5)固定在延伸超出下侧(5)的面的电隔离载体膜(13)上；
-上侧(3)的连接面(7)分别与形成预成形的三维结构的、延伸超出上侧(3)的面的导电导体件(15)相固定和/或电接触；其中
-在载体膜(13)与导体件(15)的三维结构之间产生有电隔离的块件(17)。
18.根据权利要求17所述的设备，
其特征在于
从导体件(15)产生至少一个延伸到膜平面上的连接弯形体(16)。 
CN2008801137606A 2007-09-04 2008-08-04 接触电子器件的方法、用其制造的装置和相应的设备 Expired - Fee Related CN101842887B (zh)

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DE102007041921A DE102007041921A1 (de) 2007-09-04 2007-09-04 Verfahren zur Herstellung und Kontaktierung von elektronischen Bauelementen mittels einer Substratplatte, insbesondere DCB-Keramik-Substratplatte
PCT/EP2008/060196 WO2009030562A1 (de) 2007-09-04 2008-08-04 Verfahren zur herstellung und kontaktierung von elektronischen bauelementen mittels einer substratplatte, insbesondere dcb-keramik-substratplatte

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2594867T3 (es) 2007-03-09 2016-12-23 Alexza Pharmaceuticals, Inc. Unidad de calentamiento para usar en un dispositivo de administración de fármaco
US20100065052A1 (en) * 2008-09-16 2010-03-18 Alexza Pharmaceuticals, Inc. Heating Units
US20120048963A1 (en) 2010-08-26 2012-03-01 Alexza Pharmaceuticals, Inc. Heat Units Using a Solid Fuel Capable of Undergoing an Exothermic Metal Oxidation-Reduction Reaction Propagated without an Igniter
US8941208B2 (en) * 2012-07-30 2015-01-27 General Electric Company Reliable surface mount integrated power module
DE102014203306A1 (de) * 2014-02-25 2015-08-27 Siemens Aktiengesellschaft Herstellen eines Elektronikmoduls
KR102454754B1 (ko) 2015-03-11 2022-10-14 알렉스자 파마스티칼즈, 인크. 열 에어로졸 응축 공정을 위한 에어웨이에서 대전방지 소재의 용도
DE102016220553A1 (de) 2016-10-20 2018-04-26 Robert Bosch Gmbh Leistungsmodul

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
EP1641035A1 (en) * 2004-09-27 2006-03-29 STMicroelectronics S.r.l. Mounting method of electronic power components on printed circuit boards

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2751450B2 (ja) * 1989-08-28 1998-05-18 セイコーエプソン株式会社 テープキャリアの実装構造及びその実装方法
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
JPH09116045A (ja) * 1995-10-13 1997-05-02 Dainippon Printing Co Ltd リードフレームを用いたｂｇａタイプの樹脂封止型半導体装置およびその製造方法
WO2001024260A1 (en) * 1999-09-24 2001-04-05 Virginia Tech Intellectual Properties, Inc. Low cost 3d flip-chip packaging technology for integrated power electronics modules
US7402457B2 (en) 2001-09-28 2008-07-22 Siemens Aktiengesellschaft Method for making contact with electrical contact with electrical contact surfaces of substrate and device with substrate having electrical contact surfaces
JP2003204027A (ja) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法
JP2003341782A (ja) * 2002-05-27 2003-12-03 Oki Electric Ind Co Ltd 電子デバイス収容体、電子デバイスの搬送方法、電子デバイスの実装方法、電子デバイスの収容方法
JP3809168B2 (ja) * 2004-02-03 2006-08-16 株式会社東芝 半導体モジュール
DE102004030042B4 (de) * 2004-06-22 2009-04-02 Infineon Technologies Ag Halbleiterbauelement mit einem auf einem Träger montierten Halbleiterchip, bei dem die vom Halbleiterchip auf den Träger übertragene Wärme begrenzt ist, sowie Verfahren zur Herstellung eines Halbleiterbauelementes

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
EP1641035A1 (en) * 2004-09-27 2006-03-29 STMicroelectronics S.r.l. Mounting method of electronic power components on printed circuit boards

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