CN101802990B - 使用穿透硅通道的半导体封装方法 - Google Patents
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- CN101802990B CN101802990B CN2008801066189A CN200880106618A CN101802990B CN 101802990 B CN101802990 B CN 101802990B CN 2008801066189 A CN2008801066189 A CN 2008801066189A CN 200880106618 A CN200880106618 A CN 200880106618A CN 101802990 B CN101802990 B CN 101802990B
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Abstract
Description
Claims (29)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310022626.8A CN103178032B (zh) | 2007-07-31 | 2008-07-31 | 使用穿透硅通道的半导体封装方法 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US96275207P | 2007-07-31 | 2007-07-31 | |
US60/962,752 | 2007-07-31 | ||
PCT/US2008/009356 WO2009017835A2 (en) | 2007-07-31 | 2008-07-31 | Semiconductor packaging process using through silicon vias |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201310022626.8A Division CN103178032B (zh) | 2007-07-31 | 2008-07-31 | 使用穿透硅通道的半导体封装方法 |
Publications (2)
Publication Number | Publication Date |
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CN101802990A CN101802990A (zh) | 2010-08-11 |
CN101802990B true CN101802990B (zh) | 2013-03-13 |
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ID=40305147
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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CN201310022626.8A Active CN103178032B (zh) | 2007-07-31 | 2008-07-31 | 使用穿透硅通道的半导体封装方法 |
CN2008801066189A Active CN101802990B (zh) | 2007-07-31 | 2008-07-31 | 使用穿透硅通道的半导体封装方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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CN201310022626.8A Active CN103178032B (zh) | 2007-07-31 | 2008-07-31 | 使用穿透硅通道的半导体封装方法 |
Country Status (6)
Country | Link |
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US (2) | US8193615B2 (zh) |
EP (1) | EP2183770B1 (zh) |
JP (2) | JP2010535427A (zh) |
KR (2) | KR101588723B1 (zh) |
CN (2) | CN103178032B (zh) |
WO (1) | WO2009017835A2 (zh) |
Families Citing this family (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1517166B1 (en) | 2003-09-15 | 2015-10-21 | Nuvotronics, LLC | Device package and methods for the fabrication and testing thereof |
US7901989B2 (en) | 2006-10-10 | 2011-03-08 | Tessera, Inc. | Reconstituted wafer level stacking |
US7829438B2 (en) | 2006-10-10 | 2010-11-09 | Tessera, Inc. | Edge connect wafer level stacking |
US8513789B2 (en) | 2006-10-10 | 2013-08-20 | Tessera, Inc. | Edge connect wafer level stacking with leads extending along edges |
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Also Published As
Publication number | Publication date |
---|---|
WO2009017835A3 (en) | 2009-04-16 |
US20120241976A1 (en) | 2012-09-27 |
US8193615B2 (en) | 2012-06-05 |
KR20100065151A (ko) | 2010-06-15 |
CN101802990A (zh) | 2010-08-11 |
WO2009017835A2 (en) | 2009-02-05 |
KR101588723B1 (ko) | 2016-01-26 |
CN103178032A (zh) | 2013-06-26 |
JP2013175764A (ja) | 2013-09-05 |
EP2183770B1 (en) | 2020-05-13 |
US8735287B2 (en) | 2014-05-27 |
EP2183770A2 (en) | 2010-05-12 |
CN103178032B (zh) | 2017-06-20 |
US20090065907A1 (en) | 2009-03-12 |
KR101538648B1 (ko) | 2015-07-22 |
EP2183770A4 (en) | 2010-08-04 |
JP2010535427A (ja) | 2010-11-18 |
KR20150045953A (ko) | 2015-04-29 |
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