TW569395B - Method of forming a stacked-gate cell structure and its NAND-type flash memory array - Google Patents
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569395 五、發明說明（1) 發明背景： (1) 發明範疇 本發明與一船非把# 件及其記憶陣列有關揮；性（non_volatile)半導體記憶元 gate)細胞元結構及A 4寺別是與一種疊堆閘（stacked _ 製造方法有關。 /、非和型（NAND-type)快閃記憶陣列的 (2) 習知技藝描述 基本f/i : t : ^構係組成-個高密度快閃記憶陣列的 胞元可以利結構”。…-個營堆間細 間的重疊區或位^於漂浮閘與共源擴散區之 勒（Fowler)〜笔彳1 ; 導體基板之間的重營區之富 通道埶雷子4。 （ heim)穿透機制來擦洗。通常， 通道熱電子左入機制的寫入功 且疊堆閘長由於以& t 权同且寫入效率权差並 述穿效應的限制係較不易加予微縮化。上 種寫心；=構利用通道熱電子注入機制來作為-二1:且成一種非或型（_-type)記憶陣列。 制於i元結構可以藉由富勒_諾得漢穿透機 半導體基板之間來寫入及擦洗，以獲得低功 元結構"剖面圖非如y ;之統疊堆閘= 堆問細胞元結構處於一個寫入’丨中圖- A顯-邊疊 U、 1U馬入狀悲；而圖一 B顯示該疊堆569395 V. Description of the invention (1) Background of the invention: (1) The scope of the invention The present invention relates to a boat non-operating device and its memory array; non-volatile semiconductor memory cell gate cell structure and A 4 temple are It is related to a stacked _ manufacturing method. (2) of the NAND-type flash memory array (2), the conventional art describes the basic f / i: t: ^ structure system composition-a high-density fast Cells of flash memory arrays can benefit from structures ....-an overlapping area between individual camps or between the floating gate and the common source diffusion zone ~ Fowler ~ pen 彳 1; the heavy camp area between the conductor substrates Rich channel 埶 雷 子 4. (heim) Penetration mechanism to scrub. Generally, the writing work of the channel hot electron left-entry mechanism and the stack gate length are the same as & t The limitation of the effect is that it is not easy to add miniaturization. The above writes the mind; the structure uses the channel hot electron injection mechanism as -2 1: and forms a non-or-type (_-type) memory array. Write and scrub through Fuller-Nordheim penetrating between semiconductor substrates to obtain low power element junctions The structure " cross section is not as y; the system stack gate = the cell structure of the stack is in a writing '丨 Figure-A shows-edge stack U, 1U horse into a sad state; and Figure 1 B shows the stack
569395 五、發明說明（2) 閘細胞元結構處於擦洗的狀態。由圖一 A及圖一 B可以清楚 地看出，一個閘疊堆（gate stack)由上而下至少包含_個 矽化鎢層105、一個摻雜複晶矽層1〇4、一個閘間（inte卜 gate)介電層103、一個摻雜複晶石夕層1〇2、及一個穿透氧 化層1 0 1通常係以所使用技術之一個最小線寬（F )來定義且 置於形成於一個η井3 0 0 a之内的一個p井3 0 0 b之上；以及對 稱共源/洩n+擴散區l〇6a/ 106b係以自動對準的方式佈植 一個高劑量的摻雜質於該p井 1 〇Ob之内並以該閘疊堆作為 一個離子佈植的罩幕。由圖一 A可以看出，當該控制閘1 〇 $ / 1 0 4外加一個高正閘電壓（例如+1 8伏），該源/洩n +擴散 區1 0 6 a/ 1 〇 6 b、該ρ井1 0 0 b及該η井1 〇 〇 a係接地，則位於該 穿透氧化層1 〇 1之下的感應表面反向（inversi〇n)層及源/ 洩n+擴散區l〇6a/ 10 6b之電子會穿透該穿透氧化層1〇1至 該漂浮閘層102内以執行一個寫入的操作。由圖一 B可以看 出，當該=制閘105/ 1〇4接地，該姘1〇〇b及該_ i〇〇a 外加一個尚正電壓（例如 / ί nh / ] μμΛ )，而該源/汽n+擴散區 a f ^ it f ^ V ^ 102^ 1 ^ ^ 操作。這裡可以清楚：看出，％ 10:b以執行-個擦洗的 細胞元結構的閑長加予微縮化：圖：A及圖- B之該疊堆閉 將快速縮小，而寫入及捧洗 j寫入及擦洗的有效面積 寫入的外加控制閘電壓及捭=的二將亦隨之降低。另外， 的高，因此一個漂浮問結&且的外加P井和η井電壓係相對 rat io)係屬必要，方能降彳·、有一個高耦合比（coupl ing &寫入的外加控制電壓及擦洗的569395 V. Description of the invention (2) The gate cell structure is in a scrubbing state. It can be clearly seen from FIG. 1A and FIG. 1B that a gate stack from top to bottom includes at least one tungsten silicide layer 105, a doped polycrystalline silicon layer 104, and a gate ( (Inte gate) dielectric layer 103, a doped polycrystalline stone layer 102, and a penetrating oxide layer 101 are usually defined by a minimum line width (F) of the technology used and placed in the formation On a p-well 3 0 0 b within a η-well 3 0 a; and a symmetrical common source / drain n + diffusion region 106a / 106b is implanted with a high dose of doping in an auto-aligned manner It is within 100Ob of the p-well and uses the gate stack as an ion implanted mask. It can be seen from Fig. 1A that when the control gate 10 ￥ / 104 is applied with a high positive gate voltage (for example, + 18 volts), the source / drain n + diffusion region 10 6 a / 1 〇 6 b , The ρ well 10 0 b and the η well 100a are grounded, then the induction surface inversion layer and source / drain n + diffusion region 1 located below the penetration oxide layer 101 The electrons of 〇6a / 10b will penetrate the penetrating oxide layer 101 to the floating gate layer 102 to perform a write operation. It can be seen from Fig. 1B that when the gate brake 105/1104 is grounded, the 姘 100b and the _i〇〇a plus a still positive voltage (for example / ί nh /] μμΛ), and the source / Steam n + diffusion region af ^ it f ^ V ^ 102 ^ 1 ^ ^ operation. It can be clearly seen here that% 10: b is miniaturized by the idle length of the cell structure that performs one scrub: Figures: A and Figure-B. The stack closure will quickly shrink, while writing and washing The applied control gate voltage and the effective area write of j writing and scrubbing will also decrease. In addition, it is high, so a floating junction & plus the voltages of wells P and η is relatively necessary in order to reduce 彳. There is a high coupling ratio (coupling & Controlled voltage and scrubbing
第7頁 569395 五、發明說明（3) 外加p井及η井電壓。一個淺凹槽隔離（ST I )結構具有一種 非自動對準漂浮閘層且具有一個高耦合比需要二個嚴謹（ cr i t i ca 1 )罩幕步驟而製造一個非和型快閃記憶陣列於該 自動對準淺凹槽隔離結構之上至少需要四個嚴謹的罩幕步 驟。 因此，本發明的一個主要目的係當疊堆閘長縮小時能 提供一個非和型快閃記憶陣列之一種疊堆閘細胞元結構具 有一種斜角漂浮閘結構來擁有較大的寫入及擦洗面積。 本發明的另一個目的係提供具有一個較大耦合比之一 種自動對準漂浮閘結構。 本發明的一個更進一步目的係提供一種無接點非和型 快閃記憶陣列具有較少的嚴謹罩幕步驟及較小之單位細胞 元的製造方法。 發明概述： 本發明之疊堆閘細胞元結構具有一種斜角漂浮閘層係 用來組成一種無接點非和型快閃記憶陣列，其中上述之斜 角漂浮閘層不但提供一個較大表面積於一個穿透介電層之 上來寫入及擦洗而無需加大控制閘長並且提供斜角尖端來 提昇擦洗的速度。本發明之無接點非和型快閃記憶陣列係 製造於具有一種自動對準漂浮閘結構的一種淺凹槽隔離結 構之上，其中上述之自動對準漂浮閘結構能提供比先前技 術具有一個較高的耦合比且較少的嚴謹罩幕步驟來製造以 及一個平滑表面來形成一個閘間介電層以降低尖角的場發Page 7 569395 V. Description of the invention (3) The voltage of well p and well η is added. A shallow groove isolation (ST I) structure with a non-automatically aligned floating gate layer and a high coupling ratio requires two rigorous (cr iti ca 1) curtain steps to fabricate a non-harmonic flash memory array. At least four rigorous masking steps are required to automatically align the shallow groove isolation structure. Therefore, a main object of the present invention is to provide a non-Japanese flash memory array when the stack gate length is reduced. A stack gate cell structure has an oblique floating gate structure to have a larger write and scrub. area. Another object of the present invention is to provide an auto-aligned floating gate structure having a large coupling ratio. A still further object of the present invention is to provide a method for manufacturing a contactless non-harmonic flash memory array with fewer rigorous masking steps and a smaller unit cell. Summary of the invention: The stacked gate cell element structure of the present invention has an oblique-angle floating gate layer for forming a non-contact non-harmonic flash memory array. The above-mentioned oblique-angle floating gate layer not only provides a large surface area on A penetrating dielectric layer is used for writing and scrubbing without increasing the control gate length and providing a beveled tip to increase the speed of scrubbing. The non-contact non-harmonic flash memory array of the present invention is manufactured on a shallow groove isolation structure having an automatic alignment floating gate structure, wherein the above-mentioned automatic alignment floating gate structure can provide a Higher coupling ratio and fewer rigorous masking steps to fabricate and a smooth surface to form an inter-gate dielectric layer to reduce sharp field emission
569395 五、發明說明（4) 射效應。上述之無接點非和型快閃記憶陣列的串選擇線及 接地選擇線之寬度藉由一個墊層形成技術來定義可以製造 成比所使用技術的一個最小線寬還小。上述之串選擇線及 接地選擇線的每一個之下的選擇閘電晶體之導電間係製造 成具有一個單邊斜角結構，因而能提供比該串接地選擇線 之寬度較長的通道長度。本發明之共源導電管線的每一個 係形成於由一個共源擴散區及一個第三突出場氧化物層所 交變地組成的一個第一平坦床之上，因而可以輕易地獲得 一個較低的管線電阻及相對於半導體基板間之一個較低的 管線電容。本發明之位元線接觸點的每一個係由一個平面 化共洩導電島所組成且與一個金屬位元線同時成形，因而 可以在一個微縮接觸技藝下輕易地提供一個較大的接觸面 積及一個較高的接觸可靠度。本發明之無接點非和型快閃 記憶陣列可以比先前技術需要更少的嚴謹罩幕光阻步驟來 製造且具有較小的單位細胞元尺寸。 發明之詳細說明： 現請參考圖二A及圖二B，其中本發明之一個疊堆閘細 胞元結構操作於一個寫入狀態如圖二A所示及操作於一個 擦洗狀態如圖二B所示。本發明之疊堆閘細胞元結構由上 而下至少包含一個複合控制閘3 1 Oa/ 3 0 9b、一個閘間介電 層3 08a、一個斜角漂浮閘層3 0 2b、及一個穿透介電層30 lb 形成於位於一個η井3 0 0 a之内的一個p井3 0 0 b之上；及源/ 洩擴散區3 1 2 a具有一個橫向梯度掺雜分佈係以自動對準的569395 V. Description of the invention (4) Radiation effect. The width of the string selection line and the ground selection line of the above-mentioned non-contact and non-type flash memory array is defined by a pad formation technology and can be made smaller than a minimum line width of the used technology. The conductive space of the selection gate transistor under each of the above-mentioned string selection line and ground selection line is manufactured to have a single-sided bevel structure, so that it can provide a longer channel length than the width of the string ground selection line. Each of the common source conductive pipelines of the present invention is formed on a first flat bed composed of a common source diffusion region and a third protruding field oxide layer alternately, so that a lower And a lower line capacitance relative to the semiconductor substrate. Each of the bit line contact points of the present invention is composed of a planarized common leakage conductive island and is simultaneously formed with a metal bit line, so it can easily provide a larger contact area under a miniature contact technology and A higher contact reliability. The contactless NAND flash memory array of the present invention can be manufactured with fewer rigorous mask photoresist steps than the prior art and has a smaller unit cell size. Detailed description of the invention: Please refer to FIG. 2A and FIG. 2B, wherein a stack gate cell structure of the present invention operates in a writing state as shown in FIG. 2A and operates in a scrubbing state as shown in FIG. 2B Show. The cell structure of the stack gate of the present invention includes at least one composite control gate 3 1 Oa / 3 0 9b, an inter-gate dielectric layer 3 08a, an oblique floating gate layer 3 0 2b, and a penetration from top to bottom. A dielectric layer 30 lb is formed on a p-well 3 0 0 b located within an n-well 3 0 a; and the source / drain diffusion region 3 1 2 a has a lateral gradient doping profile for automatic alignment of
第9頁 569395 五、發明說明（5) 方式跨過該斜角漂浮閘層3 0 2 b之斜角部份及該穿透介電層 3 0 1 b佈植一個高劑量的摻雜質於該p井3 0 0 b内。很明顯地 ，本發明之疊堆閘細胞元結構比圖一 A及圖一 B所示之先前 技術在已知的控制閘長下能提供面對該穿透介電層3 0 1 b更 大的一個表面積。如圖二A所示的寫入狀態，該共源及洩 擴散區31 2a及該半導體基板（P井30 0b及η井3 0 0a)係接地 ，該複合控制閘層31 0a/ 3 0 9b係外加一個高正電壓vCG，電 子可以由該共源/洩擴散區3 1 2 a及p井3 0 0 b所產生的表面 反向層穿透該穿透介電層至該斜角漂浮閘302b内，如箭頭 所標示。如圖二B所示的擦洗狀態，該複合控制閘層3丨〇a / 3 0 9 b係接地’ $亥共源/ 擴散區3 1 2 a係浮接，而該半導 體基板（p井3 0 0 b及η井3 0 0 a )係外加一個正高電壓v μ，則儲 存於該斜角漂浮閘302 b的電子可以穿透該穿透介電層3〇lb 至該P井3 0 0b及該共源/洩擴散區312a。這裡可以清楚地 看到’圖二B所示的擦洗面積比圖一 B所示的先前技術大。 另外’該斜角漂浮閘層3 0 2b的尖角亦可增強擦洗狀態的穿 透電流。在後續的展示中，一種自動對準漂浮閘結構係形 成於閘寬度方向來增加該斜角漂浮閘層3 0 2b的耦合比，而 寫入狀態之該外加控制電壓V c及擦洗狀態之該外加基板電 壓V SB可以進一步加予降低。 現請參考圖三A至圖三F，其中揭示製造具有高耦合比 之一種自動對準漂浮閘結構的一種淺凹槽隔離結構以製造 一個前進非和型陣列。 圖二A顯示一個穿透介電層3 〇 1係形成於一個第一導電Page 9 569395 V. Description of the invention (5) A high-dose dopant is implanted across the oblique portion of the oblique floating gate layer 3 0 2 b and the penetrating dielectric layer 3 0 1 b. The p well is within 3 0 0 b. Obviously, the stack gate cell structure of the present invention is larger than the prior art shown in FIG. 1A and FIG. 1B under the known control gate length, which can face the penetrating dielectric layer 3 0 1 b. A surface area. As shown in the writing state shown in FIG. 2A, the common source and drain diffusion region 31 2a and the semiconductor substrate (P well 30 0b and η well 3 0 0a) are grounded, and the composite control gate layer 31 0a / 3 0 9b Plus a high positive voltage vCG, the electrons can penetrate the penetrating dielectric layer to the oblique floating gate by the surface inversion layer generated by the common source / drain diffusion region 3 1 2 a and p well 3 0 0 b Within 302b, as indicated by the arrow. As shown in the scrubbing state shown in FIG. 2B, the composite control gate layer 3 丨 〇a / 309b is grounded, and the semiconductor substrate (p well 3) is floating. 0 0 b and η well 3 0 0 a) are applied with a positive high voltage v μ, then the electrons stored in the oblique floating gate 302 b can penetrate the penetrating dielectric layer 30 lb to the P well 3 0 0b And the common source / drain diffusion region 312a. It can be clearly seen here that the scrubbing area shown in FIG. 2B is larger than the prior art shown in FIG. 1B. In addition, the sharp angle of the oblique floating gate layer 3 2b can also enhance the penetrating current in the scrub state. In the subsequent display, an automatic alignment floating gate structure is formed in the width direction of the gate to increase the coupling ratio of the oblique floating gate layer 3 2 2b, and the applied control voltage V c in the write state and the scrub state The applied substrate voltage V SB can be further reduced. Referring now to FIGS. 3A to 3F, it is disclosed that a shallow groove isolation structure for fabricating a self-aligned floating gate structure with a high coupling ratio is fabricated to make a forward non-harmonic array. FIG. 2A shows that a penetrating dielectric layer 301 is formed on a first conductive layer.
第10頁 569395 五、發明說明（6) 型的一個半導體基板3 0 0之上；一個第一導電層3 〇 2係形成 於該穿透介電層301之上；以及一個第一罩幕介電層3〇3係 形成於該第一導電層3 0 2之上。上述之穿透介電層3〇1係一 個熱（thermal )二氧化矽層或一個氮化（nitrided)熱二氧 化石夕層且其厚度係介於6 0埃和1 2 0埃之間。上述第一導電 層3 0 2係由摻雜複晶石夕或摻雜非晶矽所組成且利用lpcvd法 來堆積’其厚度係介於1 〇 〇 〇埃和5 0 〇 〇埃之間。上述之第一 罩幕介電層3 0 3係由氮化矽所組成且利用lpcvd法來堆積， 其厚度係介於1 5 0 0埃和3 0 0 0埃之間。 ^圖三6顯示複數淺凹槽隔離區（STI)及複數主動區（AA) 藉一個罩幕光阻步驟PR1 (未圖示）交變地成形（patterned) ，該半導體基板3 0 0之上，而複數淺凹槽係填滿平面化場 氧化物層304a。上述之淺凹槽隔離區（STI )的寬度及該主 動區的寬度可以利用所使用技術的一個最小線寬（F )來定 義。上述之平面化場氧化物層3 〇 4 a係由二氧化矽、磷玻璃 (P-glass)、及硼磷玻璃（bp -giass)所組成且利用lpcvd、 高密度電漿（HDP) CVD、或電漿增強（PE) cvD法來堆積，係 先堆積一個厚二氧化矽膜3 〇 4來填滿該深凹槽的每一個空 隙再利用CMP法將所堆積之厚二氧化矽膜3〇4加予平面化並 以該成形第一罩幕介電層303 a作為一個磨平停止層（p〇ii 一 shi ng stop)。該淺凹槽位於該半導體基板3〇〇的深度係等 於2 5 0 0埃至5 0 0 0埃之間。 圖二C顯示該平面化場氧化物層3 〇 4 a係藉非等向乾式 蚀刻或屋式餘刻法來選擇性地回餘至約等於該成形第一導Page 10 569395 V. Description of the invention (6) a semiconductor substrate 300; a first conductive layer 3 02 is formed on the penetrating dielectric layer 301; and a first cover intermediary The electric layer 303 is formed on the first conductive layer 302. The above-mentioned penetrating dielectric layer 301 is a thermal silicon dioxide layer or a nitrided thermal dioxide layer, and its thickness is between 60 angstroms and 120 angstroms. The above-mentioned first conductive layer 30 is composed of doped polysilicon or doped amorphous silicon and is stacked using the lpcvd method. Its thickness is between 1000 angstroms and 500 angstroms. The above-mentioned first mask dielectric layer 3 0 3 is composed of silicon nitride and is stacked by the lpcvd method, and its thickness is between 15 0 angstroms and 3 0 0 angstroms. ^ FIG. 3 shows that the plurality of shallow groove isolation regions (STI) and the plurality of active regions (AA) are patterned alternately by a mask photoresist step PR1 (not shown) on the semiconductor substrate 300. The plurality of shallow grooves are filled with the planarized field oxide layer 304a. The width of the shallow groove isolation region (STI) and the width of the active region can be defined using a minimum line width (F) of the technology used. The above-mentioned planarized field oxide layer 304a is composed of silicon dioxide, phosphorous glass (P-glass), and borophosphoglass (bp-giass), and uses lpcvd, high-density plasma (HDP) CVD, Or plasma enhanced (PE) cvD method for stacking, first deposit a thick silicon dioxide film 3 04 to fill each void of the deep groove, and then use the CMP method to deposit the thick silicon dioxide film 3 0. 4 is planarized and the shaped first mask dielectric layer 303a is used as a flat stop layer (poi-ng stop). The shallow groove is located at a depth of 300 from the semiconductor substrate to between 25 and 50 angstroms. FIG. 2C shows that the planarized field oxide layer 3 0 4 a is selectively backed up to approximately equal to the first conductive shape by non-isotropic dry etching or house-etching.
569395 五、發明說明（7) 電層302a之一半厚度且以該成形第一罩幕介電層3 0 3a作為 蝕刻罩幕，以形成第一突出場氧化物層3 0 4b。 圖三D顯示一個平面化第二導電層3 0 5 a係填滿該成形 第一罩幕介電層3 0 3 a之間的每一個空隙，然後回蝕至該第 一導電層3 0 2 a的一個頂部表面水平，以形成一個回蝕第二 導電層30 5b於該第一突出場氧化物層304b的每一個之上； 以及一對第一側邊牆介電墊層（s p a c e r) 3 〇 6 a係形成於該複 數淺凹槽隔離區的每一個之鄰近成形第一罩幕介電層3〇3a 的側邊牆之上。上述之平面化第二導電層3〇5a係由摻雜複 晶石夕或摻雜非晶矽所組成且利用LPCVD法來堆積，係先堆 積一個厚第二導電層3〇5來填滿位於該成形第一罩幕介電 層3 0 3a之間的每一個空隙再利用cmp法將所堆積之厚第二 導電層305加予平面化並以該成形第一罩幕介電層3〇33作 ，一個磨平停止層。上述之第一側邊牆介電墊層3 〇 6 a係由 氣化石夕所組成且利用LPCVD法來堆積，係先堆積一個第一 介，層^06再回蝕所堆積之第一介電層3 0 6的一個厚度。這 裡可f清楚地看到，該第一側邊牆介電墊層30 6a的墊層厚 度係等於所堆積之第一介電層3 0 6的厚度且因而可以加予 控制。 圖二E顯示位於該複數淺凹槽隔離區的每一個之該對 第了側邊牆介電墊層3 0 6a之間的該回蝕第二導電層3 0 5b係 非等向性地加予去除以形成延伸第二導電層3 0 5 c ;然後， 該成形，一罩幕介電層3 0 3a及該第一側邊牆介電墊層3 0 6a 係利用高溫磷酸加予去除；接著，一對薄側邊牆導電墊層569395 V. Description of the invention (7) One and a half thicknesses of the electric layer 302a and using the formed first mask dielectric layer 3 0 3a as an etching mask to form a first protruding field oxide layer 3 0 4b. FIG. 3D shows that a planarized second conductive layer 3 0 5 a fills every gap between the formed first mask dielectric layer 3 0 3 a and is then etched back to the first conductive layer 3 0 2 a top surface of a is horizontal to form an etch-back second conductive layer 30 5b on each of the first protruding field oxide layer 304b; and a pair of first side wall dielectric spacers 3 〇6a is formed on the side wall of each of the plurality of shallow groove isolation regions adjacent to the first mask dielectric layer 303a formed. The above-mentioned planarized second conductive layer 305a is composed of doped polycrystalline silicon or doped amorphous silicon and is deposited by LPCVD method. A thick second conductive layer 305 is first deposited to fill the area. Each gap between the formed first mask dielectric layer 3 0 3a is planarized by the cmp method, and the formed first mask dielectric layer 3033 is planarized. Operation, a smooth stop layer. The above-mentioned first side wall dielectric cushion layer 3 0 6 a is composed of gasified stone and is stacked using LPCVD method. A first dielectric layer is deposited first, and the first dielectric layer is then etched back by layer ^ 06. A thickness of layer 3 0 6. It can be clearly seen here that the thickness of the pad of the first side wall dielectric pad 30 6a is equal to the thickness of the stacked first dielectric layer 3 06 and can therefore be controlled. FIG. 2E shows that the etched back second conductive layer 3 0 5b located between the pair of first side wall dielectric pads 3 0 6a in each of the plurality of shallow groove isolation regions is anisotropically added. Pre-removed to form an extended second conductive layer 3 0 5 c; then, in the forming, a mask dielectric layer 3 0 3a and the first side wall dielectric pad layer 3 6 a are removed by adding high-temperature phosphoric acid; Next, a pair of thin side wall conductive pads
第12頁 五 3 0 7a 係 導 係 積 發明說明（8) 電層3〇5e6^數淺凹槽隔離區的每一個之該延伸第二 由摻雜複曰 逆猶之上。上述之溥側邊牆導電墊層3 0 7a ，係先堆Ϊ : 3 ::非晶矽所組成且利用lpcvd法來堆 之上再回蝕所 溥導電層307於一個所形成的結構表面 清楚地看出，玲、之溥導電層3 〇 7的—個厚度。這裡可以 化該延伸第一=命側邊牆導電墊層3 〇 7 a係主要地用來圓形 圖】第—導電層305c所形成的尖角。 個結構表面』^閘間介電層308形成於圖三E所示的一 於該閘間介電層’q二後一個平面化第三導電層30 9a係形成 3 1 〇係形成於兮孚^之j1，以及接著—個第一覆蓋導電層 介電層308係—個二氧化石夕之上。上述之閘間 的厚度係介/(Ν0)結構所組成且其等效二氧化石夕 層309a係由摻雜複晶 ^ ^ f面化第三導電Page 12 Five 3 0 7a System Guidance System Description of the Invention (8) Each of the electric layer 3005e6 ^ each of the shallow groove isolation regions is extended by a second doping process. The conductive pad layer 3 0 7a of the above-mentioned side wall is first piled up: 3 :: amorphous silicon and is stacked on top by the lpcvd method, and then the back-etched conductive layer 307 is clearly formed on a structured surface. It can be seen that the thickness of the conductive layer 307 of Ling and Zhiyan is 307. Here can be extended the first corner = the side wall conductive pad layer 307a is mainly used for circular diagrams]-the sharp corner formed by the first conductive layer 305c. The inter-gate dielectric layer 308 is formed on the inter-gate dielectric layer, as shown in FIG. ^ J1, and then-a first overlying conductive layer dielectric layer 308 system-on top of the dioxide. The thickness between the gates mentioned above is composed of the meso / (N0) structure and its equivalent SiO2 layer is 309a, which is doped with polycrystalline ^ ^ f and third conductive
法來堆積且ϋI 2 非日夕所組成且利用LPCVD 一個第三導電声^9於\門^埃和3 0 0 0埃之間，係先堆積 亀層3 0 9於該閘間介電層308之上再利田rMD、+ 或傳統回蝕法將所堆積之第三導 ：：用CMP法 述之第一覆蓋導電層310係由矽化 力予平面化。上 -^ « LPCVD ^ ^ ^ ^ ^ (W^ ^ ^ 4_埃之間。這裡可以清楚地f到：测埃和 閘結構具有一個古無八μ應+ 自動對準漂浮 匕:J前技術之一個非自動對準漂浮 幕先阻步冑，並且該延伸漂浮問 ^則需一個罩 j瓚川Μ的次角係利用薄側堆积 I 2 is composed of non-day and night and uses LPCVD to conduct a third conductive sound ^ 9 between \ gate ^ angstrom and 3 0 0 angstrom, the 亀 layer 3 0 9 is first deposited on the inter-gate dielectric layer 308 Zilitian rMD, + or the traditional etch-back method will stack the third lead: the first covering conductive layer 310 described by the CMP method is planarized by the silicidation force. On- ^ «LPCVD ^ ^ ^ ^ ^ (W ^ ^ ^ 4_Angstrom. Here it can be clearly f to: the measuring Angstrom and the gate structure has an ancient eight μ should + auto-aligned floating dagger: J front technology One of the non-automatically aligned floating screens first stops, and the extended floating system requires a secondary angle system that uses the thin side.
第13頁 569395 五、發明說明（9) 邊牆導電墊層3 0 7a來加予圓形化以消除場發射效應及降低 該閘間介電層 3 0 8的可靠性問題。沿著該複數主動區的每 一個之剖面圖，如圖三F所示的一條F - F ’線係顯示於圖四A 中。這裡值得一提的是，圖三A至圖三F僅揭示形成高耦合 比之一種自動對準漂浮閘結構的一個範例。幾個修正的方 法亦可藉一個罩幕光阻步驟來形成一種自動對準漂浮閘結 構··第一個例子（未圖示）是圖三D所示之該平面化第二導 電層305a係回蝕一個小於該成形第一罩幕介電層303a的厚 度以形成頂部表面高於該成形第一導電層3 0 2 a的一個回蝕 第二導電層305b，接著進行圖三E及圖三F的製程；第二個 例子（未圖示）是一對側邊牆導電墊層係形成於圖三C所示 之該複數淺凹槽隔離區的每一個之回蝕空隙的側邊牆之上 來取代圖三D之該回蝕第二導電層3 0 5 b及該第一側邊牆介 電墊層3 0 6a，然後該成形第一罩幕介電層3 0 3a再加予去除 ，接著進行圖三E及圖三F的製程。 現請參考圖四A至圖四Η，其中揭示接續圖三F之所形 成的一種自動對準漂浮閘結構來製造本發明之一種無接點 非和型快閃記憶陣列的製程步驟及其剖面圖，其中圖二A 及圖二B之具有一個斜角漂浮閘層的一種疊堆閘細胞元結 構係作為一個記憶細胞元。 圖四A顯示一個第二罩幕介電層3 1 1係形成於圖三F所 示之一種疊堆閘結構之該第一覆蓋導電層3 1 0之上。這裡 值得強調的是，該第二罩幕介電層311可以形成於其他具 有高耦合比之一種自動對準漂浮閘結構或先前技術之其他Page 13 569395 V. Description of the invention (9) The side wall conductive pad layer 307a is rounded to eliminate the field emission effect and reduce the reliability problem of the gate dielectric layer 308. A cross-sectional view along each of the plurality of active regions, and an F-F 'line shown in Fig. 3F is shown in Fig. 4A. It is worth mentioning here that FIGS. 3A to 3F only disclose an example of an auto-aligned floating gate structure that forms a high coupling ratio. Several modified methods can also use a mask photoresist step to form an automatically aligned floating gate structure. The first example (not shown) is the planarized second conductive layer 305a shown in Figure 3D. Etching back a thickness of the formed first mask dielectric layer 303a to form an etched back second conductive layer 305b with a top surface higher than the formed first conductive layer 3 0 2a, and then performing FIG. 3E and FIG. 3 F process; the second example (not shown) is a pair of side wall conductive pads formed on the side wall of the etch-back gap of each of the plurality of shallow groove isolation areas shown in FIG. 3C. The etched back second conductive layer 3 0 5 b and the first side wall dielectric pad layer 3 6 6a are replaced instead of FIG. 3D, and then the first mask dielectric layer 3 0 3a is formed and removed. Then, the processes of FIG. 3E and FIG. 3F are performed. Please refer to FIG. 4A to FIG. 4B, which disclose the process steps and cross-sections of an automatically aligned floating gate structure formed after FIG. 3F to manufacture a contactless non-harmonic flash memory array of the present invention. Figure 2A and Figure 2B shows a stack gate cell structure with an oblique floating gate layer as a memory cell. FIG. 4A shows a second mask dielectric layer 3 1 1 formed on the first covering conductive layer 3 1 0 of a stacked gate structure shown in FIG. 3F. It is worth emphasizing here that the second mask dielectric layer 311 can be formed on another type of self-aligned floating gate structure with high coupling ratio or other types of the prior art.
第14頁 569395 五、發明說明（10) 非自動對準漂浮閘結構之上。上述之第二罩幕介電層3 i i 係由氮化矽所組成且利用LPCVD法來堆積，其厚度係介於 5 0 0 0埃和1 0 0 0 0埃之間。這裡值得注意的是，一個薄二氧 化矽層（未圖示）可以形成於該第一覆蓋導電層31〇之上來 改進該第二罩幕介電層311形成於該第一覆蓋導電層310之 上的貼著度。 圖四B顯示複數連線（interconnect)源/洩區（ISD)係 交變地被成形以形成複數閘疊堆軸（G S )，其中上述之複數 閘疊堆軸（GS)的每一個至少包含一個成形第二罩幕介電層 3 11 a、一個複合控制閘層3 1 0 a/ 3 0 9b以作為一個字線（WL) 、一個成形閘間介電層3 0 8 a、及複數斜角漂浮閘層3 0 2 b、 3 0 7 b、3 0 5 d ( 3 0 7 b及3 0 5 d如圖五C所示），然後複數連線源 /洩擴散區3 1 2 a係以自動對準的方式跨過所形成之斜角漂 浮閘結構及該穿透介電層3 0 1 a佈植第二導電型的一個高劑 量之摻雜質於該複數主動區的該半導體基板300表面，接 著一個第一平面化氧化物層313 a係形成於該複數連線源/ 洩區（I SD )的每一個空隙。上述之半導體基板至少包含_ 個p井3 0 0b形成於一個η井3 0 0a (未圖示）内，如圖二a及圖 二B所示。上述之斜角漂浮閘層302b、307b、305 d的斜角 Θ係介於9 0度和6 0度之間。上述之複數連線源/洩擴散區 3 1 2 a的每一個之摻雜質係砷或磷而其離子佈植的劑量係介 於1 0 15/平方公分和5x 1 0 15/平方公分之間。這裡可以清 楚地看到，上述之複數連線源/洩擴散區3 1 2a的每一個之 摻雜質分佈將呈橫向梯度形（lateral ly graded)，而該橫Page 14 569395 V. Description of the invention (10) Non-automatic alignment on the floating gate structure. The above-mentioned second mask dielectric layer 3 i i is composed of silicon nitride and is deposited by the LPCVD method, and its thickness is between 50 angstroms and 100 angstroms. It is worth noting here that a thin silicon dioxide layer (not shown) can be formed on the first cover conductive layer 31 to improve the second mask dielectric layer 311 formed on the first cover conductive layer 310. Closeness. FIG. 4B shows that a plurality of interconnected source / drain regions (ISD) are alternately formed to form a plurality of gate stack shafts (GS), wherein each of the plurality of gate lock shafts (GS) described above includes at least A shaped second mask dielectric layer 3 11 a, a composite control gate layer 3 1 0 a / 3 0 9b as a word line (WL), a shaped gate dielectric layer 3 0 8 a, and a plurality of oblique Angular floating gates 3 0 2 b, 3 0 7 b, 3 0 5 d (3 0 7 b and 3 0 5 d as shown in Figure 5C), and then connect the source / drain diffusion zone 3 1 2 a A high-dose dopant of the second conductivity type is implanted in the semiconductor substrate of the plurality of active regions across the formed oblique floating gate structure and the penetrating dielectric layer 3 0 1 in an automatic alignment manner. 300 surface, followed by a first planarized oxide layer 313a is formed in each void of the plurality of connected source / drain regions (ISD). The above semiconductor substrate includes at least _ wells 3 0 0b formed in an η well 3 0 0a (not shown), as shown in FIGS. 2a and 2B. The inclined angles Θ of the above-mentioned inclined floating gate layers 302b, 307b, and 305d are between 90 degrees and 60 degrees. The dopant of each of the above-mentioned multiple connected source / diffusion diffusion regions 3 1 2 a is arsenic or phosphorus and the dose of its ion implantation is between 1 0 15 / cm 2 and 5 × 1 0 15 / cm 2. between. It can be clearly seen here that the dopant distribution of each of the above-mentioned plurality of connected source / drain diffusion regions 3 1 2a will be laterally graded, and the laterally ly graded
第15頁 569395 五、發明說明（π) 向梯度形的連線源/洩擴散區3 1 2a之寬度可以藉由一個離 子佈植的能量加予控制。上述之第一平面化氧化物層3丨3a 係由二氧化石夕、填玻璃、或棚麟玻璃所組成且利用LPCVD 、HDPCVD、或PECVD來堆積’係先堆積一個厚二氧化碎層 3 1 3來填滿該成形第二罩幕介電層3 1 1 a之間的每一個空隙 再利用CMP法將所堆積之厚二氧化矽層3 1 3加予平面化並以 5亥成形第一'罩幕介電層311 a作為一個磨平停止層。這裡值 得一提的是，在未形成該第一平面化氧化物層313a之前可 以進行一個熱氧化製程以形成一個薄二氧化矽層於該閘疊 堆的側邊牆之上，包含該斜角漂浮閘層3 0 2b、3〇5d、3〇7b 。上述之連線源/洩區（ISD)的寬度及該閘疊堆轴（GS)可 以利用所使用技術的最小線寬（F)來加予定義；而圖示中 之串（string)選擇區（SSR)及接地（ground)選擇區（GSR)可 以分別定義為X i X 2 F，其中X X 2係可微縮化係數且 其值係介於2和4之間。上述之串選擇區（SSR)至少包含二 個串選擇閘區（SSG)及一個共洩區（CDR)位於該兩個串選擇 閘區（SSG)之間。上述之接地選擇閘區（GSR)至少包含兩個 接地選擇閘區（G S G )及一個共源區（c S R)位於該兩個接地選 擇閘區（GSG)之間。這裡值得一提的是，位於該串選擇區 (S S R)及该接地選擇區（GSR)之間的一串之串接快閃記憶細 胞元可以是1 6、3 2、6 4或更多的疊堆閘細胞元。 圖四C顯示利用一個非嚴謹（non —criticai)的罩幕光 阻P R 3覆蓋於細胞元串的每一個之上以作為一個蝕刻罩幕 來選擇性地及循序地去除位於該串選擇區（SSR)及該接地Page 15 569395 V. Description of the invention (π) The width of the gradient-connected source / diffusion diffusion zone 3 1 2a can be controlled by the energy of an ion implant. The above first planarized oxide layer 3 丨 3a is composed of stone dioxide, glass-filled, or shed glass, and is stacked using LPCVD, HDPCVD, or PECVD. First, a thick dioxide fragment 3 is deposited. 3 to fill each gap between the formed second mask dielectric layer 3 1 1 a and then use the CMP method to planarize the thick silicon dioxide layer 3 1 3 and form the first layer in 5 MH. 'The mask dielectric layer 311a serves as a flattening stop layer. It is worth mentioning here that before the first planarized oxide layer 313a is formed, a thermal oxidation process can be performed to form a thin silicon dioxide layer on the side wall of the gate stack, including the oblique angle. Floating gates 30 2b, 3 05d, and 3 07b. The width of the connection source / drain area (ISD) and the minimum line width (F) of the technology used in the brake stack shaft (GS) can be defined; and the string selection area in the illustration (SSR) and ground selection area (GSR) can be defined as X i X 2 F, where XX 2 is a scaleable coefficient and its value is between 2 and 4. The above-mentioned string selection area (SSR) includes at least two string selection gate areas (SSG) and a common leakage area (CDR) located between the two string selection gate areas (SSG). The above-mentioned ground selection gate area (GSR) includes at least two ground selection gate areas (GSG) and a common source area (cSR) located between the two ground selection gate areas (GSG). It is worth mentioning here that the string of flash memory cells located between the string selection area (SSR) and the ground selection area (GSR) can be 1, 6, 2, 6, 4 or more. Stacked gate cells. FIG. 4C shows that a non-criticai photoresist PR 3 is covered on each of the cell strings to serve as an etched mask to selectively and sequentially remove the selection regions located in the string ( SSR) and the ground
第16頁 569395 五、發明說明（12) 選f區（GSR)之該成形第二罩幕介電層311a、該成形第一 覆蓋導電層310a、該平面化第三導電層309b、及該成形閘 間介電層3 0 8 a，然後以自動對準的方式跨過該成形第一導 電層30 2b及該穿透介電層301 a佈植第一導電型的摻雜質於 該串選擇區（SSR)及該接地選擇區（GSR)之該主動區内的該 半導體基板3 0 0的表面部份，以形成離子佈植區（未圖示） ’接著去除該罩幕光阻PR3。上述之離子佈植區可以包含 一個淺離子佈植區以作為選擇閘電晶體之臨界電壓的調整 及一個深離子佈植區以形成該選擇閘電晶體之一個抵穿禁 止區（punch-through stop)。上述之佈植摻雜質係硼或硼 氟（boron-fluoride)雜質。 圖四D顯示一個回蝕第二覆蓋導電層314b形成於該串 選擇區（SSR)的每一個之内及該接地選擇區（GSR)的每一個 之内’然後一對第一側邊牆介電塾層3 1 5 a係形成於鄰近第 一平面化氧化物層313a的側邊牆之上且置於該串選擇區（ SSR)的每一個及該接地選擇區（GSR)的每一個之該回餘第 二覆蓋導電層314 b的一部份表面之上，以定義一對串選擇 線（SSL) 3 14c於該串選擇區（SSR)的每一個之内及一對接地 選擇線（GSL) 3 14c於該接地選擇區（GSR)的每一個之内。上 述之回蝕第二覆蓋導電層314b係由矽化鎢（WSi 2)或鶴（w) 所組成且利用LPCVD法或濺鍍法來堆積，係先堆積一個厚 第二覆蓋導電層314於該串選擇區（SSR)及該接地選擇區（ G S R)的每一個空隙，然後利用c Μ P法將所堆積之厚第二覆 蓋導電層314加予平面化並以該成形第二罩幕介電層3UaPage 16 569395 V. Description of the invention (12) The shaped second mask dielectric layer 311a of the f-selected (GSR) region, the shaped first covering conductive layer 310a, the planarized third conductive layer 309b, and the shaping The inter-gate dielectric layer 3 0 8 a, and then the first conductive type dopant is implanted in the string selection across the formed first conductive layer 30 2 b and the penetrating dielectric layer 301 a in an automatic alignment manner. Area (SSR) and the ground selection area (GSR) in the active area of the semiconductor substrate 300 to form an ion implantation area (not shown). Then the mask photoresist PR3 is removed. The above-mentioned ion implantation region may include a shallow ion implantation region as a threshold voltage adjustment of the selective gate transistor and a deep ion implantation region to form a punch-through stop region of the selective gate transistor. ). The above-mentioned implants are doped with boron or boron-fluoride impurities. FIG. 4D shows that an etch-back second covering conductive layer 314b is formed within each of the string selection region (SSR) and each of the ground selection region (GSR). Then a pair of first side walls The electrode layer 3 1 5 a is formed on a side wall adjacent to the first planarized oxide layer 313 a and is disposed on each of the string selection region (SSR) and each of the ground selection region (GSR). The remaining second covering conductive layer 314 b is over a part of the surface to define a pair of string selection lines (SSL) 3 14c within each of the string selection area (SSR) and a pair of ground selection lines ( GSL) 3 14c is within each of the ground selection regions (GSR). The above-mentioned etch-back second cover conductive layer 314b is composed of tungsten silicide (WSi 2) or crane (w) and is deposited by LPCVD method or sputtering method. A thick second cover conductive layer 314 is first deposited on the string. SSR and each gap of the ground selection region (GSR), and then use the CMP method to planarize the thick second overlay conductive layer 314 and use the formed second mask dielectric layer 3Ua
第17頁 569395 五、發明說明（13) ~ '' 一個磨平停止層以形成平面化第二覆蓋導電層314a， 蝕忒平面化第二覆蓋導電層314a至等於該成形第一 ^導電層310a的頂部表面水平。上述之第二側邊牆介電 曰31 5a係由氮化矽所組成且利用lPCVD法來堆積，係先 個第二介電層315於一個所形成的結構表面之上再 所堆積之第二介電層31 5的一個厚度。 一圖四E顯不進行一個非嚴謹罩幕光阻步驟（pR4)以形成 ，罩幕光阻PR4於該細胞串的每一個之上及鄰近第二側 對=^電墊層3 1 5a的一部份表面之上，然後先去除介於該 u —側邊牆介電墊層315a之間的該回蝕第二覆蓋導電層 接著非等向性地去除該延伸第二導電層3〇5c和該薄 ，，牆導電墊層3 0 7a及蝕刻該成形第一導電層3〇2b至該第 /一突出場氧化物層304b的頂部表面水平（參考圖三E)，然 ^回蝕該第一犬出場氧化物層3〇41}至該穿透介電層“I a的 T 4表面水平以形成第二突出場氧化物層3〇4c，接著去除 ^一留的成形第一導電層3 〇 2b ;然後，以自動對準的分式進 一 β子佈植以形成複數淡摻雜共洩擴散區3 1 β &位於該串選 擇區、（SSR)的每一個之該對第二側邊牆介電墊層315&之間 的該半$體基板300的表面及形成複數淡摻雜共源擴散區 3 1 6a於4接地選擇區（gsR)的每一個之該對第二側邊牆介 電塾層315a之間的半導體基板3〇〇的表面。佈植之摻雜質 係j或砷，而佈植之劑量係介於1 0 13/平方公分和5x 1 〇 14 /平方公分之間。由圖四E可以清楚地看到，該串/接地 選擇線（SSL) 31 5a的寬度係由該第二側邊牆介電墊層315aPage 17 569395 V. Description of the invention (13) ~ '' A flat stop layer is formed to form a planarized second cover conductive layer 314a, and the second planar cover conductive layer 314a is etched to be equal to the formed first conductive layer 310a. The top surface is horizontal. The above-mentioned second side wall dielectric 31a is composed of silicon nitride and is deposited by the lPCVD method. It is a second dielectric layer 315 which is deposited on the surface of a formed structure and then is deposited. A thickness of the dielectric layer 315. One picture four E shows that a non-rigorous mask photoresist step (pR4) is performed to form, and the mask photoresist PR4 is on each of the cell strings and adjacent to the second side pair = ^ electrically cushion layer 3 1 5a On a part of the surface, and then the etched back second conductive layer between the u-side wall dielectric pad layer 315a is removed first, and then the extended second conductive layer 30c is removed anisotropically And the thin layer, the wall conductive pad layer 307a and the top surface level of the first conductive layer 302b etched to form the first / first protruding field oxide layer 304b (see FIG. 3E), and then etch back the The first dog field oxide layer 3041} to the T 4 surface level of the penetrating dielectric layer "Ia" to form a second protruding field oxide layer 304c, and then the remaining formed first conductive layer is removed 3 〇2b; Then, a β sub-planting is performed with an auto-aligned fraction to form a plurality of lightly doped co-leakage diffusion regions 3 1 β & The pair of second in each of the string selection regions (SSR) The surface of the half-body substrate 300 between the sidewall spacers 315 & and each of the plurality of lightly doped common source diffusion regions 3 1 6a to 4 ground selection region (gsR) The surface of the semiconductor substrate 300 between the pair of second sidewall spacers 315a. The implanted dopant is j or arsenic, and the implanted dose is between 10 13 / cm 2. And 5x 1 0 14 / cm 2. As can be clearly seen from Figure 4E, the width of the string / ground selection line (SSL) 31 5a is determined by the second side wall dielectric pad 315a.
第18頁 569395 五、發明說明（14) 的墊層寬度來定義，而該選擇閘層302c、305e、307c係一 個單邊斜角漂浮閘結構具有一個較大的通道長度及一個較 窄的串/接地選擇線31 4c (SSL/ GSL)。 圖四F顯示該罩幕光阻PR4被去除，然後一對第三侧邊 牆介電墊層3 1 7a係形成於該對第二側邊牆介電墊層3 1 7a、 該串/接地選擇線314c、及該選擇閘層3 0 2c、3 0 5e、3 0 7c 所組成的側邊牆之上且置於該共源/洩區（CSR) / (CDR) 的每一個之由該穿透介電層301 a及該第二突出場氧化物層 3〇4c所交變地組成之一個平坦表面的一部份之上；然後，Page 18 569395 V. The description of the invention (14) cushion layer width, and the selection gate layer 302c, 305e, 307c is a single-sided oblique angle floating gate structure with a larger channel length and a narrower string / Ground selection line 31 4c (SSL / GSL). Figure 4F shows that the mask photoresist PR4 is removed, and then a pair of third side wall dielectric pads 3 1 7a are formed on the pair of second side wall dielectric pads 3 1 7a, the string / ground Each of the selection line 314c and the selection gate layer 3 0 2c, 3 0 5e, 3 0 7c is placed on the side wall of the common source / drain area (CSR) / (CDR), The dielectric layer 301 a and a portion of a flat surface alternately composed of the second protruding field oxide layer 304 c; and
以自動對準的方式跨過該穿透介電層3〇1&佈植該第二導電 型的一個高劑量之摻雜質於該主動區的半導體基板3〇〇之 表面’以形成一個高摻雜共源/洩擴散區3 1 6 b於該淡摻雜 ^源/沒擴散區3 1 6 a的每一個之内；接著，利用非等向乾 $餘刻法或稀釋氫氟酸的泡浸法去除位於該對第三側邊牆 ^ 層31 7a之間的該穿透介電層30 la並同時蝕刻該第二 = 场氧化物層3〇4c，以形成第三突出場氧化物層3〇4d; 牆介 個平面化第四導電層31 8a係形成於該對第三側邊 3回^構墊層31 ^之間的空隙。上述之第三側邊牆介電墊層 積—&個Ϊ ^氧化碎所組成且利用LPCVD法來堆積，係先堆 蝕所堆藉二介電層317於一個所形成的結構表面之上再回 四導電第二介電層317的一個厚度。上述之平面化第 積，係^ &係由摻雜複晶矽所組成且利用LPCVD法來堆 甸邊牌八Ϊ積一個厚第四導電層318以填滿位於該對第三 ° 墊層3 1 7a之間的每一個空隙再利用CMP法將所A high dose of a dopant of the second conductivity type implanted on the surface of the semiconductor substrate 300 of the active region is implanted across the penetrating dielectric layer 3101 in an automatic alignment manner to form a high The doped common source / drain diffusion region 3 1 6 b is within each of the lightly doped source / non-diffusion region 3 1 6 a; then, using an anisotropic dry etching method or diluting the hydrofluoric acid The bubble immersion method removes the penetrating dielectric layer 30 la between the pair of third side wall ^ layers 31 7a and simultaneously etches the second = field oxide layer 304c to form a third protruding field oxide Layer 304d; the wall interposed between the planarized fourth conductive layers 31 8a is formed in the gap between the pair of third sides 3 times the structure pad layer 31 ^. The above-mentioned third side wall dielectric pad layer is composed of > ^ oxidized fragments and stacked using LPCVD method, which is firstly deposited by stacking two dielectric layers 317 on a formed structure surface. A thickness of the four-conducting second dielectric layer 317 is returned again. The above-mentioned planarization product is composed of doped polycrystalline silicon and used LPCVD method to stack a thick fourth conductive layer 318 to fill the third layer of cushion layer. Each gap between 3 1 7a is reused by the CMP method.
第19頁 569395 五、發明說明（15) 堆積之厚第四導電層318加予平面化並以該成形第二罩幕 層3 1 1 a作為一個磨平停止層。上述之高摻雜共源/洩擴散 區3 1 6b所佈植的摻雜質係砷或磷，而所佈植的劑量係介於 1 0 15/平方公分至5x 1 0 15/平方公分之間。這裡值得一提 的是，該平面化第四導電層3 18a係分別置於該共源區（CSR )的每一個之由該高摻雜共源擴散區316b及該第三突出場 氧化物層3 0 4d所交變地組成的第一平坦床之上及置於該共 洩區（CDR)的每一個之由該高摻雜共洩擴散區31 6b及該第 三突出場氧化物層304d所交變地組成的一個第二平坦床之 上。 圖四G顯示位於該共源/洩區的每一個之該平面化第 四導電層3 1 8 a係選擇性地回蝕至一個預定的厚度以形成回 #第四導電層318b，然後以自動對準的方式佈植該第二導 電型的一個高劑量之摻雜質於該回蝕第四導電層3 18b中； 接著，一個平面化第三覆蓋導電層3丨9a形成於該對第三側 邊牆介電墊層3 1 7 a之間；然後，利用一個非嚴謹的罩幕光 阻PR5(未圖示）選擇性地回蝕位於該共源區（CSR)之該平面 化第三覆蓋導電層3 1 9 a至另一個預定的深度以形成共源導 電管線319b/ 318b，其中該罩幕光阻PR5係置於該共洩區 (CDR)之上；然後去除該罩幕光阻pR5;接著，一個第二平 面化覆蓋氧化層32 0a係形成於該共源導電管線31 9b/ 318b 的每一個之上。上述之平面化第三覆蓋導電層319 a係由矽 化鎢（WSi 2 )或鎢（W)所組成且利用LpCVD法或濺鍍法來堆積 ’係先堆積一個厚第三覆蓋導電層3丨9來填滿位於該共源Page 19 569395 V. Description of the invention (15) The thick fourth conductive layer 318 is flattened and the formed second cover layer 3 1 1 a is used as a smoothing stop layer. The dopant implanted in the above-mentioned highly doped common source / diffusion diffusion region 3 1 6b is arsenic or phosphorus, and the implanted dose ranges from 1015 / cm2 to 5x1015 / cm2. between. It is worth mentioning here that the planarized fourth conductive layer 318a is placed in each of the common source regions (CSR) by the highly doped common source diffusion region 316b and the third protruding field oxide layer. Above the first flat bed composed of 3 0 4d alternately and placed on each of the co-drained regions (CDR), the highly doped co-drained diffusion region 31 6b and the third protruding field oxide layer 304d Alternately composed on a second flat bed. FIG. 4G shows that the planarized fourth conductive layer 3 1 8 a located in each of the common source / drain regions is selectively etched back to a predetermined thickness to form a fourth conductive layer 318 b, and then automatically A high-dose dopant of the second conductivity type is implanted in the aligning fourth conductive layer 3 18b in an aligned manner; then, a planarized third covering conductive layer 3 9a is formed in the pair of third Side wall dielectric cushion layer 3 1 7 a; then, using a non-rigid mask PR5 (not shown) to selectively etch back the planarized third located in the common source region (CSR) Cover the conductive layer 3 1 9 a to another predetermined depth to form a common source conductive pipeline 319b / 318b, wherein the mask photoresist PR5 is placed on the common leakage area (CDR); then the mask photoresist is removed pR5; Next, a second planarized cover oxide layer 32 0a is formed on each of the common source conductive lines 31 9b / 318b. The above-mentioned planarized third cover conductive layer 319 a is composed of tungsten silicide (WSi 2) or tungsten (W) and is deposited by LpCVD method or sputtering method. First, a thick third cover conductive layer is deposited. 3 丨 9 To fill the common source
第20頁 569395 五、發明說明（16) /洩區的每一個空隙再利用CMP法將所堆積之厚第三覆蓋 導電層3 1 9加予平面化並以該成形第二罩幕介電層311&作 為一個磨平停止層。上述之第二平面化覆蓋氧化層32 0a係 由二氧化矽、磷玻璃、或硼磷玻璃所組成且利用LPCVD法 、HDPCVD法、或PECVD法來堆積’係先堆積一個厚氧化層 320以填滿該共源區的每一個空隙再利用CMP法將所堆積之 厚氧化層32 0加予平面化並以該成形第二罩幕介電層311a 作為一個磨平停止層。 圖四Η顯示一個金屬層321係形成於圖四G所示之一個 形成的結構表面之上並與平面化第三覆蓋導電層319a置於 該回鍅第四導電層318b同時藉由一個罩幕光阻（pR6)(未圖 示）加予成形，以形成複數金屬位元線32 1 a(BL)與平面化 共泡導電島319c/ 318 c積體化連結。上述之金屬層3 2 1至 少包含一個鋁（A1 )或銅（Cu)層置於一個障礙金屬（barrier metal)之上所組成。上述之罩幕光阻步驟pR6至少包含由 複數罩幕光阻PR6所成形之複數第三罩幕介電層322a對準 於該複數主動區（AA)之上及一個第四側邊牆介電塾層323a 形成於該複數第三罩幕介電層3 2 2 a的每一個側邊牆之上來 降低誤對準（misalignment)，如圖五b至圖五E所示。 由圖三A至圖三F及圖四A至圖四η，本發明之無接點非 和型快閃記憶陣列僅需三個嚴謹罩幕光阻步驟來製造，而 先前技術至少需六個嚴謹的罩幕光阻步驟。這裡值得一提 的是’在未堆積金屬層321之前，該成形第二罩幕介電層 3 1 1 a及該第二側邊牆介電墊層3 1 5 a可以利用高溫磷酸加予Page 20 569395 V. Description of the invention (16) / Each void in the leakage area is then planarized by using the CMP method to deposit the thick third covering conductive layer 3 1 9 and forming the second mask dielectric layer in this way. 311 & acts as a smooth stop layer. The above-mentioned second planarized cover oxide layer 320a is composed of silicon dioxide, phosphor glass, or borophospho glass and is deposited by LPCVD method, HDPCVD method, or PECVD method. First, a thick oxide layer 320 is deposited to fill Each gap that fills the common source area is planarized by the CMP method, and the formed second mask dielectric layer 311a is used as a flattening stop layer. FIG. 4A shows that a metal layer 321 is formed on the structural surface formed by the one shown in FIG. 4G and is placed with the planarized third covering conductive layer 319a on the fourth conductive layer 318b at the same time through a mask. A photoresist (pR6) (not shown) is preformed to form a complex metal bit line 32 1 a (BL) and a planar co-foam conductive island 319c / 318 c integrated connection. The above-mentioned metal layer 3 2 1 is composed of at least one aluminum (A1) or copper (Cu) layer placed on a barrier metal. The above mask photoresist step pR6 includes at least a plurality of third mask dielectric layers 322a formed by the multiple mask photoresist PR6 aligned on the multiple active area (AA) and a fourth side wall dielectric. The ytterbium layer 323a is formed on each side wall of the plurality of third mask dielectric layers 3 2 2 a to reduce misalignment, as shown in FIG. 5b to FIG. 5E. From FIG. 3A to FIG. 3F and FIG. 4A to FIG. 4η, the contactless non-harmonic flash memory array of the present invention requires only three rigorous mask photoresist steps to be manufactured, compared with at least six in the prior art. Rigorous mask photoresist steps. It is worth mentioning here that before the metal layer 321 is not stacked, the formed second cover dielectric layer 3 1 1 a and the second side wall dielectric cushion layer 3 1 5 a can be added with high temperature phosphoric acid.
第21頁 569395 五、發明說明（17) 選擇性地去除，再回填平面化第三覆蓋氧化物層（未圖示） ，以降低位元線3 2 1 a與字線、串選擇線間的電容。 現請參見圖五A，其中揭示本發明之一種無接點非和 型快閃記憶陣列的一個簡要頂視圖，其中一條A-A，線所標 示之剖面圖係如圖四Η所示；沿著一條B - B，線的一個剖面 圖顯示於圖五Β中；沿著一條C-C’線的一個剖面圖係顯示 於圖五C中；沿著一條D-D’線的一個剖面圖係顯示於圖五d 中；以及沿著一條Ε-Ε’線的一個剖面圖係顯示於圖五ε中 〇 圖五Α顯示該主動區（ΑΑ)及該淺凹槽隔離區（sti )係交 變地形成；複數字線（W L)係與該主動區（A A)互為垂直，其 中上述之複數字線（WL)的母一個至》包含《—個複合控制閘 層310a/ 3 0 9b形成於複數自動對準漂浮閘層302b、30 5d、 3 0 7 b之上方，如圖五D所示，而該複數自動對準漂浮閘層 3 0 2b、3 0 5d、3 0 7b的每一個具有一個斜角漂浮閘結構如虛 線所標示；一對串選擇線（SSL) 314c及一對接地選擇線（ G S L ) 3 1 4 c係位於細胞元串的每一個側邊部份，其中上述之 偶對串/接地選擇線3 1 4 c至少包含複數單邊斜角漂浮間 302c、305e、307c如圖五C所不；複數平面化共泡導電島 3 1 9 c/ 3 1 8 c係形成於一對第三側邊牆介電塾層3 1 7 a之間且 至少置於共茂擴散區316b/ 31 6a之上係與複數金屬位元線 321a同時成形’其中上述之複數金屬位元線（BL)321a的每 一個係由一個第三罩幕介電層322—準於該主動區（AA)之 上及一個第四側邊牆介電墊層323a形成於該第三罩幕介電Page 21 569395 V. Description of the invention (17) Selectively remove and then back-fill planarize the third covering oxide layer (not shown) to reduce the capacitance between the bit line 3 2 1 a and the word line and string selection line. . Please refer to FIG. 5A, which discloses a brief top view of a non-contact non-NAND flash memory array of the present invention. A cross-sectional view indicated by an AA line is shown in FIG. 4; B-B, a cross-sectional view of the line is shown in Fig. 5B; a cross-sectional view along a line CC-C 'is shown in Fig. 5C; a cross-sectional view along a line D-D' is shown In Figure 5d; and a cross-sectional view along an Ε-Ε 'line is shown in Figure 5ε. Figure 5A shows that the active region (AA) and the shallow groove isolation region (sti) are alternated. The ground is formed; the complex digital line (WL) is perpendicular to the active area (AA), wherein the parent of the complex digital line (WL) mentioned above includes "a composite control gate layer 310a / 3 0 9b formed in The plurality of automatic alignments are above the floating gates 302b, 30 5d, and 3 0 7 b, as shown in FIG. 5D, and each of the plurality of automatic alignments is located at each of the floating gates 3 0 2b, 3 5 5d, and 3 0 7b. A beveled floating gate structure is indicated by the dotted line; a pair of string selection lines (SSL) 314c and a pair of ground selection lines (GSL) 3 1 4 c For each side of the cell string, the above-mentioned pair of pairs / ground selection lines 3 1 4 c at least include a plurality of single-sided oblique floating chambers 302c, 305e, and 307c as shown in Figure 5C; The conductive island 3 1 9 c / 3 1 8 c is formed between a pair of third side wall dielectric plutonium layers 3 1 7 a and is placed at least on the common metallocene diffusion region 316b / 31 6a. The bit lines 321a are simultaneously formed. 'Each of the above-mentioned plural metal bit lines (BL) 321a is formed by a third mask dielectric layer 322—above the active area (AA) and a fourth side edge. A wall dielectric layer 323a is formed on the third mask dielectric
第22頁 569395 五、發明說明（18) 層322a的每一個側邊牆之上來成形，如圖五b所示；以及 一個共源導電管線3 1 9b/ 3 1 8b係形成於該對第三側邊牆介 電墊層317a之間的一個第一平坦床之上，其中上述之第一 平坦床係交變地由一個共源擴散區3丨6b/ 3丨6a及一個第三 突出場氧化物層3 0 4 d所交變地組成，如圖五£所示。 圖五B顯示沿著該平面化共洩導電島3丨9c/ 3 1 8c如圖 五A的一條B - B，線所標示之一個剖面圖，其中上述之金屬 位元線3 2 1 a的每一個係與該平面化共洩導電島3 1 9 c/ 3 1 8 c 積體化連結且藉由一個第三罩幕介電層323a對準於該主動 區（AA)之上及一個第四側邊牆介電墊層323a形成於該第三 罩幕介電層323a的每一個側邊牆之上來降低誤對準；該平 面化共洩導電島3 1 9c/ 3 1 8c至少形成於具有一個高摻雜共 洩擴散區3 1 6b形成於一個淡掺雜共洩擴散區3 1 6a之内所組 成的一個共洩擴散區3 1 6 b/ 3 1 6 a之上；以及一個第二平坦 床係交變地由一個高摻雜共洩擴散區3 1 6 b及一個第三突出 場氧化物層304d所組成。 圖五C顯示沿著一個串選擇線（S S L ) 3 1 4 c如圖五A的一 條B-B’線所標示之一個剖面圖，其中上述之_選擇線（SSl )3 14c係置於由一個自動對準漂浮閘層3 0 2c、3 0 5e、3 0 7及 一個第一突出場氧化物層3 0 4b所交變地組成的一個表面之 上；一個第二側邊牆介電墊層 3 1 5a係形成於該串選擇線 3 14c之上來定義該串選擇線（SSL) 3 14c的寬度；該金屬位 元線3 2 1 a係形成於該第二側邊牆介電塾層315 a之上且由上 述之罩幕光阻步驟 （PR6)來成形；以及該_選擇閘302c的Page 22 569395 V. Description of the invention (18) Each side wall of the layer 322a is formed, as shown in Fig. 5b; and a common source conductive pipeline 3 1 9b / 3 1 8b is formed in the third pair Above a first flat bed between the side wall dielectric pads 317a, wherein the above first flat bed is alternately oxidized by a common source diffusion region 3 丨 6b / 3 丨 6a and a third protruding field The alternating layer composition of the physical layer 3 0 4 d is shown in Fig. 5. Figure 5B shows a cross-sectional view along the plane of the common leakage conductive island 3 丨 9c / 3 1 8c as shown by a line B-B in Figure 5A, in which the metal bit line 3 2 1 a Each of them is integrated with the planarized common leakage conductive island 3 1 9 c / 3 1 8 c and is aligned above the active area (AA) and a first through a third mask dielectric layer 323 a. Four side wall dielectric pads 323a are formed on each side wall of the third mask dielectric layer 323a to reduce misalignment; the planarized common leakage conductive island 3 1 9c / 3 1 8c is formed at least on Having a highly doped co-drained diffusion region 3 1 6b formed on a co-drained diffusion region 3 1 6 b / 3 1 6 a formed within a lightly doped co-drained diffusion region 3 1 6a; and a first The two flat beds alternately consist of a highly doped co-drained diffusion region 3 1 6 b and a third protruding field oxide layer 304d. FIG. 5C shows a cross-section view along a string selection line (SSL) 3 1 4 c as indicated by a BB ′ line in FIG. 5A, in which the above-mentioned _selection line (SSl) 3 14c is placed by An automatically aligned floating gate layer 3 2c, 3 5e, 3 07 and a first protruding field oxide layer 3 0 4b alternately on a surface; a second side wall dielectric pad The layer 3 1 5a is formed on the string selection line 3 14c to define the width of the string selection line (SSL) 3 14c; the metal bit line 3 2 1 a is formed on the second sidewall dielectric layer. 315 a and formed by the above-mentioned mask photoresist step (PR6); and the _select gate 302c
第23頁 569395 五、發明說明（19) 每一個係形成於鄰近第一突出場氧化物層3 〇 4b之間的一個 穿透介電層3 0 1 b之上。這裡可以清楚地看到，該串選擇線 3 1 4c係與金氧半場效電晶體閘積體化連結，而異於先前技 術之與快閃記憶元件連結。 圖五D顯示沿著一條字線（W L )如圖五A所示之一條D - D， 線所標示之一個剖面圖，其中具有高耦合比之一個自動對 準漂浮閘結構係形成於如圖三F所示的該淺凹槽隔離結構 之上；一個成形第二罩幕介電層3 1 1 a係形成於該複合控制 閘層310a/ 3 0 9b之上；以及該金屬位元線32 la係形成於該 成形第二罩幕介電層311 a之上且藉由上述之罩幕光阻步驟 (PR6)來成形。 圖五E顯示沿著一個共源導電管線3 1 9b/ 3 1 8b如圖五A 所示之一條E-E’線所標示之一個剖面圖，其中上述之共源 導電管線3 1 9b/ 3 1 8b係形成於由一個第三突出場氧化物層 3 04d及一個共源擴散區316b/ 31 6a所交變地組成的一個第 一平坦床之上，而該共源擴散區3 1 6 b/ 3 1 6 a至少包含一個 高摻雜共源擴散區3 1 6b形成於一個淡摻雜共源擴散區3 1 6a 之内所組成；一個第二平面化覆蓋氧化層32 0a係形成於該 共源導電管線3 1 9 b/ 3 1 8 b之上；相似地，該金屬位元線係 形成於該第二平面化覆蓋氧化物層320 a之上且經由上述之 罩幕光阻步驟（PR6 )來成形。這裡可以清楚地看到，該共 源導電管線3 1 9b/ 3 1 8b比先前技術之埋層擴散線具有較低 的管線電阻及相對於該半導體基板3 0 0間較低的管線電容Page 23 569395 V. Description of the invention (19) Each system is formed on a penetrating dielectric layer 3 0 1 b adjacent to the first protruding field oxide layer 3 04 b. It can be clearly seen here that the string selection line 3 1 4c is connected to the metal-oxide half-field-effect transistor gate integration, which is different from the connection to the flash memory element in the prior art. FIG. 5D shows a cross-section view along a word line (WL) as shown in FIG. 5A, one of the D-D, lines, in which an automatically aligned floating gate structure with a high coupling ratio is formed as shown in FIG. Above the shallow groove isolation structure shown by 3F; a formed second mask dielectric layer 3 1 1 a is formed on the composite control gate layer 310 a / 3 0 9b; and the metal bit line 32 The la series is formed on the forming second mask dielectric layer 311a and is formed by the mask photoresist step (PR6) described above. FIG. 5E shows a cross-section view along an E-E 'line shown in FIG. 5A along a common source conductive pipeline 3 1 9b / 3 1 8b, where the above-mentioned common source conductive pipeline 3 1 9b / 3 1 8b is formed on a first flat bed consisting of a third protruding field oxide layer 3 04d and a common source diffusion region 316b / 31 6a, and the common source diffusion region 3 1 6 b / 3 1 6 a includes at least one highly doped common source diffusion region 3 1 6b formed in a lightly doped common source diffusion region 3 1 6a; a second planarized cover oxide layer 32 0a is formed in the The common source conductive pipeline 3 1 9 b / 3 1 8 b; similarly, the metal bit line is formed on the second planarized cover oxide layer 320 a and passes through the above-mentioned mask photoresist step ( PR6). It can be clearly seen here that the common conductive pipeline 3 1 9b / 3 1 8b has a lower pipeline resistance than the buried diffusion line of the prior art and a lower pipeline capacitance of 300 compared to the semiconductor substrate.
第24頁 569395Page 569395
第25頁 569395 圖式簡單說明 圖一 A和圖一 B顯示一個非和型快閃記憶陣列中之一個 傳統疊堆閘快閃記憶細胞元結構及其寫入和擦洗的簡要圖 ，其中圖一 A顯示一個寫入狀態而圖一 B顯示一個擦洗狀態 〇 圖二A和圖二B顯示一個非和型快閃記憶陣列之本發明 的一個疊堆閘快閃記憶細胞元結構及其寫入和擦洗的簡要 圖，其中圖二A顯示一個寫入狀態而圖二B顯示一個擦洗狀 態。 圖三A至圖三F揭示製造本發明之一種非和型快閃記憶 陣列之具有一種自動對準漂浮閘結構之一種淺凹槽隔離結 構的製程步驟及其剖面圖。 圖四A至圖四Η揭示接續圖三F製造本發明之一種非和 型快閃記憶陣列之製程步驟及其剖面圖。 圖五Α至圖五Ε揭示本發明之一個簡要頂部佈建圖及其 剖面圖，其中圖五A揭示圖四Η的一個簡要頂視圖；圖五B 揭示圖五Α所示之沿著一條Β - Β ’線的一個剖面圖；圖五C揭 示圖五A所示之沿著一條C - C ’線的一個剖面圖；圖五D揭示 圖五A所示之沿著一條D - D ’線的一個剖面圖；以及圖五E揭 示圖五A所示之沿著一條E - E ’線的一個剖面圖。 圖號對照說明： 300 半導體基板 301b穿透介電層 302b斜角第一導電層 302c單邊斜角第一導電層Page 25 569395 Brief Description of the Drawings Figures A and B show a schematic diagram of a traditional stacked gate flash memory cell structure and its writing and scrubbing in a NAND flash memory array, of which Figure 1 A shows a writing state and FIG. 1B shows a scrubbing state. FIG. 2A and FIG. 2B show a non-and-type flash memory array of a stack gate flash memory cell structure of the present invention and its writing and A brief diagram of scrubbing, wherein FIG. 2A shows a writing state and FIG. 2B shows a scrubbing state. FIG. 3A to FIG. 3F show the manufacturing steps and cross-sectional views of a shallow groove isolation structure with an automatic alignment floating gate structure for manufacturing a non-harmonic flash memory array of the present invention. FIG. 4A to FIG. 4B show the process steps and cross-sectional views of the NAND flash memory array of the present invention following FIG. 3F. FIGS. 5A to 5E disclose a brief top layout diagram and a sectional view of the present invention, wherein FIG. 5A reveals a brief top view of FIG. 4A; FIG. 5B reveals a line B along FIG. 5A -A cross-sectional view of the line Β '; Figure 5C reveals a cross-section view along a line C-C' shown in Figure 5A; Figure 5D illustrates a line D-D 'shown in Figure 5A A cross-sectional view of FIG. 5; and FIG. 5E discloses a cross-sectional view along an E-E 'line shown in FIG. 5A. Comparative illustration of drawing numbers: 300 semiconductor substrate 301b penetrates dielectric layer 302b beveled first conductive layer 302c unilateral beveled first conductive layer
第26頁 569395 圖式簡單說明 3 0 3a第一罩幕介電層 3 0 4a平面化場氧化物層 3 0 4b第一突出場氧化物層 3 0 4c第二突出場氧化物層 3 04d第三突出場氧化物層 3 0 5a平面化第二導電層 305b回蝕平面化第二導電層305c延伸第二導電層 3 0 6 a第一側邊牆介電墊層 3 0 7 a薄側邊牆導電墊層 3 0 8 a成形閘間介電層 3 0 9 a平面化第三導電層 309b成形平面化第三導電層310a成形第一覆蓋導電層 311 第二罩幕介電層 311a成形第二罩幕介電層 3 1 2 a連線共源/洩擴散區 3 1 3 a第一平面化覆蓋氧化層 314b回蝕第二覆蓋導電層 314c串/接地選擇線 3 1 5a第二側邊牆介電墊層 3 1 6a淡摻雜共源/洩擴散區 3 1 6b高摻雜共源/洩擴散區3 1 7a第三側邊牆介電墊層 318a平面化第四導電層 318b回蝕平面化第四導電層 318c回蝕平面化第四導電島319a平面化第三覆蓋導電層 319b回蝕第三覆蓋導電層 319c平面化第三覆蓋導電島 320a第二平面化覆蓋氧化層321a金屬位元線 322a成形第三罩幕介電層 323a第四側邊牆介電墊層Page 26 569395 Brief description of the diagram 3 0 3a First mask dielectric layer 3 0 4a Planar field oxide layer 3 0 4b First protruding field oxide layer 3 0 4c Second protruding field oxide layer 3 04d Three protruding field oxide layer 3 0 5a planarized second conductive layer 305b etched back planarized second conductive layer 305c extended second conductive layer 3 0 6 a first side wall dielectric pad layer 3 0 7 a thin side Wall conductive pad layer 3 0 8 a forming inter-gate dielectric layer 3 0 9 a planarization third conductive layer 309 b forming planarization third conductive layer 310 a forming first covering conductive layer 311 second covering dielectric layer 311 a forming first Second cover dielectric layer 3 1 2 a Connection common source / drain diffusion area 3 1 3 a First planarized cover oxide layer 314b Etching back second cover conductive layer 314c String / ground selection line 3 1 5a Second side Wall dielectric pad 3 1 6a lightly doped common source / drain diffusion region 3 1 6b highly doped common source / drain diffusion region 3 1 7a third side wall dielectric pad layer 318a planarization fourth conductive layer 318b back Etch planarization fourth conductive layer 318c etch back planarization fourth conductive island 319a planarization third covering conductive layer 319b etch back third covering conductive layer 319c planarization third covering conductive 320a 321a covering second planarized metal bit line 322a forming the third oxide layer a dielectric layer mask fourth side wall 323a of the dielectric underlayer
第27頁Page 27
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| US7791199B2 (en) | 2006-11-22 | 2010-09-07 | Tessera, Inc. | Packaged semiconductor chips |
| US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
| EP2135280A2 (en) | 2007-03-05 | 2009-12-23 | Tessera, Inc. | Chips having rear contacts connected by through vias to front contacts |
| JP2010535427A (en) | 2007-07-31 | 2010-11-18 | テッセラ，インコーポレイテッド | Semiconductor packaging process using through silicon vias |
| US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
| US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
| US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
| US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
| US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
| KR101059490B1 (en) | 2010-11-15 | 2011-08-25 | 테세라 리써치 엘엘씨 | Conductive pads defined by embedded traces |
| US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
| US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
| US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
| US8610264B2 (en) | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
-
2002
- 2002-10-30 TW TW91132230A patent/TW569395B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW200406884A (en) | 2004-05-01 |
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