CN107680967B - Power semiconductor chip and forming method thereof - Google Patents
Power semiconductor chip and forming method thereof Download PDFInfo
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- CN107680967B CN107680967B CN201711031103.4A CN201711031103A CN107680967B CN 107680967 B CN107680967 B CN 107680967B CN 201711031103 A CN201711031103 A CN 201711031103A CN 107680967 B CN107680967 B CN 107680967B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
A power semiconductor chip and a method of forming the same, wherein the power semiconductor chip includes: a ring-shaped junction termination region located at an edge of the power semiconductor chip; a cell region surrounded by the junction termination region, wherein a cell array is formed in the cell region, and the cells are power transistors; the cell area comprises more than two sub-areas, one sub-area is a central sub-area and is positioned at the center of the cell area, and the other sub-areas are annular and are sequentially arranged around the central sub-area; the cell channel lengths in the same sub-region are the same, and the cell channel length in the center sub-region is smaller than the cell channel lengths in the other sub-regions. The heat distribution is uniform in the working process of the power semiconductor chip, and the reliability is higher.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a power semiconductor chip and a method for forming the same.
Background
Power semiconductor devices can be classified into uncontrollable devices, semi-controllable devices, and fully controllable devices. The uncontrollable devices comprise various diodes, the semi-controllable devices comprise Silicon Controlled Rectifiers (SCR) and the like, and the fully-controllable devices comprise power metal oxide field effect transistors, insulated Gate Bipolar Transistors (IGBT), bipolar Junction Transistors (BJT) and the like.
The fully-controlled power device generally works in a switching state, is in an ohmic region after being conducted, and has extremely low voltage drop or on-resistance; the power device is in a cut-off area after being cut off, and only has little electric leakage, so that the loss generated on the power device is small when the power device is used as a switch, and the device can keep higher reliability in the working process.
However, in some applications, such as solid state relays, electronic loads, and the like, it is desirable to operate the power discrete devices in the saturation region for a period of time to maintain the characteristics, and very large losses are generated in the devices. The reliability of the conventional power device at this time is drastically reduced.
Therefore, a special fully-controlled power discrete device is designed to improve the reliability of the power discrete device in the saturation region aiming at the application field requiring the power device to work in the saturation region.
Disclosure of Invention
The invention aims to provide a power semiconductor chip and a forming method thereof, which can improve the reliability of the power semiconductor chip.
In order to solve the above-described problems, the present invention provides a power semiconductor chip including: a ring-shaped junction termination region located at an edge of the power semiconductor chip; a cell region surrounded by the junction termination region, wherein a cell array is formed in the cell region, and the cells are power transistors; the cell area comprises more than two sub-areas, one sub-area is a central sub-area and is positioned at the center of the cell area, and the other sub-areas are annular and are sequentially arranged around the central sub-area; the cell channel lengths in the same sub-region are the same, and the cell channel length in the center sub-region is smaller than the cell channel lengths in the other sub-regions.
Alternatively, the cell channel lengths in the different sub-regions are sequentially incremented outwardly from the central sub-region.
Optionally, the cellular region includes a first sub-region, a second sub-region surrounding the first sub-region, a third sub-region surrounding the second sub-region, and a fourth sub-region surrounding the third sub-region; the cell channel length increases from the first subarea to the fourth subarea in sequence.
Optionally, the cell channel length in the first sub-region is 0.8 μm-1.2 μm; the length of a cell channel in the second sub-region is 0.9-1.3 mu m; the length of a cell channel in the third sub-region is 1.05-1.45 mu m; the length of the cell channel in the fourth sub-region is 1.3-1.7 mu m.
Optionally, the power semiconductor chip is strip-shaped.
Optionally, the power transistor is a power field effect transistor or an insulated gate bipolar transistor.
Optionally, the unit cell includes a body doped region located in the substrate, and the spacing between adjacent body doped regions in different sub-regions decreases sequentially from the central sub-region outwards.
In order to solve the above problems, the present invention further provides a method for forming the power semiconductor chip, including: providing a substrate, wherein the substrate comprises a junction terminal area and a cell area surrounded by the junction terminal area, the cell area is used for forming a cell array, the cell area comprises more than two sub-areas, one sub-area is a central sub-area and is positioned at the central position of the cell area, and the other sub-areas are annular and are sequentially arranged around the central sub-area; forming a body doped region of a cell in each sub-region of the cell region; forming a gate oxide layer on the surface of the cellular region; forming a grid on the surface of the grid oxide layer, wherein the grid is positioned on the surface of the substrate between adjacent body doping regions and covers part of the body doping regions, the widths of the body doping regions covered by the grids positioned in the same subarea are the same, and the widths of the body doping regions covered by the grids on the central subarea are smaller than those of the body doping regions covered by the grids on other subareas; and forming source doped regions in the body doped regions at two sides of the grid, wherein the width of the source doped regions covered by the grid is the same in each sub-region.
Optionally, in the step of forming the gate on the surface of the gate oxide layer, the widths of the body doped regions covered by the gates in different sub-regions are sequentially increased from the central sub-region to the outside.
Optionally, the cellular region is in a strip shape.
Optionally, the spacing between adjacent bulk doped regions in different sub-regions decreases sequentially from the central sub-region outwards.
The length of the cell channel in the central sub-area of the cell area of the power semiconductor chip is smaller than that of the cell channels in other sub-areas, so that the central heating value of the chip is reduced in the working process of the chip, the uniformity of the heat distribution of the chip is improved, and the reliability of the chip is improved.
Further, the power semiconductor chip is in a strip shape, and the shortest heat dissipation channel between the center of the cellular region and the junction terminal region is shorter, so that the heat dissipation efficiency of the inner central region of the formed semiconductor power chip is improved, the heat distribution is more uniform in the working process of the chip, and the reliability of the chip is improved
According to the method for forming the power semiconductor chip, the body doping region is formed in the cell region, and then the grid electrode is formed, so that the widths of the grid electrodes on all the subregions of the cell region can be flexibly adjusted to cover different body doping regions by adjusting the sizes of the grid electrodes on all the subregions, the widths of the body doping regions covered by the grid electrodes of the central subregion of the cell region are smaller than those of the body doping regions covered by the grid electrodes of other subregions, the channel width of the cell formed in the central subregion is enabled to be minimum, the heat productivity of the cell in the central subregion of the power semiconductor chip in the working process is further reduced, the heat distribution uniformity of the power semiconductor chip is improved, and the reliability of the power semiconductor chip is improved.
Furthermore, in the method for forming the power semiconductor chip, the cell area is in a strip shape, and compared with a square cell area with the same active area, the shortest heat dissipation channel between the center of the strip-shaped cell area and the junction terminal area is shorter, so that the heat dissipation efficiency of the inner central area of the formed semiconductor power chip is improved, the heat distribution of the chip is more uniform in the working process, and the reliability of the chip is improved.
Drawings
FIG. 1 is a schematic top view of a power semiconductor chip according to an embodiment of the present invention;
FIG. 2 is a schematic top view of a prior art power semiconductor chip;
FIG. 3 is a schematic top view of a power semiconductor chip according to an embodiment of the present invention;
Fig. 4 to 12 are schematic structural views illustrating a process of forming a power semiconductor chip according to an embodiment of the present invention.
Detailed Description
As described in the background art, the semiconductor device of the prior art will generate very large loss on the device when it is operated in the saturated state, and the reliability is lowered. The inventor researches find that the reliability of the power semiconductor device is reduced mainly because the heat distribution in the chip of the device is uneven in the saturated state, the temperature of the central position of the chip is higher than that of the edge position of the chip, and the heat productivity of the central region of the chip is larger than that of the edge region, so that cells in the central region are easy to damage, the loss of the device is increased, and the reliability is reduced.
The invention reduces the cell channel length of the central area of the chip, realizes the reduction of the heating value of the central area, ensures that the internal heating of the chip is uniform, and improves the reliability of the power semiconductor chip.
The following describes in detail the power semiconductor chip and the forming method thereof provided by the invention with reference to the accompanying drawings.
Fig. 1 is a schematic top view of a power semiconductor chip according to an embodiment of the invention.
The power semiconductor chip 100 includes: a ring-shaped junction termination region 101 located at an edge of the power semiconductor chip 100; a cell region 102 surrounded by the junction termination region 101, in which a cell array (not shown) is formed, the cell being a Power field effect transistor, such as a Power field effect transistor (Power MOSFET) or an Insulated Gate Bipolar Transistor (IGBT), or the like; the cellular region 102 includes more than two sub-regions, one of which is a central sub-region, located at the center of the cellular region, and the other sub-regions are annular and are sequentially arranged around the central sub-region; the cell channel lengths in the same sub-region are the same, and the cell channel length in the center sub-region is smaller than the cell channel lengths in the other sub-regions.
In this specific embodiment, the cellular region includes 4 sub-regions, which are a first sub-region I located at the center of the cellular region, the first sub-region I being a central sub-region, a second sub-region II surrounding the first sub-region I, a third sub-region III surrounding the second sub-region II, and a fourth sub-region IV surrounding the third sub-region III. The space from the center of the chip, i.e. the center of the cell region, outwards to the junction termination region 101 is divided into four sub-regions. In this embodiment, the width of each sub-region passing through on a path perpendicular to the junction termination region 101 from the center outward is uniform; in other embodiments of the invention, the width of each sub-region traversed may also be different.
In other embodiments of the present invention, the space from the cell region center outward to the junction termination region 101 may be divided into more than two regions, such as two, three, or five sub-regions, etc.
In the specific embodiment of the invention, the cell channel length in the central sub-region positioned in the center is smaller than the cell channel lengths of other sub-regions at the periphery, so that the threshold voltage and the on-resistance of the cells in the central sub-region are lower than those of the cells in other sub-regions, thereby reducing the heating value of the cells in the central sub-region, further improving the heat distribution uniformity of the power semiconductor chip in the saturation region during operation, and further improving the reliability of the power semiconductor chip.
In order to further improve the uniformity of the heat distribution of the chip, the lengths of cell channels in different sub-regions can be sequentially increased from the center sub-region to the outside. In this embodiment, the cell channel length increases sequentially from the first sub-region I to the fourth sub-region IV. In a specific embodiment, the cell channel length in the first sub-region is 0.8 μm to 1.2 μm; the length of a cell channel in the second sub-region is 0.9-1.3 mu m; the length of a cell channel in the third sub-region is 1.05-1.45 mu m; the length of the cell channel in the fourth sub-region is 1.3-1.7 mu m. Preferably, the length of the cell channel in the first subregion I is 1 μm, the length of the cell channel in the second subregion II is 1.1 μm, the length of the cell channel in the third subregion III is 1.25 μm, and the length of the cell channel in the fourth subregion IV is 1.5 μm.
In order to further improve the heat dissipation efficiency of the cells in the chip near the central area, the power semiconductor chip is designed to be in a long strip shape, as shown in fig. 1, and comprises a long side and a short side, the distance from the center of the chip to the junction terminal area at the edge of the short side is L2, and the distance from the center of the chip to the junction terminal area at the edge of the long side is L1, wherein L1< L2. In the prior art, for the purpose of saving chip area, the power semiconductor chips are generally designed to be square (please refer to fig. 2), so that the vertical distance between the center of the chip and the junction termination region is L3. When the strip-shaped chip has the same cell area or active area as the square chip in the prior art, L1 is smaller than L3, and the heat dissipation efficiency in the heat dissipation transmission process is determined by the shortest heat dissipation channel, so that in the specific embodiment of the invention, the shortest heat dissipation channel of the strip-shaped power semiconductor chip is obviously shortened, the heat dissipation efficiency of the central area inside the chip is improved, the heat of the central area in the working process of the chip can be further reduced, the heat distribution of the chip is even, and the reliability of the chip is improved.
In a specific embodiment of the present invention, the intervals between adjacent body doped regions in the cell region may be equal, or the intervals between adjacent body doped regions in different sub-regions gradually decrease from the central sub-region to the outside, so that the on-resistance of the cells in the central sub-region is lower than that of the cells in other sub-regions, thereby reducing the heat productivity of the cells in the central sub-region, and further improving the heat distribution uniformity of the power semiconductor chip during the operation in the saturation region, and further improving the reliability of the power semiconductor chip.
Referring to fig. 3, in an embodiment of the present invention, a metal connection layer is further formed above the cell area, including a gate bus bar 301 connected to the gate of the cell, where the gate bus bar 301 is disposed along the length direction of the power semiconductor chip; a gate pad 302 connected to the gate bus bar 301; and a source bonding region 303 connected to the source of the cell. The gate bus bar 301 may also be disposed in the width direction of the power semiconductor chip.
The gate bus bar 301, the gate pad 302, and the source pad 303 serve as an electrical connection layer for connecting the cell gate and the source on the chip surface.
The cell channel length in the central subarea of the cell region of the power semiconductor chip provided by the specific embodiment of the invention is smaller than the cell channel lengths in other subareas, so that the central heating value of the chip is reduced in the working process of the chip, the uniformity of the heat distribution of the chip is improved, and the reliability of the chip is improved.
The embodiment of the invention also provides a forming method of the power semiconductor chip.
Fig. 4 to 12 are schematic structural views illustrating a process of forming a power semiconductor chip according to an embodiment of the present invention.
Referring to fig. 4, a substrate 400 is provided, where the substrate 400 includes a junction terminal area 401 and a cell area 402 surrounded by the junction terminal area 401, where the cell area is used to form a cell array, and the cell area includes more than two sub-areas, one of the sub-areas is a central sub-area, and is located at the central position of the cell area, and the other sub-areas are annular and are sequentially disposed around the central sub-area. The unit cell is a power field effect transistor.
The substrate 400 may be monocrystalline silicon and a single-layer or multi-layer doped epitaxial layer structure on the surface of the monocrystalline silicon, or may be a structure produced by single or multiple ion implantation of monocrystalline silicon. Specifically, in this embodiment, the substrate 400 includes a single crystal silicon layer and an N-type doped epitaxial layer on the surface thereof.
In this embodiment, the cellular region 402 includes a first sub-region 402a, which is a central sub-region, and is located at a central position of the cellular region 402; a second sub-region 402b disposed around the first sub-region 402 a; a third sub-region 402c disposed around the second sub-region 402 b; a fourth sub-area 402d is arranged around said third sub-area 402 c. The space from the center of the cell region 402 outward to the junction termination region 401 is divided into four sub-regions. In this embodiment, the width of each sub-region passing through on a path perpendicular to junction termination region 401 from the center of cell region 402 outwards is uniform; in other embodiments of the invention, the width of each sub-region traversed may also be different.
In other embodiments of the present invention, the space from the center of the cell region 402 outward to the junction termination region 401 may be divided into more than two regions, such as two, three, or five sub-regions, etc.
A body doped region of a cell is formed within each sub-region of the cell region 402.
In order to further improve the heat dissipation efficiency of the central sub-region of the cell region, in this embodiment, the cell region 402 is in a strip shape, and compared with a square cell region with the same active region area, the shortest heat dissipation channel between the center of the strip-shaped cell region and the junction terminal region 401 is shorter, so that the heat dissipation efficiency of the central region inside the formed semiconductor power chip is improved, the heat distribution of the chip is more uniform in the working process, and the reliability of the chip is improved.
Please refer to fig. 5-6, which are schematic diagrams illustrating a partial cross-section of a body doped region 601 formed in a cellular region 402 of the substrate.
After forming the thin oxygen layer 501 on the surface of the cellular region 402, a patterned mask layer 502 is formed on the surface of the thin oxygen layer 501, where the mask layer 502 may be a photoresist, silicon nitride or silicon oxynitride layer. The mask layer 502 has an opening exposing a portion of the surface of the thin oxygen layer 501. Then, the masking layer 502 is used as a mask to perform ion implantation on the cellular region 402, thereby forming a body doped layer 503. In this embodiment, P-type ion implantation, such as B-ion implantation, is performed on the cellular region 402 to form a P-type body doped layer 503. The thin oxygen layer 501 can reduce damage to the surface of the cellular region 402 during ion implantation. In each sub-region within the cell region 402, the bulk-doped layers 503 may be uniform in size, and the spacing of the bulk-doped layers 503 in different sub-regions may be the same or taper outwardly along the center. In a specific embodiment, the space between the bulk doping layers 503 in the central sub-region is larger than the space between the bulk doping layers 503 in other peripheral sub-regions, so that the space between the bulk doping regions 601 of the cells in the final central sub-region is larger than the space between the bulk doping regions 601 in the peripheral sub-region, and the on-resistance of the cells in the central sub-region is lower than that of the cells in other sub-regions, thereby reducing the heat productivity of the cells in the central sub-region, and further improving the heat distribution uniformity of the power semiconductor chip during the operation in the saturation region, and further improving the reliability of the power semiconductor chip.
In this embodiment, forming a junction termination doped region in the junction termination region prior to or concurrent with forming the bulk doped layer 503 is also included.
And (3) diffusing doped ions in the bulk doped layer 503 through an annealing process to form a bulk doped region 601 of a cell, and then sequentially removing the mask layer 502 and the thin oxygen layer 501.
Referring to fig. 7, a gate oxide layer 701 is formed on the surface of the cellular region 402. The gate oxide layer 701 may be made of dielectric material such as silicon oxide or silicon nitride. The gate oxide layer 701 may be formed by a thermal oxidation process, a chemical vapor deposition process, or the like.
Referring to fig. 8 and 9, a gate 702 is formed on the surface of the gate oxide layer 701, the gate 702 is located on the surface of the substrate between adjacent body doped regions 601 and covers a part of the body doped regions, the width of the body doped region 601 covered by the gate 702 in the same sub-region is the same, and the width of the body doped region 601 covered by the gate 702 in the central sub-region is smaller than the width of the body doped regions 601 covered by the gates 702 in other sub-regions. In this embodiment, only the cross-sectional view of the gate electrode 702 formed on the first sub-region 402a and the second sub-region 402b is illustrated.
The method for forming the gate 702 includes: after forming a gate material layer on the surface of the gate oxide layer 701, forming a patterned mask layer on the surface of the gate material layer, and etching the gate material layer by taking the patterned mask layer as a mask to form a gate 702, wherein the pattern sizes of the patterned mask layer above each sub-region can be different, so that the gate 702 with different sizes is formed on the surface of each sub-region, and the width of the body doped region 601 covered by the gate 702 on the central sub-region is smaller than the width of the body doped region 601 covered by the gate on other sub-regions, and the width of the body doped region 601 covered by the gate 702 is adjusted. In this embodiment, the material of the gate 702 is polysilicon.
In this embodiment, the width of the body doped region 601 covered by the gate 702 is sequentially increased in the cell region from the central sub-region to the outside in different sub-regions. Specifically, fig. 8 is a schematic cross-sectional view after forming a gate 702 on the first sub-region 402a of the cell region 402. The width of the body doped region 601 covered by the gate 702 formed on the first sub-region 402a is d1. Fig. 9 is a schematic cross-sectional view after forming a gate 702 over the second sub-region 402b of the cellular region 402. The gate 702 formed on the second sub-region 402 covers the body doped region 601 with a width d2, d1< d2. In this embodiment, the width of the body doped region 601 covered by the gate 702 formed on the third sub-region 402c is d3, and the width of the body doped region 601 covered by the gate 702 formed on the third sub-region 402d is d4, then d1< d2< d3< d4.
Since the body doping region 601 is formed in the cell region 402 and then the gate 702 is formed, the width of the body doping region 601 covered by the gate 702 can be adjusted by controlling the size of the gate 702 formed on each sub-region during the formation of the gate 702, thereby adjusting the channel length of the cell formed in each sub-region.
Referring to fig. 10, a mask layer 800 is formed on the surface of the cell region 402 between adjacent gates 702, and ion implantation is performed by using the mask layer 800 and the gates 702 as masks, so as to form a source doped layer 801 in the body doped regions at both sides of the gates 702. In this embodiment, N-type ion implantation, such as Ph ion implantation, is performed using the mask layer 800 and the gate 702 as masks, so as to form an N-type source doped layer 801.
Referring to fig. 11 and 12, an annealing process is performed to diffuse the dopant ions in the source doped layer 801 to form a source doped region 802, and then the mask layer 800 is removed. Since the source doped layer 801 is formed by self-aligned ion implantation at the edge of the gate 702, and each sub-region is annealed simultaneously, the diffusion rate of the dopant ions is uniform, and thus the width of the source doped region 802 formed by diffusion within each sub-region is uniform, which is covered by the gate 702.
Taking the first sub-region 402a and the second sub-region 402b as an example, the width of the source doped region 802 covered by the gate 702 is X, then the cell channel length in the first sub-region 402a is d1-X, and the cell channel length in the second sub-region 402b is d2-X, and since d1< d2, the cell channel length in the first sub-region 402a is smaller than the cell channel length in the second sub-region 402 b. Similarly, in this embodiment, the cell channel length in the second sub-region 402b is less than the cell channel length in the third sub-region 402c, and the cell channel length in the third sub-region 402c is less than the cell channel length in the fourth sub-region 402 d.
In this embodiment, after forming the source doped region 802, forming an interlayer dielectric layer on the substrate; etching the interlayer dielectric layer to form a contact hole; forming a metal layer filling the contact and covering the interlayer dielectric layer; etching the metal layer to form a source electrode, a grid bus bar and a grid pressure welding area; and thinning and depositing a metal layer on the back surface of the substrate to form a drain electrode layer.
According to the method for forming the power semiconductor chip provided by the specific embodiment of the invention, the body doping region is formed in the cell region, and then the grid electrode is formed, so that the widths of the grid electrodes on all the sub-regions of the cell region can be flexibly adjusted to cover different body doping regions by adjusting the sizes of the grid electrodes on all the sub-regions of the cell region, so that the widths of the body doping regions covered by the grid electrodes of the central sub-region of the cell region are smaller than those of the body doping regions covered by the grid electrodes of other sub-regions, the channel width of the cell formed in the central sub-region is minimized, the heat productivity of the cell in the central sub-region of the power semiconductor chip in the working process is reduced, the heat distribution uniformity of the power semiconductor chip is improved, and the reliability of the power semiconductor chip is improved.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (11)
1. A power semiconductor chip, comprising:
a ring-shaped junction termination region located at an edge of the power semiconductor chip;
A cell region surrounded by the junction termination region, wherein a cell array is formed in the cell region, and the cells are power transistors;
The cell area comprises more than two sub-areas, one sub-area is a central sub-area and is positioned at the center of the cell area, and the other sub-areas are annular and are sequentially arranged around the central sub-area; the cell channel lengths in the same subarea are the same, and the cell channel length in the central subarea is smaller than the cell channel lengths in other subareas;
and the metal connecting layer is positioned above the cellular region.
2. The power semiconductor chip of claim 1, wherein cell channel lengths in different sub-regions sequentially increment from a center sub-region outward.
3. The power semiconductor chip of claim 1, wherein the cellular region comprises a first sub-region, a second sub-region surrounding the first sub-region, a third sub-region surrounding the second sub-region, and a fourth sub-region surrounding the third sub-region; the cell channel length increases from the first subarea to the fourth subarea in sequence.
4. A power semiconductor chip according to claim 3, wherein the cell channel length in the first sub-region is 0.8 μm to 1.2 μm; the length of a cell channel in the second sub-region is 0.9-1.3 mu m; the length of a cell channel in the third sub-region is 1.05-1.45 mu m; the length of the cell channel in the fourth sub-region is 1.3-1.7 mu m.
5. The power semiconductor chip of claim 1, wherein the power semiconductor chip is elongated.
6. The power semiconductor chip of claim 1, wherein the power transistor is a power field effect transistor or an insulated gate bipolar transistor.
7. The power semiconductor chip of claim 1, wherein the cells include bulk-doped regions within the substrate, the spacing between adjacent bulk-doped regions in different sub-regions decreasing in sequence, outward from the central sub-region.
8. A method of forming a power semiconductor chip, comprising:
Providing a substrate, wherein the substrate comprises a junction terminal area and a cell area surrounded by the junction terminal area, the cell area is used for forming a cell array, the cell area comprises more than two sub-areas, one sub-area is a central sub-area and is positioned at the central position of the cell area, and the other sub-areas are annular and are sequentially arranged around the central sub-area;
forming a body doped region of a cell in each sub-region of the cell region;
forming a gate oxide layer on the surface of the cellular region;
Forming a grid on the surface of the grid oxide layer, wherein the grid is positioned on the surface of the substrate between adjacent body doping regions and covers part of the body doping regions, the widths of the body doping regions covered by the grids positioned in the same subarea are the same, and the widths of the body doping regions covered by the grids on the central subarea are smaller than those of the body doping regions covered by the grids on other subareas;
And forming source doped regions in the body doped regions at two sides of the grid, wherein the width of the source doped regions covered by the grid is the same in each sub-region.
9. The method of claim 8, wherein in the step of forming the gate electrode on the surface of the gate oxide layer, the width of the body doped region covered by the gate electrode increases from the central sub-region to the outside in different sub-regions.
10. The method of claim 8, wherein the cell region is elongated.
11. The method of claim 8, wherein the spacing between adjacent bulk doped regions in different sub-regions decreases sequentially from the center sub-region outward.
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| CN101150069A (en) * | 2007-11-09 | 2008-03-26 | 中国电子科技集团公司第二十四研究所 | Making method for low on-resistance power VDMOS transistor |
| CN101728382A (en) * | 2008-10-21 | 2010-06-09 | 北大方正集团有限公司 | Power device chip |
| CN103325838A (en) * | 2013-06-26 | 2013-09-25 | 株洲南车时代电气股份有限公司 | Power semiconductor chip and manufacturing method thereof |
| JP2014003200A (en) * | 2012-06-20 | 2014-01-09 | Renesas Electronics Corp | Vertical power mosfet and semiconductor device |
| CN107680967A (en) * | 2017-10-25 | 2018-02-09 | 嘉兴奥罗拉电子科技有限公司 | Power semiconductor chip and forming method thereof |
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| CN101150069A (en) * | 2007-11-09 | 2008-03-26 | 中国电子科技集团公司第二十四研究所 | Making method for low on-resistance power VDMOS transistor |
| CN101728382A (en) * | 2008-10-21 | 2010-06-09 | 北大方正集团有限公司 | Power device chip |
| JP2014003200A (en) * | 2012-06-20 | 2014-01-09 | Renesas Electronics Corp | Vertical power mosfet and semiconductor device |
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