CN103474466A - High-voltage device and manufacturing method thereof - Google Patents

High-voltage device and manufacturing method thereof Download PDF

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CN103474466A
CN103474466A CN2013104180884A CN201310418088A CN103474466A CN 103474466 A CN103474466 A CN 103474466A CN 2013104180884 A CN2013104180884 A CN 2013104180884A CN 201310418088 A CN201310418088 A CN 201310418088A CN 103474466 A CN103474466 A CN 103474466A
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type semiconductor
conductive type
drift region
region
tagma
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CN103474466B (en
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乔明
李燕妃
蔡林希
吴文杰
许琬
陈涛
胡利志
张波
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University of Electronic Science and Technology of China
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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Abstract

The invention relates to the semiconductor technology, in particular to a high-voltage device and a manufacturing method of the high-voltage device. The high-voltage device is integrated on a semiconductor substrate of a first conducting type and comprises a semiconductor drift region of a second conducting type, a semiconductor source region of the second conducting type, a semiconductor drain region of the second conducting type, a semiconductor heavily doped region of the second conducting type, a semiconductor body region of the second conducting type, a semiconductor body contact zone of the first conducting type, a semiconductor reduced-field layer of the first conducting type, a gate oxide, a field oxide, a metal front medium, a polysilicon gate electrode, source electrode metal, and drain electrode metal. The semiconductor heavily-doped layer of the second conducting type is arranged between the field oxide and the semiconductor reduced-field layer of the first conducting type. The high-voltage device and the manufacturing method of the high-voltage device have the advantages that smaller chip area is achieved under the conduction that the conducting capability is not changed, an electric field of the surface of a device is optimized, the manufacturing method is simple, and the technological difficulty is low. The high-voltage device and the manufacturing method of the high-voltage device are especially suitable for high-voltage devices.

Description

A kind of high tension apparatus and manufacture method thereof
Technical field
The present invention relates to semiconductor technology, relate to specifically a kind of high tension apparatus and manufacture method thereof.
Background technology
High tension apparatus is that high-voltage power integrated circuit develops requisite part, and high voltage power device requires to have high puncture voltage, low conducting resistance and low switching loss.At power LDMOS(Latral Double-diffused MOSFET) in device design, there are contradictory relation in conduction resistance and puncture voltage, raising along with puncture voltage, the conduction resistance of device sharply rises, thereby limited the application of high-voltage LDMOS device in high-voltage power integrated circuit, especially in the circuit that requires low conduction loss and little chip area.In order to overcome the problem of high conducting resistance, the people such as J.A.APPLES have proposed RESURF(Reduced SURface Field) reduction surface field technology, be widely used in the design of high tension apparatus, wherein, triple RESURF is up to now, the good structure of near optimal for products such as actual AC/DC, further improve on this basis high tension apparatus conduction resistance and withstand voltage be the demand of industry, the source electric field of triple RESURF structure is too high simultaneously, affects device reliability.
Summary of the invention
Technical problem to be solved by this invention, be exactly for the problems referred to above, proposes a kind of novel high-pressure device and preparation method thereof.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of high tension apparatus, its structure cell comprises the first conductive type semiconductor substrate 1, the second conductive type semiconductor drift region 21, the second conductive type semiconductor source region 22, the second conductive type semiconductor drain region 23, the first conductive type semiconductor tagma 31, the first conductive type semiconductor body contact zone 32, the first conductive type semiconductor tagma buried regions 33, a layer 34 falls in the first conductive type semiconductor, gate oxide 41, field oxide 42, medium 43 before metal, polygate electrodes 51, source metal 52 and drain metal 53, described the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31 and the first conductive type semiconductor tagma buried regions 33 are arranged in the first conductive type semiconductor substrate 1, described the first conductive type semiconductor tagma buried regions 33 is arranged on the lower surface in the first conductive type semiconductor tagma 31, a layer 34 falls in described the first conductive type semiconductor and the second conductive type semiconductor drain region 23 is arranged in the second conductive type semiconductor drift region 21, described the second conductive type semiconductor source region 22 and the first conductive type semiconductor body contact zone 32 are arranged in the first conductive type semiconductor tagma 31 also separate, described field oxide 42 is arranged on the upper surface of the second conductive type semiconductor drift region 21, described gate oxide 41 is arranged on the upper surface in part the second conductive type semiconductor source region 22, the upper surface of the upper surface in the first conductive type semiconductor tagma 31 and the second conductive type semiconductor drift region 21 also is connected with field oxide 42, described polygate electrodes 51 is arranged on the upper surface of gate oxide 41 and the upper surface of part field oxide 42, described source metal 52 is arranged on the upper surface of the first conductive type semiconductor body contact zone 32, the upper surface in part the second conductive type semiconductor source region 22, described drain metal 53 is arranged on the upper surface in part the second conductive type semiconductor drain region 23, before described metal, medium 43 is filled between source metal 52 and drain metal 53, source metal 52 and drain metal 53 medium 43 upper surfaces before metal extend to form field plate, it is characterized in that, also comprise the second conductive type semiconductor heavily doped layer, described the second conductive type semiconductor heavily doped layer consists of the second conductiving type semiconductor area that is divided into multistage and is arranged on the first conductive type semiconductor and falls between layer 34 and field oxide 42.
Wherein, the second conductive type semiconductor heavily doped layer is divided into 6 1～6 imultistage, a plurality of the second conductive type semiconductor heavily doped layers 6 1～6 ithe sectional area size can be identical or different, interregional distance along with to the second conductive type semiconductor drain region 23 near and reduce gradually, the spacing of sectional area can be identical or not identical, area size along with to the second conductive type semiconductor drain region 23 near and increase gradually.
Concrete, also comprising the second conductive type semiconductor buried regions 24, described the second conductive type semiconductor buried regions 24 is arranged in the second conductive type semiconductor drift region 21 and is positioned at the first conductive type semiconductor and falls a lower surface of layer 34.
The advantage of this programme is to provide for device the conductive channel of another low-resistance.
Concrete, described the first conductive type semiconductor tagma 31 and the first conductive type semiconductor tagma buried regions 33 are arranged in the second conductive type semiconductor drift region 21.
Concrete, described the second conductive type semiconductor drift region 21 is arranged on the upper surface of the first conductive type semiconductor substrate 1.
Concrete, also comprise SOI substrate 2, described SOI substrate 2 is arranged between the first conductive type semiconductor substrate 1 and the second conductive type semiconductor drift region 21 and is connected with the second conductive type semiconductor drift region 21 with the first conductive type semiconductor substrate 1 respectively.
A kind of manufacture method of high tension apparatus, is characterized in that, comprises the following steps:
The first step: adopt photoetching and ion implantation technology, inject the second conductive type semiconductor impurity in the first conductive type semiconductor substrate 1, annealing diffuses to form the second conductive type semiconductor drift region 21, the resistivity of described the first conductive type semiconductor substrate 1 is 10～200 ohmcms, and the implantation dosage of the second conductive type semiconductor drift region 21 is 1E12cm -2～2E13cm -2;
Second step: adopt photoetching and ion implantation technology, inject the first conductive type semiconductor impurity in the first conductive type semiconductor substrate 1, annealing diffuses to form the first conductive type semiconductor tagma 31, and the implantation dosage in described the first conductive type semiconductor tagma 31 is 1E12cm -2～5E13cm -2;
The 3rd step: in the second conductive type semiconductor drift region, 21 upper surfaces form field oxide 42;
The 4th step: adopt photoetching and ion implantation technology, inject the first conductive type semiconductor impurity in the second conductive type semiconductor drift region 21, form the first conductive type semiconductor tagma buried regions 33 and the first conductive type semiconductor and fall a layer 34, the implantation dosage of described the first conductive type semiconductor impurity is 1E11cm -2～2E13cm -2;
The 5th step: adopt photoetching and ion implantation technology, inject the second conductive type semiconductor impurity in the second conductive type semiconductor drift region 21, rapid thermal annealing forms the second conductive type semiconductor heavily doped layer of segmentation, and the implantation dosage of described the second conductive type semiconductor heavily doped layer is 1E11cm -2～2E13cm -2;
The 6th step: form gate oxide 41 at the upper surface in part the second conductive type semiconductor source region 22, the upper surface in the first conductive type semiconductor tagma 31 and the upper surface of the second conductive type semiconductor drift region 21, the thickness of described gate oxide 41 is 7nm～100nm;
The 7th step: form polygate electrodes 51 at the upper surface of gate oxide 41 and the upper surface of part field oxide 42, the square resistance of described polysilicon gate 51 is 10～40 ohms/square;
The 8th step: adopt photoetching and ion implantation technology, form the second conductive type semiconductor drain region 23 in the second conductive type semiconductor drift region 21, form separate the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32 in the first conductive type semiconductor tagma 31, the implantation dosage of described the second conductive type semiconductor drain region 23, the second conductive type semiconductor source 22, the first conductive type semiconductor body contact zone 32 is 1E13cm -2～2E16cm -2;
The 9th step: medium 43 before the upper surface deposit in the upper surface of the upper surface of the upper surface in part the second conductive type semiconductor source 22, polysilicon gate 51, oxide layer 42 and part the second conductive type semiconductor drain region 23 forms metal;
The tenth step: at the upper surface of the first conductive type semiconductor body contact zone 32 and the upper surface in the second conductive type semiconductor source 22, form source metal 52, form drain metal 53 at the upper surface in the second conductive type semiconductor drain region 23, source metal 52 with the front medium 43 of drain metal 53 and metal, be connected and before metal the upper surface of medium 43 extend to form field plate.
Concrete, described the first conductive type semiconductor tagma buried regions 33 can prevent the parasitic triode conducting, improves the performance of device, the 4th step also can not form the first conductive type semiconductor tagma buried regions 33.
Concrete, in described the 5th step, the second conductive type semiconductor heavily doped layer 6 of segmentation 1～6 iby rapid thermal anneal process, form, it is identical or different that it injects window size, window pitch along with to the second conductive type semiconductor drain region 23 near and reduce gradually, the spacing of injecting window is identical or not identical, window size along with to the second conductive type semiconductor drain region 23 near and increase gradually.
Further, can also form the second conductive type semiconductor drift region 21 by epitaxy technique, or form the second conductive type semiconductor drift region 21 on the SOI backing material, the second conductive type semiconductor heavily doped layer 6 1～6 iadopt sectional dopedly, introduce a plurality of surface field spikes when withstand voltage, the optimised devices surface field avoids the source electric field excessive simultaneously, prevents high-field effect.
Beneficial effect of the present invention is, in the situation that keep high puncture withstand voltage, can reduce greatly the device conduction resistance, reduce the peak electric field of high tension apparatus source simultaneously, avoid high-field effect, improve the puncture voltage of device, with the conventional high-tension device, compare, high tension apparatus provided by the invention is in the situation that the identical chips area has less conducting resistance, in the situation that identical ducting capacity has less chip area, and the surface field of optimised devices well, simultaneously, preparation method provided by the invention is simple, and technology difficulty is lower.
The accompanying drawing explanation
Fig. 1 is the generalized section of conventional high-tension device;
Fig. 2 is the generalized section of a kind of high tension apparatus of the present invention, along with close to the second conductive type semiconductor drain electrode heavily doped region 23, and the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 ispacing reduces gradually, and the second conductive type semiconductor drift region 21 forms by Implantation and knot technique, is integrated on the first conductive type semiconductor substrate 1;
Fig. 3 is the generalized section of a kind of high tension apparatus of the present invention, along with close to the second conductive type semiconductor drain electrode heavily doped region 23, and the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 iwidth increases gradually, and the second conductive type semiconductor drift region 2 is to form by Implantation and knot technique, is integrated on the first conductive type semiconductor substrate 1;
Fig. 4 is the generalized section of a kind of high tension apparatus of the present invention, along with close to the second conductive type semiconductor drain electrode heavily doped region 23, and the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 ispacing reduces gradually, and the second conductive type semiconductor drift region 21 forms by epitaxy technique, is integrated on the first conductive type semiconductor substrate 1;
Fig. 5 is the generalized section of a kind of high tension apparatus of the present invention, along with close to the second conductive type semiconductor drain electrode heavily doped region 23, and the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 iwidth increases gradually, and the second conductive type semiconductor drift region 21 is to form by epitaxy technique, is integrated on the first conductive type semiconductor substrate 1;
Fig. 6 is the generalized section of a kind of high tension apparatus of the present invention, along with close to the second conductive type semiconductor drain electrode heavily doped region 23, and the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 ispacing reduces gradually, and the second conductive type semiconductor drift region 21 forms by epitaxy technique, is integrated on the SOI substrate;
Fig. 7 is the generalized section of a kind of high tension apparatus of the present invention, along with close to the second conductive type semiconductor drain electrode heavily doped region 23, and the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 iwidth increases gradually, and the second conductive type semiconductor drift region 21 forms by epitaxy technique, is integrated on the SOI substrate;
Fig. 8 is the generalized section of a kind of high tension apparatus of the present invention, along with close to the second conductive type semiconductor drain electrode heavily doped region 23, and the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 ispacing reduces gradually, and the second conductive type semiconductor buried regions 24 is arranged in the second conductive type semiconductor drift region 21, is positioned at the first conductive type semiconductor and falls layer 34 below;
Fig. 9 is the generalized section of a kind of high tension apparatus of the present invention, along with close to the second conductive type semiconductor drain electrode heavily doped region 23, and the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 iwidth increases gradually, and the second conductive type semiconductor buried regions 24 is arranged in the second conductive type semiconductor drift region 21, is positioned at the first conductive type semiconductor and falls layer 34 below;
Figure 10 is the generalized section of a kind of high tension apparatus of the present invention, along with close to the second conductive type semiconductor drain electrode heavily doped region 23, and the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 ispacing reduces gradually, and all high-voltage device structures all are arranged in the second conductive type semiconductor drift region 21;
Figure 11 is the generalized section of a kind of high tension apparatus of the present invention, along with close to the second conductive type semiconductor drain electrode heavily doped region 23, and the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 iwidth increases gradually,, all high-voltage device structures all are arranged in the second conductive type semiconductor drift region 21;
Figure 12 is the second conductive type semiconductor heavily doped layer 6 in embodiment 1 1～6 ia plurality of injection window structure schematic diagrames;
Figure 13 is that embodiment 1 injects the second conductive type semiconductor heavily doped layer 6 that forms segmentation 1～6 ischematic diagram;
Figure 14 is the second conductive type semiconductor heavily doped layer 6 in embodiment 2 1～6 ia plurality of injection window structure schematic diagrames;
Figure 15 is that embodiment 2 injects the second conductive type semiconductor heavily doped layer 6 that forms segmentation 1～6 ischematic diagram.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
As shown in Figure 1, for traditional high-voltage device structure profile, high tension apparatus is integrated on the first conductive type semiconductor substrate 1, comprises that a layer 34, field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32 fall in the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor; The first conductive type semiconductor falls a layer 34 and realizes, surrounded by the second conductive type semiconductor drift region 21 by ion implantation technology; The first conductive type semiconductor tagma buried regions 33 is between the first conduction type tagma 31 and the first conductive type semiconductor substrate 1; Source metal 52 is positioned at the first conductive type semiconductor tagma 31 upsides, is connected with the first conductive type semiconductor body contact zone 32 with the second conductive type semiconductor source region 22, and drain metal 53 is connected with the second conductive type semiconductor drain region 23; Polygate electrodes 51 is positioned at gate oxide 41 tops, and field oxide 43 is positioned at 21 tops, the second conductive type semiconductor drift region; Between polygate electrodes 51, source metal 52 and drain metal 53, by medium 43 before metal, mutually isolate.
As shown in Figure 2, for a kind of high-voltage device structure profile provided by the invention, comprise that a layer 34, field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, the front medium 43 of metal, source metal 52, drain metal 53 fall in the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor; It is characterized in that, described high-voltage semi-conductor device also comprises that layer 34 and the second conductive type semiconductor heavily doped layer 6 fall in the first conductive type semiconductor 1～6 i, described the second conductive type semiconductor heavily doped layer 6 1～6 iat field oxide 42 and the first conductive type semiconductor, fall between a layer 34.Wherein, a layer 34 falls in the first conductive type semiconductor to be realized by Implantation and knot technique, the second conductive type semiconductor heavily doped layer 6 1～6 iby Implantation and rapid thermal anneal process, realize, along with close to the first conductive type semiconductor drain region 23, the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 ispacing reduces gradually, and this structure not only reduces the conduction resistance of device, also reduces device source Electric Field Distribution, avoids high-field effect, the optimised devices surface field, thus improve device electric breakdown strength, alleviate withstand voltage and contradictory relation conduction resistance.
As shown in Figure 3, be a kind of high-voltage device structure profile provided by the invention, comprise that a layer 34, the second conductive type semiconductor heavily doped layer 6 fall in the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor 1～6 i, medium 43, source metal 52, drain metal 53 before field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metal.Wherein, a layer 34 falls in the first conductive type semiconductor to be realized by Implantation and knot technique, the second conductive type semiconductor heavily doped layer 6 1～6 iby Implantation and rapid thermal anneal process, realize, along with close to the first conductive type semiconductor drain region 23, the second conductive type semiconductor heavily doped region 6 of segmentation 1～6 iwidth increases gradually, and its operation principle is similar to Fig. 2, reduces device source Electric Field Distribution, avoids high-field effect, improves device electric breakdown strength, simultaneously for electric current provides low impedance path, reduces the device conduction resistance, alleviates conduction resistance and withstand voltage contradictory relation.
As shown in Figure 4, be a kind of high-voltage device structure profile provided by the invention, comprise that a layer 34, the second conductive type semiconductor heavily doped layer 6 fall in the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor 1～6 i, medium 43, source metal 52, drain metal 53 before field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metal.Wherein, device is integrated on the first conductive type semiconductor substrate 1, and the second conductive type semiconductor drift region 21 realizes by epitaxy technique, and other technical processs and operation principle are referring to the explanation to Fig. 2.
As shown in Figure 5, be a kind of high-voltage device structure profile provided by the invention, comprise that a layer 34, the second conductive type semiconductor heavily doped layer 6 fall in the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor 1～6 i, medium 43, source metal 52, drain metal 53 before field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metal.Wherein, device is integrated on the first conductive type semiconductor substrate 1, and the second conductive type semiconductor drift region 21 realizes by epitaxy technique, and other technical processs and operation principle are referring to the explanation to Fig. 3.
As shown in Figure 6, be a kind of high-voltage device structure profile provided by the invention, comprise that a layer 34, the second conductive type semiconductor heavily doped layer 6 fall in the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor 1～6 i, medium 43, source metal 52, drain metal 53 before field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metal.Wherein, device is integrated on the SOI backing material, and the second conductive type semiconductor drift region 21 realizes by epitaxy technique, and other technical processs and operation principle are referring to the explanation to Fig. 2.
As shown in Figure 7, be a kind of high-voltage device structure profile provided by the invention, comprise that a layer 34, the second conductive type semiconductor heavily doped layer 6 fall in the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor 1～6 i, medium 43, source metal 52, drain metal 53 before field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metal.Wherein, device is integrated on the SOI backing material, and the second conductive type semiconductor drift region 21 realizes by epitaxy technique, and other technical processs and operation principle are referring to the explanation to Fig. 3.
As shown in Figure 8, be a kind of high-voltage device structure profile provided by the invention, comprise that a layer 34, the second conductive type semiconductor heavily doped layer 6 fall in the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor 1～6 i, medium 43, source metal 52, drain metal 53 before the second conductive type semiconductor buried regions 24, field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metal.The second conductive type semiconductor buried regions 24 is arranged in the second conductive type semiconductor drift region 21, its upper surface falls a layer 34 with the first conductive type semiconductor and is connected, the second conductive type semiconductor buried regions 24 has improved another low impedance path for high tension apparatus, further reduces conduction resistance.Other technical processs and operation principle are referring to the explanation to Fig. 2.
As shown in Figure 9, be a kind of high-voltage device structure profile provided by the invention, comprise that a layer 34, the second conductive type semiconductor heavily doped layer 6 fall in the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor 1～6 i, medium 43, source metal 52, drain metal 53 before the second conductive type semiconductor buried regions 24, field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metal.The second conductive type semiconductor buried regions 24 is arranged in the second conductive type semiconductor drift region 21, its upper surface falls a layer 34 with the first conductive type semiconductor and is connected, the second conductive type semiconductor buried regions 24 has improved another low impedance path for high tension apparatus, further reduces conduction resistance.Other technical processs and operation principle are referring to the explanation to Fig. 3.
As shown in figure 10, be a kind of high-voltage device structure profile provided by the invention, comprise that a layer 34, the second conductive type semiconductor heavily doped layer 6 fall in the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor 1～6 i, medium 43, source metal 52, drain metal 53 before the second conductive type semiconductor buried regions 24, field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metal.The all structures of high tension apparatus all are arranged in the second conductive type semiconductor drift region 21, and self-isolation is realized in the first conductive type semiconductor tagma and the second conductive type semiconductor drift region 21.Other technical processs and operation principle are referring to the explanation to Fig. 2.
As shown in figure 11, be a kind of high-voltage device structure profile provided by the invention, comprise that a layer 34, the second conductive type semiconductor heavily doped layer 6 fall in the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor tagma buried regions 33, the first conductive type semiconductor 1～6 i, medium 43, source metal 52, drain metal 53 before the second conductive type semiconductor buried regions 24, field oxide 42, gate oxide 41, polygate electrodes 51, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32, metal.The all structures of high tension apparatus all are arranged in the second conductive type semiconductor drift region 21, and self-isolation is realized in the first conductive type semiconductor tagma and the second conductive type semiconductor drift region 21.Other technical processs and operation principle are referring to the explanation to Fig. 3.
Operation principle of the present invention is:
Operation principle of the present invention and traditional high tension apparatus are similar, be all the puncture voltage that the application charge balance concept improves device, but lateral high-voltage device conduction loss provided by the invention are lower than traditional lateral high-voltage device.Fig. 1 is traditional high tension apparatus, comprises that a layer 34, field oxide 42, gate oxide 41, polysilicon gate 51, the front medium 43 of metal, the second conductive type semiconductor drain region 23, the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32 fall in the first conductive type semiconductor substrate 1, the second conductive type semiconductor drift region 21, the first conductive type semiconductor tagma 31, the first conductive type semiconductor.During break-over of device, electric current flows to the second conductive type semiconductor source region 22 from 23rd district, the second conductive type semiconductor drain region through the second conductive type semiconductor drift region 21, because the concentration of the second conductive type semiconductor drift region 21 is lower, the conducting resistance of device is very large, and conduction loss increases.As shown in Figure 2, for high tension apparatus provided by the invention, with traditional lateral high-voltage device, compare, high tension apparatus provided by the invention forms the first conductive type semiconductor and falls a layer 34 in the second conductive type semiconductor drift region 21 by ion implantation technology, and the second conductive type semiconductor heavily doped layer 6 of the 21 surface formation segmentations in the second conductive type semiconductor drift region by Implantation and knot technique 1～6 i.During ON state, the heavily doped layer 6 of high concentration 1～6 ifor high tension apparatus provides a large amount of majority carriers, form the conductive channel of a low-resistance at device surface, can greatly reduce break-over of device resistance, thereby reduce greatly process costs.During OFF state, drain metal 53 adds high pressure, and layer 34 and the first conductive type semiconductor substrate 1 assisted depletion the second conductive type semiconductor drift region 21 and the second conductive type semiconductor heavily doped layer 6 fall in the first conductive type semiconductor 1～6 i, make device obtain larger puncture voltage.Simultaneously, the second conductive type semiconductor heavy doping 6 of segmentation 1～6 ireduce the source electric field of device, avoid high-field effect, introduce a plurality of electric field spikes on surface, the surface field of modulation drift region 21, improve the withstand voltage of device, thereby alleviated conduction resistance and withstand voltage contradictory relation in horizontal high voltage power device.Therefore, in the power integrated circuit application, under the condition of same output current ability, the area of high-voltage semi-conductor device is minimized.
Preparation method's step of a kind of high tension apparatus provided by the invention is as follows:
The first step: adopt photoetching and ion implantation technology, inject the second conductive type semiconductor impurity in the first conductive type semiconductor substrate 1, annealing diffuses to form the second conductive type semiconductor drift region 21, the resistivity of described the first conductive type semiconductor substrate 1 is 10～200 ohmcms, and the implantation dosage of the second conductive type semiconductor drift region 21 is 1E12cm -2～2E13cm -2;
Second step: adopt photoetching and ion implantation technology, inject the first conductive type semiconductor impurity in the first conductive type semiconductor substrate 1, annealing diffuses to form the first conductive type semiconductor tagma 31, and the implantation dosage in described the first conductive type semiconductor tagma 31 is 1E12cm -2～5E13cm -2;
The 3rd step: in the second conductive type semiconductor drift region, 21 upper surfaces form field oxide 42;
The 4th step: adopt photoetching and ion implantation technology, inject the first conductive type semiconductor impurity in the second conductive type semiconductor drift region 21, form the first conductive type semiconductor tagma buried regions 33 and the first conductive type semiconductor and fall a layer 34, the implantation dosage of described the first conductive type semiconductor impurity is 1E11cm -2～2E13cm -2;
The 5th step: adopt photoetching and ion implantation technology, inject the second conductive type semiconductor impurity in the second conductive type semiconductor drift region 21, rapid thermal annealing forms the second conductive type semiconductor heavily doped layer of segmentation, and the implantation dosage of described the second conductive type semiconductor heavily doped layer is 1E11cm -2～2E13cm -2;
The 6th step: form gate oxide 41 at the upper surface in part the second conductive type semiconductor source region 22, the upper surface in the first conductive type semiconductor tagma 31 and the upper surface of the second conductive type semiconductor drift region 21, the thickness of described gate oxide 41 is 7nm～100nm;
The 7th step: form polygate electrodes 51 at the upper surface of gate oxide 41 and the upper surface of part field oxide 42, the square resistance of described polysilicon gate 51 is 10～40 ohms/square;
The 8th step: adopt photoetching and ion implantation technology, form the second conductive type semiconductor drain region 23 in the second conductive type semiconductor drift region 21, form separate the second conductive type semiconductor source region 22, the first conductive type semiconductor body contact zone 32 in the first conductive type semiconductor tagma 31, the implantation dosage of described the second conductive type semiconductor drain region 23, the second conductive type semiconductor source 22, the first conductive type semiconductor body contact zone 32 is 1E13cm -2～2E16cm -2;
The 9th step: medium 43 before the upper surface deposit in the upper surface of the upper surface of the upper surface in part the second conductive type semiconductor source 22, polysilicon gate 51, oxide layer 42 and part the second conductive type semiconductor drain region 23 forms metal;
The tenth step: at the upper surface of the first conductive type semiconductor body contact zone 32 and the upper surface in the second conductive type semiconductor source 22, form source metal 52, form drain metal 53 at the upper surface in the second conductive type semiconductor drain region 23, source metal 52 with the front medium 43 of drain metal 53 and metal, be connected and before metal the upper surface of medium 43 extend to form field plate.
Wherein, the second conductive type semiconductor drift region 21 can also form by epitaxy technique; Field oxide 42 can also form after a layer 34 falls in the first conductive type semiconductor, can utilize the annealing process of field oxide 42, a layer 34 is fallen in the first conductive type semiconductor and carry out annealing in process, and device can be integrated on the SOI substrate simultaneously.
The present invention forms the first conductive type semiconductor and falls a layer in the second conductive type semiconductor drift region by ion implantation technology, and forms the second conductive type semiconductor heavily doped layer by ion implantation technology above a layer falls in the first conductive type semiconductor.During ON state, the second conductive type semiconductor heavily doped layer, for device provides the surface conductance passage of a low-resistance, has reduced conducting resistance and the power consumption of device.Simultaneously, the second conductive type semiconductor heavily doped layer of segmentation reduces device source electric field, avoids high-field effect, at device surface, introduces a plurality of electric field spikes, optimised devices surface field, thereby the puncture voltage of raising device.With the horizontal high voltage power device of tradition, compare, high tension apparatus provided by the invention is in the situation that the identical chips area has less conducting resistance (or in the situation that identical ducting capacity has less chip area).And the present invention also provides a kind of manufacturing technology of high tension apparatus, its technique is comparatively simple, and cost is lower.
In method provided by the invention, the 4th step and the 5th step are the key feature step.
Embodiment 1:
This routine adopting process is, the second conductive type semiconductor heavily doped layer 6 1～6 ihave a plurality of Implantation windows, the size of window is identical, and the spacing difference of window, along with close to the second conductive type semiconductor drain region 23, is injected window pitch to reduce gradually, as shown in figure 12.Figure 13 is the device architecture profile after the second conductive type semiconductor Impurity injection, forms the second conductive type semiconductor heavily doped layer 6 of segmentation in figure after the second conductive type semiconductor Impurity injection 1～6 i.Simultaneously, field oxide 42 formed before an ion implantation technology of layer 34 falls in the first conductive type semiconductor, first formed field oxide 42, and the annealing process of field oxide 42 can not affect the Implantation of back.The second conductive type semiconductor heavily doped layer 6 of segmentation 1～6 i, the surface of a low-resistance is provided for high tension apparatus during ON state, reduce the conduction resistance of device, reduce the source electric field of device during OFF state, avoid device to puncture in advance, improve the puncture voltage of device.
Embodiment 2:
This routine adopting process is, the second conductive type semiconductor heavily doped layer 6 1～6 ithere are a plurality of Implantation windows, the varying in size of window, and the spacing of window is identical, along with close to the second conductive type semiconductor drain region 23, injects window size to increase gradually, as shown in figure 14.Figure 15 is the device architecture profile after the second conductive type semiconductor Impurity injection, forms the second conductive type semiconductor heavily doped layer 6 of segmentation in figure after the second conductive type semiconductor Impurity injection 1～6 i.Simultaneously, field oxide 42 formed before an ion implantation technology of layer 34 falls in the first conductive type semiconductor, first formed field oxide 42, and the annealing process of field oxide 42 can not affect the Implantation of back.The second conductive type semiconductor heavily doped layer 6 of segmentation 1～6 i, the surface of a low-resistance is provided for high tension apparatus during ON state, reduce the conduction resistance of device, reduce the source electric field of device during OFF state, avoid device to puncture in advance, improve the puncture voltage of device.The high tension apparatus that this routine technological process forms, its operation principle is identical with embodiment 1.
By above-mentioned explanation, can be obtained, the present invention forms the first conductive type semiconductor by photoetching and ion implantation technology and falls a layer 34 in the second conductive type semiconductor drift region 21, by photoetching and ion implantation technology, the second conductive type semiconductor heavily doped layer 6 formed on the surface of the second conductive type semiconductor drift region 21 1～6 i.During ON state, the second conductive type semiconductor heavily doped layer 6 1～6 ifor device provides a surperficial low-resistance conductive channel, reduced the resistivity of device surface, thereby greatly reduced the conducting resistance of device.During OFF state, the second conductive type semiconductor heavily doped layer 6 of linear doping 1～6 ithe surface field of optimised devices, avoid the source electric field excessive, prevents that high-field effect from causing device to puncture in advance, makes the novel high-pressure device have higher puncture voltage.Therefore, with the conventional high-tension device, compare, high tension apparatus provided by the invention is in the situation that the identical chips area has less conducting resistance (or in the situation that identical ducting capacity has less chip area).

Claims (7)

1. a high tension apparatus, its structure cell comprises the first conductive type semiconductor substrate (1), the second conductive type semiconductor drift region (21), the second conductive type semiconductor source region (22), the second conductive type semiconductor drain region (23), the first conductive type semiconductor tagma (31), the first conductive type semiconductor body contact zone (32), the first conductive type semiconductor tagma buried regions (33), a layer (34) falls in the first conductive type semiconductor, gate oxide (41), field oxide (42), medium (43) before metal, polygate electrodes (51), source metal (52) and drain metal (53), described the second conductive type semiconductor drift region (21), the first conductive type semiconductor tagma (31) and the first conductive type semiconductor tagma buried regions (33) are arranged in the first conductive type semiconductor substrate (1), described the first conductive type semiconductor tagma buried regions (33) is arranged on the lower surface in the first conductive type semiconductor tagma (31), a layer (34) falls in described the first conductive type semiconductor and the second conductive type semiconductor drain region (23) is arranged in the second conductive type semiconductor drift region (21), described the second conductive type semiconductor source region (22) and the first conductive type semiconductor body contact zone (32) are arranged in the first conductive type semiconductor tagma (31) also separate, described field oxide (42) is arranged on the upper surface of the second conductive type semiconductor drift region (21), described gate oxide (41) is arranged on the upper surface in part the second conductive type semiconductor source region (22), the upper surface of the upper surface in the first conductive type semiconductor tagma (31) and the second conductive type semiconductor drift region (21) also is connected with field oxide (42), described polygate electrodes (51) is arranged on the upper surface of gate oxide (41) and the upper surface of part field oxide (42), described source metal (52) is arranged on the upper surface of the first conductive type semiconductor body contact zone (32), the upper surface in part the second conductive type semiconductor source region (22), described drain metal (53) is arranged on the upper surface in part the second conductive type semiconductor drain region (23), before described metal, medium (43) is filled between source metal (52) and drain metal (53), source metal (52) and drain metal (53) medium (43) upper surface before metal extends to form field plate, it is characterized in that, also comprise the second conductive type semiconductor heavily doped layer, described the second conductive type semiconductor heavily doped layer consists of the second conductiving type semiconductor area that is divided into multistage and is arranged on the first conductive type semiconductor and falls between layer (34) and field oxide (42).
2. a kind of high tension apparatus according to claim 1, it is characterized in that, also comprise the second conductive type semiconductor buried regions (24), described the second conductive type semiconductor buried regions (24) is arranged in the second conductive type semiconductor drift region (21) and is positioned at the first conductive type semiconductor and falls a lower surface of layer (34).
3. a kind of high tension apparatus according to claim 1 and 2, it is characterized in that, described the first conductive type semiconductor tagma (31) and the first conductive type semiconductor tagma buried regions (33) are arranged in the second conductive type semiconductor drift region (21).
4. a kind of high tension apparatus according to claim 3, is characterized in that, described the second conductive type semiconductor drift region (21) is arranged on the upper surface of the first conductive type semiconductor substrate (1).
5. a kind of high tension apparatus according to claim 4, it is characterized in that, also comprise SOI substrate (2), described SOI substrate (2) is arranged between the first conductive type semiconductor substrate (1) and the second conductive type semiconductor drift region (21) and is connected with the second conductive type semiconductor drift region (21) with the first conductive type semiconductor substrate (1) respectively.
6. the manufacture method of a high tension apparatus, is characterized in that, comprises the following steps:
The first step: adopt photoetching and ion implantation technology, inject the second conductive type semiconductor impurity in the first conductive type semiconductor substrate (1), annealing diffuses to form the second conductive type semiconductor drift region (21), the resistivity of described the first conductive type semiconductor substrate (1) is 10～200 ohmcms, and the implantation dosage of the second conductive type semiconductor drift region (21) is 1E12cm -2～2E13cm -2;
Second step: adopt photoetching and ion implantation technology, inject the first conductive type semiconductor impurity in the first conductive type semiconductor substrate (1), annealing diffuses to form the first conductive type semiconductor tagma (31), the first conductive type semiconductor tagma (31) is connected with the second conductive type semiconductor drift region (21), and the implantation dosage in described the first conductive type semiconductor tagma (31) is 1E12cm -2～5E13cm -2;
The 3rd step: at the second conductive type semiconductor drift region (21) upper surface, form field oxide (42);
The 4th step: adopt photoetching and ion implantation technology, inject the first conductive type semiconductor impurity in the second conductive type semiconductor drift region (21), form the first conductive type semiconductor tagma buried regions (33) and the first conductive type semiconductor and fall a layer (34), the implantation dosage of described the first conductive type semiconductor impurity is 1E11cm -2～2E13cm -2;
The 5th step: adopt photoetching and ion implantation technology, inject the second conductive type semiconductor impurity in the second conductive type semiconductor drift region (21), rapid thermal annealing forms the second conductive type semiconductor heavily doped layer of segmentation, and the implantation dosage of described the second conductive type semiconductor heavily doped layer is 1E11cm -2～2E13cm -2;
The 6th step: form gate oxide (41) at the upper surface in part the second conductive type semiconductor source region (22), the upper surface in the first conductive type semiconductor tagma (31) and the upper surface of the second conductive type semiconductor drift region (21), the thickness of described gate oxide (41) is 7nm～100nm;
The 7th step: form polygate electrodes (51) at the upper surface of gate oxide (41) and the upper surface of part field oxide (42), the square resistance of described polysilicon gate (51) is 10～40 ohms/square;
The 8th step: adopt photoetching and ion implantation technology, form the second conductive type semiconductor drain region (23) in the second conductive type semiconductor drift region (21), form separate the second conductive type semiconductor source region (22), the first conductive type semiconductor body contact zone (32) in the first conductive type semiconductor tagma (31), the implantation dosage of described the second conductive type semiconductor drain region (23), the second conductive type semiconductor source (22), the first conductive type semiconductor body contact zone (32) is 1E13cm -2～2E16cm -2;
The 9th step: medium (43) before the upper surface deposit in the upper surface of the upper surface of the upper surface in part the second conductive type semiconductor source (22), polysilicon gate (51), oxide layer (42) and part the second conductive type semiconductor drain region (23) forms metal;
The tenth step: at the upper surface of the first conductive type semiconductor body contact zone (32) and the upper surface in the second conductive type semiconductor source (22), form source metal (52), form drain metal (53) at the upper surface in the second conductive type semiconductor drain region (23), the front medium (43) of source metal (52) and drain metal (53) and metal be connected and before metal the upper surface of medium (43) extend to form field plate.
7. the preparation method of a kind of high tension apparatus according to claim 6, is characterized in that, the described first step is for adopting epitaxy technique to form the second conductive type semiconductor drift region (21).
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