CN101542726A - Semiconductor chip with silicon through holes and side bonding pads - Google Patents
Semiconductor chip with silicon through holes and side bonding pads Download PDFInfo
- Publication number
- CN101542726A CN101542726A CN200880000341A CN200880000341A CN101542726A CN 101542726 A CN101542726 A CN 101542726A CN 200880000341 A CN200880000341 A CN 200880000341A CN 200880000341 A CN200880000341 A CN 200880000341A CN 101542726 A CN101542726 A CN 101542726A
- Authority
- CN
- China
- Prior art keywords
- silicon
- hole
- chip
- bonding pads
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06183—On contiguous sides of the body
- H01L2224/06187—On contiguous sides of the body with specially adapted redistribution layers [RDL]
- H01L2224/06188—On contiguous sides of the body with specially adapted redistribution layers [RDL] being disposed in a single wiring level, i.e. planar layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06551—Conductive connections on the side of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a multi-chip semiconductor element encapsulation used in flash memory products or the like. In an embodiment, a semiconductor chip can comprise silicon through holes and side bonding pads.
Description
Technical field
[0001] the multi-chip semiconductor equipment that can in such as flash memory products (flash memorydevice), use of the present invention relates to disclosed here.
Background of invention
[0002] integrated circuit has become the basic element of character of many electronic equipments.In some cases, merging a plurality of integrated circuit (IC) wafer or " chip " is very useful in same semiconductor equipment.For example, chip can be stacked on another chip, chip can be electrically connected mutually by lead-in wire bonding (wire-bonding) in some cases, chip can be electrically connected mutually by silicon through hole (through-silicon-via) in other cases, and it can pass completely through a Silicon Wafer and is electrically connected.In the encapsulating structure of this laminated chips, bottom chip can provide and be electrically connected to substrate.Signal redistributed by substrate and electric power is given laminated chips.Substrate can also be electrically connected to a printed circuit board (PCB), for example, is connected with external equipment and/or assembly to allow semiconductor equipment by solder joint.Multi-chip semiconductor equipment can be widely used, and comprises such as flash memory products.
Description of drawings
[0003] particularly points out with clear at the conclusion part of specification theme of the present invention has been described.But, by with reference to detailed description, be appreciated that its structure and/or operation method below in conjunction with accompanying drawing, and purpose, feature and/or advantage, wherein:
[0004] Fig. 1 a is the vertical view of a multi-chip semiconductor encapsulation example embodiment;
[0005] Fig. 1 b is the sectional view of Fig. 1 a demonstration semiconductor packages;
[0006] Fig. 2 a describes an aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer and side bonding pads;
[0007] Fig. 2 b describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer and side bonding pads, comprises wafer bonding to a support;
[0008] Fig. 2 c describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer and side bonding pads, comprises making wafer thinner;
[0009] Fig. 2 d describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer and side bonding pads, comprises boring (drilling hole);
[0010] Fig. 2 e describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer and side bonding pads, comprises forming a separator;
[0011] Fig. 2 f describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer and side bonding pads, comprises forming an adhesion layer;
[0012] Fig. 2 g describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer and side bonding pads, comprises filling vias;
[0013] Fig. 2 h describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer and side bonding pads, comprises forming a polymeric layer;
[0014] Fig. 2 i describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer and side bonding pads, comprises forming solder bump (solder bump);
[0015] Fig. 2 j describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer and side bonding pads, comprises wafer cutting (dicing);
[0016] Fig. 3 is a sectional view that comprises the semiconductor equipment example embodiment of silicon through hole and side interconnection;
[0017] Fig. 4 is the sectional view of the example embodiment of a semiconductor chip stack; With
[0018] Fig. 5 describes the flow chart of the example embodiment of a kind of silicon through hole that forms semiconductor chip and side bonding pads method;
[0019] Fig. 6 describes the flow chart of example embodiment that a kind of assembling comprises the demonstration semiconductor equipment method of silicon through hole and side bonding pads laminated chips.
[0020] with reference to following detailed description to accompanying drawing, it constitutes a part of the present invention, and wherein from first to last same number is meant that same assembly is to show correspondence or similar element.For convenience of description, should be appreciated that the element of describing is not necessarily drawn according to actual size in accompanying drawing.For example, according to other element, can amplify the size of some of them element.And, should be appreciated that, also can utilize other embodiment, and can make the change of structure and/or logic aspect, and not depart from scope of the present invention.Also should be noted that, can service orientation and numbering such as upper and lower, top, the end etc. so that accompanying drawing is discussed, but this is not to be intended to limit application of the present invention.So the following detailed description and the scope of the invention that is defined by the present invention and equivalent thereof are not restrictive.
Detailed Description Of The Invention
[0021] in the following detailed description, will set forth many concrete details so that can complete understanding the present invention.But it will be understood to those of skill in the art that does not need these details can implement the present invention yet.Therefore, will can not describe known method, process, assembly and/or circuit in detail at this.
[0022] in specification, " embodiment " is meant that special feature, structure or a characteristic that present embodiment is described are included among at least one embodiment of the present invention.Therefore, not necessarily be meant same embodiment at different local " in the embodiment " that occur of this specification.And special feature, structure or characteristic can merge in one or more embodiment by any way.
[0023] as mentioned above, in some electronic equipments, many semiconductor chips can be arranged with stacked system, so that can improve serviceability and keep less relatively cost and less size." multicore sheet " semiconductor equipment can be widely used in electronic device field.For example, " lamination " of semiconductor chip to be arranged in the flash memory device be useful especially.Certainly, miscellaneous equipment also can make full use of laminated semiconductor chip structure and other multicore sheet structure.
[0024] stacked multichip technology comprises the lead-in wire bonding.The lead-in wire bonding has some shortcomings, as the relatively large size (form factor) that causes by relatively large lead-in wire profile, and the higher stack chip height when using the lead-in wire bonding.Another shortcoming comprises relatively poor relatively electrical property, as the signal delay that is caused by relatively long pin interconnection.Silicon through hole technology can be avoided these latent defects at least in part.
[0025] as mentioned above, when realizing the laminated semiconductor chip, semiconductor chip can utilize silicon through hole (TSV) to transmit signal to another chip from a chip.As used herein, " silicon through hole " and abbreviation TSV thereof are meant and comprise any vertical electrical connection that passes completely through Silicon Wafer, wafer or a chip.As used herein, " wafer " and " chip " is synonym, can exchange use mutually.Usually, " wafer " is meant the rectangular segments of semiconductor crystal wafer.
[0026] may have some advantages although have the laminated semiconductor chip of TSV, also have some shortcomings.For example, TSV is useful when each semiconductor chip that provides shared signal to the part lamination.Shared signal can comprise such as address signal and/or data-signal.As used herein, " shared signal " is meant any signal of sharing in a plurality of laminated chips.In many embodiment, shared signal can be shared in all laminated chips.Therefore, TSV transmits shared signal to chip from chip, and signal will arrive each expection chip.For example, if laminated chips forms the part flash memory device, address signal may need to be paired to each semiconductor chip.May be quite effective in that these signals are provided to each lamination elements T SV.On the other hand, non-shared signal such as chip selectivity signal, utilizes TSV effectively not handled.To non-shared signal,, cause sizable wafer size and cost to increase and failure rate if use the TSV quantity that TSV may significantly increase to be needed.
[0027] moreover, utilize the conventional semiconductor wafer to have superiority, as aim at those designs that the lead-in wire bonding is implemented, for example TSV technology.But if use some TSV solutions, and any change is not done in design to wafer, may be difficult to hold enough TSV interconnection owing to the space is limited and be used for shared and non-shared signal.Certainly, change chip design and may need bigger effort and enough resources.One or more embodiment described herein provides TSV interconnection, and does not need to change the wafer design, and can hold shared and non-shared signal.
[0028] in an embodiment, non-shared signal can be by the side substrate of a flexibility, and the side bonding pads from semiconductor chip is routed to a substrate, as a substrate that comprises Bismaleimide Triazine (BT).Moreover in this example embodiment, one or more shared signals can be routed to substrate by one or more TSV.As used herein, " non-shared signal " is meant a kind of like this signal, and the core number that sort signal will go to is less than all core numbers in the lamination.In a plurality of embodiment, non-shared signal may only remove a chip, although scope of the present invention is not limited in this respect.In memory device, the example of non-shared signal includes but not limited to chip selectivity signal and power signal.
[0029] Fig. 1 a is the vertical view that a multi-chip semiconductor encapsulates 100 example embodiment.Semiconductor packages 100 in this example comprises a semiconductor chip stack 400, and it comprises a plurality of discrete semiconductor wafers, and each semiconductor wafer is placed on the top of another semiconductor wafer.In an embodiment, to small part by the welding on a plurality of TSV position 130, chip can be bonded together mutually, and can strengthen physical bond by the polymer material layer between the chip.The semiconductor chip stack 400 of this example embodiment is electrically connected to substrate 150.In an example embodiment, substrate 150 can comprise Bismaleimide Triazine (BT), although scope of the present invention is not limited in this respect.
[0030] in one or more embodiment, semiconductor chip stack 400 can be soldered to BT substrate 150 by TSV130, and can utilize the bottom of polymeric material to fill to strengthen physical bond, although scope of the present invention is not limited to these aspects.
[0031] moreover, in an embodiment, semiconductor chip stack 400 can comprise one or more sides substrate 140, also can be called the side connector this its.In one or more embodiment, the side substrate can comprise flexible side substrate.For example, the side substrate can comprise the one or more metallic signal lines on the flexiplast bearing, and this flexiplast bearing can be bonded to one or more side bonding pads by viscose glue, although scope of the present invention is not limited to these aspects.
[0032] Fig. 1 b is the sectional view of a multi-chip semiconductor encapsulation 100.This schematic diagram shows the semiconductor chip stack 400 with some silicon through holes 130 and side connector 140.The semiconductor chip stack 400 of this example is positioned on the BT substrate 150, and at least in part by material 170 sealed package.In the embodiment, TSV 130 can be electrically connected to substrate 150 with a plurality of shared signals, and side substrate 140 can be electrically connected to BT substrate 150 with one or more non-shared signals.In Fig. 1 a and the described embodiment of 1b, multi-chip semiconductor encapsulation 100 can comprise a nand flash memory product, although scope of the present invention is not limited in this respect.In one or more embodiment, more than a kind of chip type can be integrated in the chip-stack.The example that can be integrated into this chip type in the chip-stack can include but not limited to flash chip, dynamic random access memory (DRAM) chip, application-specific integrated circuit (ASIC) (ASIC) chip etc.
[0033] in an embodiment, side substrate 140 comprises a pair of polymeric layer, and they surround the copper layer.Towards the surface of the side of chip-stack 400 substrate 400, be formed with a plurality of bonding welding pads, it can be connected to a plurality of sides connector on the chip of chip-stack 400.In an embodiment, bonding welding pad can comprise the copper of nickel/gold surface polishing.Bonding welding pad can be electrically connected to the intermediate metal layer of side substrate 140 via through hole.In addition, in an embodiment, being clipped in two copper layers between the polymeric layer can not be a pantostrat, but may comprise a structure, to be re-assigned to side substrate 400 from the signal of chip-stack 400 than lower part, so that connect signal to BT substrate 150.Certainly, this only is the example embodiment of a side substrate, and scope of the present invention is not limited in this respect.
[0034] in an embodiment, semiconductor chip stack 400 can protect by a kind of moulding material 170.In an example embodiment, substrate 150 also can protect at least in part, although in other embodiment, substrate 150 is not by moulding material 170 sealed package.In an example embodiment, moulding material 170 can comprise the epoxy polymer material, although scope of the present invention is not limited in this respect.
[0035] Fig. 2 a describes an aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer 200 and side bonding pads.In following diagram, will the many aspects of this exemplary teachings be described.Embodiments of the invention can comprise all, the part or a plurality of described different aspect.In addition, the relevant order of discussing only is a demonstration order, so scope of the present invention is not limited in this respect.Embodiments of the invention are not subject to exemplary teachings described herein.And, can use the prior art of any formation silicon through hole and side bonding pads or the technology of developing in the future.Moreover concrete material described herein only is to be used as example to use, so scope of the present invention is not limited to concrete example described herein.
[0036] in the described example of Fig. 2 a, wafer 200 can comprise one the input wafer, its may be from such as
Company or Samsung company buying and coming.Wafer 200 can comprise a plurality of integrated circuits 210.In order clearly to be described, two integrated circuits 210 are described in this example.Certainly, scope of the present invention is not limited in this respect.In integrated circuit 210, have a plurality of bonding welding pads 250, in an example embodiment, pad may comprise the copper with nickel/gold surface.But this only is the example of a bonding welding pad, so scope of the present invention is not limited in this respect.Between bonding welding pad and integrated circuit, there is a re-distribution layer 255 to provide interconnected.
[0037] common, wafer such as wafer 200 can be divided into a plurality of individual chips, and in some cases, a plurality of chips can be stacked on together.When implementing, use Wire Bonding Technology to come the interconnect stack chip, gold thread can be bonded to a bonding welding pad, also is bonded to the bonding welding pad of another chip simultaneously.With compare based on the chip-stack of lead-in wire bonding, the TSV technology has some advantages usually, comprises owing to the reduced size that does not have feed-through collar (wire loop) to produce because the better electrical property that produces than lack interconnecting, it can reduce signal delay and power consumption.Other potential advantage may comprise and alleviates the integrated of various functional chip types, and lower overall manufacturing cost.
[0038] in one or more embodiment, provide enough spaces to hold the TSV interconnection of non-shared signal for fear of redesign integrated circuit and/or wafer, can form the side connector and be used for non-shared signal.The TSV interconnection can be used for shared signal, and it can make full use of the bonding welding pad that has been produced on the existing wafer.Wafer 200 is initially used for the lead-bonding chip lamination and is designed, and in this example, it promptly is the starting point of described demonstration in Fig. 2 b-2j.
[0039] in an embodiment, semiconductor crystal wafer 200 comprises a silicon layer 220.Moreover, in an embodiment, in this silicon layer, support to have integrated circuit 210.Embodiments of the invention may comprise the integrated circuit of any kind, include but not limited to memory circuit.In addition, can use any known technology or the technology of developing in the future, form integrated circuit 210.As described above, in one or more embodiment, the wafer that wafer 200 has been made before can comprising, it comprises integrated circuit, re-distribution layer and bonding welding pad.
[0040] Fig. 2 b describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer 200 and side bonding pads.In an embodiment, above wafer, make one layer of polymeric base viscose glue 240, and wafer support 230 can be bonded to wafer 200.In one or more embodiment, support 230 may comprise glass.In another embodiment, support 230 may comprise silicon.But these only are the exemplary materials that possible be used for support 230, so scope of the present invention is not limited in this respect.Moreover in an embodiment, polymer-matrix viscose glue 240 can be bonded to support 230 with wafer 200 on a quite low temperature, and wafer also can be removed bonding by making viscose glue 240 be subjected to a quite high temperature.In an embodiment, viscose glue 240 may comprise a kind of thermoplastic materials polymer, and it can provide temporary transient bonding being lower than on about 150 ℃ temperature.Moreover, in an embodiment, one about 180 ℃ on the temperature of 210 ℃ of scopes, wafer can be removed bonding from support 230.But scope of the present invention is not limited to these aspects.
[0041] Fig. 2 c describes another aspect of the exemplary teachings of a kind of silicon through hole that forms wafer 200 and side bonding pads.In one or more example embodiment, can be with silicon layer 220 attenuation.Promptly can reduce the thickness of silicon layer 220.Although embodiments of the invention are not limited to reduce any special technology of silicon layer thickness, in an example embodiment, (mechanicalgrinding process) can make the silicon layer attenuation by a mechanical disruption technology.Make other possible technique of wafer 200 attenuation may include but not limited to chemico-mechanical polishing (chemicalmechanical polishing), wet etching (wet etching) and dry chemical etch (dry chemicaletching) by the thickness that reduces silicon layer 220.In one or more embodiment, wafer 200 is before attenuation, and its thickness may be in the scope of about 300-400 μ m, and after attenuation, thickness may be in the scope of about 50-100 μ m, although scope of the present invention is not limited in this respect.
[0042] Fig. 2 d describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer 200 and side bonding pads.In one or more embodiment, a plurality of through holes 260 are arranged, its degree of depth extends through silicon layer 220 to arrive integrated circuit 210.In present embodiment, through hole 260 is approximately consistent with the position of previous through hole 255.But these only are the demonstration positions of through hole, so scope of the present invention is not limited in this respect.
[0043] in an embodiment, approximately is being formed with a part deep hole 265 on the centre position between two integrated circuits.In an embodiment, the position of part deep hole 265 can be one and aim at wafer cutting (die saw) and the position of design.In an embodiment, the degree of depth of part deep hole 265 is less than the degree of depth of through hole 260.Scope of the present invention is not limited to any special degree of depth of part deep hole.
[0044] in one or more embodiment, can use any known technology or the technology of exploitation in the future to form through hole 260 and part deep hole 265.In an example embodiment, can form each hole by a deep reactive ion etch (DRIE) technology, comprise spin coating one deck photoetching material (photoresist material) on crystal column surface, and exposure and manifest photoetching material and determine the zone that will be holed.In another embodiment, can utilize a kind of method for drilling holes.But these only are the exemplary teachings of making each hole, so scope of the present invention is not limited to these aspects.
[0045] Fig. 2 e describes another aspect of the exemplary teachings of a kind of silicon through hole that forms semiconductor crystal wafer 200 and side bonding pads.In one or more embodiment, separator 225 of formation below wafer is included on the sidewall of through hole 260 and on the bottom of part deep hole 265 and the sidewall and forms separator.In an embodiment, separator 225 may comprise silica (SiO
2), although scope of the present invention is not limited in this respect, so other insulating material also is feasible.Others as described herein can utilize the technology of any known technology or exploitation in the future to form separator 225.In an embodiment, separator 225 may comprise the SiO for preparing by chemical vapour deposition (CVD) (PECVD)
2, its thickness may approximately be 0.5 μ m, although scope of the present invention is not limited in this respect.
[0046] Fig. 2 f describes another aspect of the exemplary teachings of a kind of silicon through hole that forms wafer 200 and side bonding pads.In an embodiment, form an adhesion layer 270 in the part bottom of wafer 200.As described in Fig. 2 f, can form adhesion layer 270 in through hole 260 and part deep hole 265 and on the basal surface of the wafer 200 of peripheral region.Adhesion layer 270 can adhere to separator 225 and Seed Layer (not shown), and it can form after forming adhesion layer, to provide an electrode to following described electroplating technology.Seed Layer can comprise the same material that uses in the padding of the following stated, although scope of the present invention is not limited in this respect.In an embodiment, can use a kind of sputtering technology (sputtering technique), make adhesion layer 270 and Seed Layer, although scope of the present invention is not limited in this respect.In an embodiment, adhesion layer 270 also can serve as a separator, to avoid copper conductor in the through hole (not describing) and insulating material 225 that exposes or the potential reaction between the silicon layer 220 in Fig. 2 f.In an embodiment, adhesion layer 270 may comprise the titanium tungsten that thickness is approximately 0.1 to 0.2 μ m, although scope of the present invention is not limited in this respect.
[0047] Fig. 2 g describes another aspect of the exemplary teachings of a kind of silicon through hole that forms wafer 200 and side bonding pads.In an embodiment, fill a kind of electric conducting material in through hole 260 and part deep hole 265.For example, can fill copper in the hole.In another example embodiment, can fill polysilicon in the hole.Other operable exemplary materials include but not limited to gold, scolder, tungsten, conducting resinl etc.But these only are the electric conducting materials of demonstration, so scope of the present invention is not limited in this respect.In one or more embodiment, the exemplary teachings of deposits conductive material may include but not limited to that electroless plating (electroless plating), dipping are electroplated (immersion plating), scolder printing, conducting resinl is printed or configuration and metallide technology.In through hole 260, conductive path, extends fully through silicon layer 220, thereby forms TSV up to through hole 260 locational pads 290 from the through hole 235 locational bonding welding pads 250 made before by deposits conductive material.
[0048] Fig. 2 h describes another aspect of the exemplary teachings of a kind of silicon through hole that forms wafer 200 and side bonding pads.In one or more embodiment, deposition one layer of polymeric material layer 295 is at the downside of wafer 200.Polymeric layer 295 can provide extra structural intergrity, and can provide a surface so that bond to another semiconductor chip, for example, if the words of using lamination to implement.In addition, polymeric layer 295 can determine that the position to make pad on instinct via top, does not touch another pad to guarantee pad, and causes short circuit.In an example embodiment, polymeric material 295 may comprise polyamine (PI) or benzocyclobutene (BCB), although scope of the present invention is not limited in this respect.Moreover in an embodiment, polymeric layer 295 can form by spin coating and curing technology (spin coating and curing techniques), although scope of the present invention is not limited in this respect.
[0049] Fig. 2 i describes another aspect of the exemplary teachings of a kind of silicon through hole that forms wafer 200 and side bonding pads.In an embodiment, deposition pad 290 with about consistent zone, through hole 260 positions.In one or more embodiment, pad 290 may comprise tin, tin/lead-in wire synthetic material, tin/copper synthetic material, tin/silver/copper synthetic material, tin/indium synthetic material, tin/golden synthetic material etc., although scope of the present invention is not limited in this respect.The exemplary teachings that forms pad 290 may include but not limited to electroplate and/or the little seal of solder cream (solder paste micro-printing).Others as described herein, embodiments of the invention are not limited to deposit any special technology of pad.
[0050] Fig. 2 j describes another aspect of the exemplary teachings of a kind of silicon through hole that is used for forming wafer 200 and side bonding pads.In this example embodiment, two integrated circuits have been described in Fig. 2 a-2j.Certainly, other embodiment may comprise the more integrated circuit (IC) wafer of big figure usually.But in this example, two integrated circuits are intended to describe a kind of technology that forms side bonding pads 235.In an embodiment, when wafer 200 was cut, part deep hole 265 was cut apart, and as described in Fig. 2 j, electric conducting material 280 forms a pair of side bonding pads 235.This links to each other with an integrated circuit to one of them of side bonding pads, and another side bonding pads links to each other with another integrated circuit.In this embodiment, wafer cutting 299 is divided into two different chips with wafer 200.Moreover, in one or more embodiment, temperature to be brought up to more than 180 ℃, wafer 200 can be removed bonding from support 240.
[0051] in the described example of Fig. 2 j, side bonding pads 235 is electrically connected to TSV.But, in other example embodiment, can have indivedual conductive paths that side bonding pads and integrated circuit are linked together.For example, polymeric layer 295 can comprise the electric conducting material of TSV, links to each other with side bonding pads, but can not provide bond pads, thereby have the conductive path of an insulation between side bonding pads and the integrated circuit.
[0052] Fig. 3 describes the sectional view of the example embodiment of a semiconductor chip 300.In one or more embodiment, chip 300 can comprise a silicon layer 320.Although do not show in Fig. 3, semiconductor equipment 300 may comprise an integrated circuit that forms on silicon layer 320.A plurality of silicon through holes 340 extend through silicon layer 320 and polymeric layer 310.In this embodiment, a plurality of bonding welding pads 350 are arranged on the upper surface of silicon layer.As described above, if wafer is for utilizing the lead-in wire bonding to design and make, bonding welding pad 350 has just existed.As shown in Figure 4, bonding welding pad 350 is positioned at the top of TSV 340, and in the via top that links to each other with side bonding pads 330.Certainly, these through holes may be to form according to above-described exemplary teachings.Should be noted that these through holes that link to each other with side bonding pads 330 extend fully and penetrate polymeric layer 310, touch the bonding welding pad of a chip of chip 300 belows in the lamination to avoid through hole.Moreover in an embodiment, bond pads 390 also can be formed on the TSV 340.Notice, a pair of pad is arranged for TSV 340.Bonding welding pad 350 has appeared on the wafer, and bond pads 390 is to form according to exemplary teachings described herein.
[0053] TSV 340 can be connected to one or more shared signals of integrated circuit, and side bonding pads 330 can be connected to the one or more non-shared signal that links to each other with integrated circuit.As following shown in Figure 4, a plurality of semiconductor chips such as chip 300 can be piled up mutually, and TSV provides the interconnection of the shared signal between the chip.Although example embodiment described herein is mentioned shared signal that links to each other with TSV and the non-shared signal that links to each other with side bonding pads, scope of the present invention is not so limited, so other embodiment also is possible, be that one or more non-shared signals can link to each other with TSV, and one or more shared signal can link to each other with side bonding pads.
[0054] Fig. 4 describes the sectional view of the example embodiment of a semiconductor chip stack 400.In the example that Fig. 4 describes, semiconductor chip stack 400 comprises a nand flash memory lamination.In an embodiment, the chip of chip-stack 400 may comprise similar chip.In one or more other embodiment, the chip of chip-stack 400 may comprise different kinds of chips.In an example embodiment, chip-stack may comprise one or more nand flash memory chips, dram chip and asic chip.Certainly, these only are the examples that can constitute the chip type of a chip-stack, and scope of the present invention is not limited in this respect.Moreover, in this example, four semiconductor chips have been described, although scope of the present invention is not limited in this respect, other embodiment can utilize any number of dies.
[0055] in one or more example embodiment, the semiconductor chip of lamination 400 may comprise the element as the similar semiconductor chip of describing in Fig. 3 300, as the integrated circuit that forms in a silicon layer.A plurality of silicon through holes extend through the silicon layer and the polymeric layer of a plurality of chips.In an embodiment, a plurality of bonding welding pads are formed on the upper surface of silicon layer, and as described above, bonding welding pad approximately is positioned at the top of TSV, also is positioned on the top of the through hole that links to each other with side bonding pads.In this example embodiment, the through hole that links to each other with side bonding pads can not extend fully and penetrates polymeric layer, touches the bonding welding pad of a chip of current chip below in the lamination to avoid through hole.Other embodiment as described herein, TSV can be connected to one or more shared signals of integrated circuit, and side bonding pads can be connected to the one or more non-shared signal that links to each other with integrated circuit.Moreover in one or more embodiment, by the connection of bond pads, the bonding welding pad of first chip can be electrically connected to second chip of placing at the first chip top.Bond pads has description above the description in conjunction with Fig. 3 in the embodiment.In the example of Fig. 4, between each chip of chip-stack 400, there is a plurality of bonding welding pads/bond pads to connect 445.
[0056] in present embodiment, semiconductor chip stack is installed on the connector 430.Connector 430 can comprise holding wire in case distributing signal to TSV or from the TSV received signal.For example, connector 430 may comprise shared signal pad 440, and at a demonstration Shi Lili, it can be soldered to substrate 450, can be soldered to a printed circuit board (PCB) (not shown) subsequently.In the described example of Fig. 4, be connected to the top of connector 430 from the shared signal of chip-stack 400.In this example embodiment, connector 430 can be redistributed shared signal, and signal can also be connected to the bonding welding pad of connector bottom, is soldered to substrate 450 subsequently.In one or more embodiment, connector 430 may comprise silicon, although scope of the present invention is not limited in this respect.In one or more embodiment, substrate 450 may comprise Bismaleimide Triazine (BT), although scope of the present invention is not limited in this respect.
[0057] as described in the accompanying drawing 4, side substrate 410 is connected to a plurality of side bonding pads.Other embodiment as described herein, side bonding pads can link to each other with one or more non-shared signals.In this example embodiment, wherein semiconductor chip stack 400 comprises a nand flash memory lamination, and one or more non-shared signals may comprise chip select signal.In an embodiment, chip select signal can be electrically connected to substrate 450.The side substrate 410 of this example can comprise non-shared signal pad 420.Certainly, chip select signal only is the example of a signal type, and it can transmit via side bonding pads and side substrate.In one or more example embodiment, side substrate 410 may comprise a flexible sides substrate.
[0058] as described above, in an embodiment, the flexible sides substrate may comprise a pair of polymeric layer, and it is clipped in the middle layer of copper.But this only is the example embodiment of a side substrate, so scope of the present invention is not limited in this respect.
[0059] Fig. 5 is the flow chart of the example embodiment of a kind of silicon through hole that forms semiconductor chip and side bonding pads method.2a-2j in conjunction with the accompanying drawings describes the various aspects of this demonstration methods in detail.In module 510, there is the wafer of at least one integrated circuit to be bonded on the support, in module 520, make wafer thinner.In module 530, etch through hole, in module 540, form a separator.In module 550, at least a portion separator, form an adhesion layer.In module 560, filling vias in module 570, forms a polymer-matrix.In module 580, scolder is electroplated on the through hole of filling, and in module 590, wafer is cut.Embodiments of the invention can comprise among the module 510-590 all, the part and a plurality of module.In addition, the order of module 510-590 only is a demonstration order, and scope of the present invention is not limited in this respect.
[0060] Fig. 6 is the flow chart of example embodiment of the semiconductor equipment method of the laminated chips of a kind of assembling with TSV and side bonding pads.In module 610, make a connector that the TSV interconnection is arranged, its bottom chip with final chip-stack is mated, and in module 620, bottom chip is installed on the connector.In module 630,,, add next chip to lamination in module 640 if determine to also have other chip also will be installed on this lamination.In module 630,, be bonded to the side bonding pads of laminated chips at 650, one side substrates of module if determine not have other chip.In module 660, the side substrate is bonded to a bottom substrate, and in module 670, reflux solder is fixed on the bottom substrate with the solder joint with connector.Certainly, embodiments of the invention may comprise among the module 610-670 all, the part or a plurality of module.And the order of module 610-670 only is a demonstration order, so scope of the present invention is not limited in this respect.
[0061] be referred to herein as " and/or " may be meant " with ", may be meant " or ", may be meant " exclusive or ", may be meant " one of them ", may be meant " some, but be not whole ", may be meant " neither being ", and/or may be meant " both is ", although scope of the present invention is not limited in this respect.
[0062] in the description in front, various aspects of the present invention has been described.For convenience of explanation, concrete number, system and/or structure have been set forth so that can understand the present invention all sidedly.But it will be understood by those skilled in the art that does not need these concrete details can implement the present invention yet, thereby obtains the advantage of this disclosure.For example, can ignore and/or simplify known feature, so that can clearly understand the present invention.Though in this description and/or some feature of the present invention is described, the experienced technical staff in the art can make many improvement, replacement, change and/or be equal to.So, will be understood that additional claim, it is intended to be included in all improvement and/or change in the present invention's spirit scope.
Claims (30)
1. device comprises:
A plurality of semiconductor chips are arranged with stacked system, and a plurality of chips comprise one or more silicon through holes and one or more side bonding pads; With
A side substrate, it is electrically connected to one or more side bonding pads.
2. device according to claim 1, one or more silicon through holes are electrically connected to a bottom substrate with one or more shared signals from a plurality of semiconductor chips.
3. device according to claim 1, one or more silicon through holes are electrically connected to a connector (interposer) with one or more shared signals from a plurality of semiconductor chips, and connector is electrically connected to a bottom substrate.
4. device according to claim 3, wherein the side substrate is electrically connected to bottom substrate.
5. device according to claim 4, one or more side bonding pads are electrically connected to bottom substrate by the side substrate from a plurality of semiconductor chips with one or more non-shared signals.
6. device according to claim 5, wherein bottom substrate comprises Bismaleimide Triazine (BT).
7. device according to claim 1, wherein the side substrate comprises a flexible sides substrate, and it comprises the two layers of polymers layer, accompanies one deck conductive layer in the middle of the two layers of polymers layer.
8. device according to claim 3, wherein one or more shared signals comprise one or more address signals and/or data-signal.
9. device according to claim 5, wherein one or more non-shared signals comprise one or more chip select signals and/or power signal.
10. device according to claim 1, wherein a plurality of semiconductor chips comprise one or more flash chips, dynamic random storage chip and/or dedicated IC chip.
11. a multi-chip semiconductor encapsulation comprises:
A plurality of semiconductor chips are arranged with stacked system, and a plurality of semiconductor chips comprise one or more silicon through holes and one or more side bonding pads;
A side substrate, it is electrically connected to one or more side bonding pads; With
A bottom substrate is electrically connected to one or more side bonding pads via the side substrate, and bottom substrate is electrically connected to one or more silicon through holes.
12. multi-chip semiconductor encapsulation according to claim 11 also comprises a connector that is placed between a plurality of semiconductor chips and the bottom substrate, connector is electrically connected to bottom substrate with one or more signals from one or more silicon through holes.
13. multi-chip semiconductor encapsulation according to claim 11, wherein a plurality of semiconductor chips comprise one or more flash chips, dynamic random storage chip and/or dedicated IC chip.
14. multi-chip semiconductor encapsulation according to claim 11, one or more side bonding pads are electrically connected to one or more semiconductor chips by the side substrate from bottom substrate with one or more non-shared signals.
15. multi-chip semiconductor encapsulation according to claim 11, one or more silicon through holes are electrically connected to a plurality of semiconductor chips with one or more shared signals from connector.
16. multi-chip semiconductor encapsulation according to claim 11, wherein the side substrate comprises a flexible sides substrate, and it comprises a conductive layer, and this conductive layer is protected by two polymer material layers.
17. a method comprises:
Form silicon through hole and side bonding pads on one or more semiconductor chips of a wafer, through hole is electrically connected to first signal of first integrated circuit that forms on silicon layer, and side bonding pads is electrically connected to the secondary signal of first integrated circuit.
18. method according to claim 17, first signal comprise a shared signal, and secondary signal comprises a non-shared signal.
19. method according to claim 18, wherein shared signal comprises an address signal, but not shared signal comprises a chip select signal.
20. method according to claim 17, wherein said formation silicon through hole and side bonding pads comprise:
Wafer is provided, wherein wafer is included in a plurality of bonding welding pads on the silicon layer, a plurality of bonding welding pads comprise the one or more bonding welding pads that are electrically connected with first integrated circuit, and comprise the one or more bonding welding pads that are electrically connected with second integrated circuit that forms on silicon layer.
21. method according to claim 20, wherein said formation silicon through hole and side bonding pads also comprise:
Form a polymer-matrix viscose glue on silicon layer, polymer-matrix viscose glue to small part protected key closes pad; With
Wafer is adhered on the support.
22. method according to claim 21, wherein said formation silicon through hole and side bonding pads also comprise makes wafer thinner.
23. method according to claim 22, wherein said formation silicon through hole and side bonding pads also comprise:
Form a plurality of through holes, wherein the position of a plurality of through holes is approximately consistent with the position of a plurality of bonding welding pads; With
On a position that aims at the wafer cutting and design, between first and second integrated circuits, form another hole, wherein said another hole development length is less than whole silicon layer thickness.
24. method according to claim 23, wherein said formation silicon through hole and side bonding pads also comprise: in the bottom of silicon layer, form a separator on the sidewall in the sidewall of a plurality of through holes and another hole and bottom.
25. method according to claim 24, wherein said formation silicon through hole and side bonding pads also comprise: form an adhesion layer and a Seed Layer (seedlayer) in a plurality of through holes and another hole.
26. method according to claim 25, wherein said formation silicon through hole and side bonding pads also comprise: a kind of electric conducting material is filled into through hole and another hole.
27. method according to claim 26, wherein said formation silicon through hole and side bonding pads also comprise: form a polymeric layer in the wafer bottom, polymeric layer is reserved the electric conducting material that exposes in through hole and another hole at least in part.
28. method according to claim 27, wherein said formation silicon through hole and side bonding pads also comprise: with the about consistent location of at least some lead to the hole site on, form scolder on electric conducting material.
29. method according to claim 28, wherein said formation silicon through hole and side bonding pads also comprise: approximately on the consistent location wafer is being cut with another hole central authorities, thereby the sidewall in another hole forms a pair of side bonding pads, one of them links to each other with first integrated circuit, and another links to each other with second integrated circuit.
30. a method comprises:
Make a connector, it comprises the interconnecting silicon through holes that mates with the bottom chip of chip-stack;
Pile up bottom chip on connector;
Pile up one or more other chips on bottom chip;
A side substrate is electrically connected to one or more side bonding pads of one or more laminated chips;
The side substrate is electrically connected to a bottom substrate; With
Connector is electrically connected to bottom substrate.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2008/073100 WO2010057339A1 (en) | 2008-11-19 | 2008-11-19 | Semiconductor chip with through-silicon-via and sidewall pad |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101542726A true CN101542726A (en) | 2009-09-23 |
| CN101542726B CN101542726B (en) | 2011-11-30 |
Family
ID=41124199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200880000341.1A Active CN101542726B (en) | 2008-11-19 | 2008-11-19 | Semiconductor chip with silicon through holes and side bonding pads |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN101542726B (en) |
| WO (1) | WO2010057339A1 (en) |
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847664A (en) * | 2010-03-15 | 2010-09-29 | 香港应用科技研究院有限公司 | Electron device package and method for manufacturing same |
| CN102044522A (en) * | 2010-07-15 | 2011-05-04 | 黄婷婷 | Multi-chip stacking structure |
| CN102270603A (en) * | 2011-08-11 | 2011-12-07 | 北京大学 | Manufacturing method of silicon through hole interconnect structure |
| CN102449762A (en) * | 2010-06-25 | 2012-05-09 | 合胜科技有限公司 | Memory device |
| CN102484100A (en) * | 2009-09-18 | 2012-05-30 | Ev集团E·索尔纳有限责任公司 | Method for chip to wafer bonding |
| CN102487058A (en) * | 2010-12-01 | 2012-06-06 | 海力士半导体有限公司 | Semiconductor chip, semiconductor package, and method for manufacturing semiconductor chip |
| CN103887262A (en) * | 2012-12-19 | 2014-06-25 | 日月光半导体制造股份有限公司 | Stacked package and manufacturing method thereof |
| CN104465568A (en) * | 2013-09-24 | 2015-03-25 | 英特尔公司 | Stacked microelectronic dice embedded in microelectronic substrate |
| CN104733417A (en) * | 2013-12-21 | 2015-06-24 | 国际商业机器公司 | Semiconductor Chip And Method For Manufacturing Same |
| CN105321914A (en) * | 2014-07-08 | 2016-02-10 | 三星电子株式会社 | Chip and chip-stacked package using the same |
| CN106653731A (en) * | 2015-10-27 | 2017-05-10 | 晟碟信息科技（上海）有限公司 | Sidewall bridge interconnector in semiconductor device |
| CN109755215A (en) * | 2017-11-02 | 2019-05-14 | 长鑫存储技术有限公司 | Semiconductor package assembly and a manufacturing method thereof |
| CN110010495A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of high density side wall interconnected method |
| CN110010620A (en) * | 2017-11-21 | 2019-07-12 | 长江存储科技有限责任公司 | A kind of production method and 3D nand flash memory of high stacking number 3D nand flash memory |
| CN110010496A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of production method of the system in package interconnection architecture with high density side wall pad |
| CN110010494A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of system in package interconnection architecture production method of the side wall with pad |
| CN111128762A (en) * | 2018-10-31 | 2020-05-08 | 台湾积体电路制造股份有限公司 | Semiconductor package and method of forming the same |
| WO2020108387A1 (en) * | 2018-11-28 | 2020-06-04 | Changxin Memory Technologies, Inc. | Semiconductor device, fabrication method thereof, package and fabrication method thereof |
| CN111863791A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Semiconductor packaging body and chip packaging body |
| CN111863641A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Chip packaging method |
| CN111952244A (en) * | 2020-08-24 | 2020-11-17 | 浙江集迈科微电子有限公司 | Flexible circuit board side wall interconnection process |
| CN112366194A (en) * | 2020-11-02 | 2021-02-12 | 上海燧原智能科技有限公司 | Bridging chip and semiconductor packaging structure |
| CN114664793A (en) * | 2022-05-24 | 2022-06-24 | 威海艾迪科电子科技股份有限公司 | Chip side surface interconnection packaging structure and manufacturing method thereof |
| WO2022247024A1 (en) * | 2021-05-26 | 2022-12-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method for same |
| WO2024045329A1 (en) * | 2022-09-02 | 2024-03-07 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing same |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101088825B1 (en) | 2010-07-09 | 2011-12-01 | 주식회사 하이닉스반도체 | Semiconductor chip and stack package having the same |
| CN102446883A (en) * | 2011-12-12 | 2012-05-09 | 清华大学 | Universal package substrate, package structure and package method |
| CN103247570A (en) * | 2013-05-10 | 2013-08-14 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing method for silicon through holes and silicon through hole interconnection |
| US9871019B2 (en) | 2015-07-17 | 2018-01-16 | Invensas Corporation | Flipped die stack assemblies with leadframe interconnects |
| US9490195B1 (en) | 2015-07-17 | 2016-11-08 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
| US9825002B2 (en) | 2015-07-17 | 2017-11-21 | Invensas Corporation | Flipped die stack |
| US9508691B1 (en) | 2015-12-16 | 2016-11-29 | Invensas Corporation | Flipped die stacks with multiple rows of leadframe interconnects |
| US10566310B2 (en) | 2016-04-11 | 2020-02-18 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
| US9595511B1 (en) | 2016-05-12 | 2017-03-14 | Invensas Corporation | Microelectronic packages and assemblies with improved flyby signaling operation |
| US9728524B1 (en) | 2016-06-30 | 2017-08-08 | Invensas Corporation | Enhanced density assembly having microelectronic packages mounted at substantial angle to board |
| CN107994001A (en) * | 2017-11-28 | 2018-05-04 | 信利光电股份有限公司 | A kind of chip package and terminal device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5790380A (en) * | 1995-12-15 | 1998-08-04 | International Business Machines Corporation | Method for fabricating a multiple chip module using orthogonal reorientation of connection planes |
| KR100524948B1 (en) * | 2003-02-22 | 2005-11-01 | 삼성전자주식회사 | Multi chip package with reduced chip crack and fabricating method thereof |
| KR100668857B1 (en) * | 2005-07-07 | 2007-01-16 | 주식회사 하이닉스반도체 | Stack type package |
| JP2008263005A (en) * | 2007-04-11 | 2008-10-30 | Toyobo Co Ltd | Interposer |
| JP2008135763A (en) * | 2007-12-20 | 2008-06-12 | Seiko Epson Corp | Semiconductor module, and method for manufacturing electronic equipment and semiconductor module |
-
2008
- 2008-11-19 CN CN200880000341.1A patent/CN101542726B/en active Active
- 2008-11-19 WO PCT/CN2008/073100 patent/WO2010057339A1/en active Application Filing
Cited By (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102484100A (en) * | 2009-09-18 | 2012-05-30 | Ev集团E·索尔纳有限责任公司 | Method for chip to wafer bonding |
| CN102484100B (en) * | 2009-09-18 | 2015-07-29 | Ev集团E·索尔纳有限责任公司 | The method of joint chip on wafer |
| CN101847664B (en) * | 2010-03-15 | 2014-04-02 | 香港应用科技研究院有限公司 | Electron device package and method for manufacturing same |
| CN101847664A (en) * | 2010-03-15 | 2010-09-29 | 香港应用科技研究院有限公司 | Electron device package and method for manufacturing same |
| CN102449762A (en) * | 2010-06-25 | 2012-05-09 | 合胜科技有限公司 | Memory device |
| CN102449762B (en) * | 2010-06-25 | 2015-06-17 | 新普力科技有限公司 | Memory device |
| CN102044522A (en) * | 2010-07-15 | 2011-05-04 | 黄婷婷 | Multi-chip stacking structure |
| CN102487058A (en) * | 2010-12-01 | 2012-06-06 | 海力士半导体有限公司 | Semiconductor chip, semiconductor package, and method for manufacturing semiconductor chip |
| CN102487058B (en) * | 2010-12-01 | 2016-05-18 | 海力士半导体有限公司 | The manufacture method of semiconductor chip, semiconductor package part and semiconductor chip |
| CN102270603B (en) * | 2011-08-11 | 2013-12-04 | 北京大学 | Manufacturing method of silicon through hole interconnect structure |
| CN102270603A (en) * | 2011-08-11 | 2011-12-07 | 北京大学 | Manufacturing method of silicon through hole interconnect structure |
| CN103887262A (en) * | 2012-12-19 | 2014-06-25 | 日月光半导体制造股份有限公司 | Stacked package and manufacturing method thereof |
| CN104465568A (en) * | 2013-09-24 | 2015-03-25 | 英特尔公司 | Stacked microelectronic dice embedded in microelectronic substrate |
| US9564400B2 (en) | 2013-09-24 | 2017-02-07 | Intel Corporation | Methods of forming stacked microelectronic dice embedded in a microelectronic substrate |
| CN104733417A (en) * | 2013-12-21 | 2015-06-24 | 国际商业机器公司 | Semiconductor Chip And Method For Manufacturing Same |
| CN105321914A (en) * | 2014-07-08 | 2016-02-10 | 三星电子株式会社 | Chip and chip-stacked package using the same |
| CN106653731B (en) * | 2015-10-27 | 2019-12-31 | 晟碟信息科技（上海）有限公司 | Sidewall bridge interconnect in semiconductor device |
| CN106653731A (en) * | 2015-10-27 | 2017-05-10 | 晟碟信息科技（上海）有限公司 | Sidewall bridge interconnector in semiconductor device |
| CN109755215A (en) * | 2017-11-02 | 2019-05-14 | 长鑫存储技术有限公司 | Semiconductor package assembly and a manufacturing method thereof |
| CN109755215B (en) * | 2017-11-02 | 2021-07-27 | 长鑫存储技术有限公司 | Semiconductor package and method of manufacturing the same |
| CN110010620B (en) * | 2017-11-21 | 2021-04-13 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND flash memory with high stack number and 3D NAND flash memory |
| CN110010620A (en) * | 2017-11-21 | 2019-07-12 | 长江存储科技有限责任公司 | A kind of production method and 3D nand flash memory of high stacking number 3D nand flash memory |
| US11476219B2 (en) | 2018-10-31 | 2022-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal-bump sidewall protection |
| CN111128762A (en) * | 2018-10-31 | 2020-05-08 | 台湾积体电路制造股份有限公司 | Semiconductor package and method of forming the same |
| CN111128762B (en) * | 2018-10-31 | 2021-12-31 | 台湾积体电路制造股份有限公司 | Semiconductor package and method of forming the same |
| WO2020108387A1 (en) * | 2018-11-28 | 2020-06-04 | Changxin Memory Technologies, Inc. | Semiconductor device, fabrication method thereof, package and fabrication method thereof |
| CN110010495B (en) * | 2018-12-26 | 2021-05-28 | 浙江集迈科微电子有限公司 | High-density side wall interconnection method |
| CN110010495A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of high density side wall interconnected method |
| CN110010496B (en) * | 2018-12-26 | 2023-04-28 | 浙江集迈科微电子有限公司 | Manufacturing method of system-in-package interconnection structure with high-density side wall bonding pads |
| CN110010494B (en) * | 2018-12-26 | 2021-04-06 | 浙江集迈科微电子有限公司 | Method for manufacturing system-in-package interconnection structure with side wall provided with bonding pad |
| CN110010496A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of production method of the system in package interconnection architecture with high density side wall pad |
| CN110010494A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of system in package interconnection architecture production method of the side wall with pad |
| CN111863641A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Chip packaging method |
| CN111863791A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Semiconductor packaging body and chip packaging body |
| CN111952244A (en) * | 2020-08-24 | 2020-11-17 | 浙江集迈科微电子有限公司 | Flexible circuit board side wall interconnection process |
| CN112366194A (en) * | 2020-11-02 | 2021-02-12 | 上海燧原智能科技有限公司 | Bridging chip and semiconductor packaging structure |
| WO2022247024A1 (en) * | 2021-05-26 | 2022-12-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method for same |
| US11916044B2 (en) | 2021-05-26 | 2024-02-27 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
| CN114664793A (en) * | 2022-05-24 | 2022-06-24 | 威海艾迪科电子科技股份有限公司 | Chip side surface interconnection packaging structure and manufacturing method thereof |
| CN114664793B (en) * | 2022-05-24 | 2022-08-16 | 威海艾迪科电子科技股份有限公司 | Chip side surface interconnection packaging structure and manufacturing method thereof |
| WO2024045329A1 (en) * | 2022-09-02 | 2024-03-07 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101542726B (en) | 2011-11-30 |
| WO2010057339A1 (en) | 2010-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101542726B (en) | Semiconductor chip with silicon through holes and side bonding pads | |
| US11387214B2 (en) | Multi-chip modules formed using wafer-level processing of a reconstituted wafer | |
| US11996401B2 (en) | Packaged die and RDL with bonding structures therebetween | |
| US8674482B2 (en) | Semiconductor chip with through-silicon-via and sidewall pad | |
| US11217563B2 (en) | Fully interconnected heterogeneous multi-layer reconstructed silicon device | |
| US10497616B2 (en) | Embedded 3D interposer structure | |
| CN101752270B (en) | Method of forming stacked IC semiconductor crystal grain | |
| US9748216B2 (en) | Apparatus and method for a component package | |
| TWI714913B (en) | Package structure and manufacturing method thereof | |
| US8367466B2 (en) | Manufacturing stacked semiconductor device | |
| JP4865197B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20130087919A1 (en) | Lightweight and compact through-silicon via stack package with excellent electrical connections and method for manufacturing the same | |
| US9847284B2 (en) | Stacked wafer DDR package | |
| CN110335859B (en) | Multi-chip packaging structure based on TSV and preparation method thereof | |
| JP2022021336A (en) | Semiconductor package and method for manufacturing the same | |
| JP2013153083A (en) | Semiconductor device and manufacturing method thereof | |
| CN111128974A (en) | Wafer stacking method and wafer stacking structure | |
| CN108735684B (en) | Multi-chip semiconductor package, vertically stacked semiconductor chip and packaging method | |
| US11380611B2 (en) | Chip-on-wafer structure with chiplet interposer | |
| US20220328395A1 (en) | Chip-On-Wafer Structure with Chiplet Interposer | |
| CN115312496A (en) | Three-dimensional semiconductor integrated packaging structure and process based on rear through hole technology | |
| CN103377990A (en) | Through-silicon-via structure | |
| US10229901B2 (en) | Immersion interconnections for semiconductor devices and methods of manufacture thereof | |
| KR20130077628A (en) | Semicondcutor apparatus and method of manufacturing the same | |
| TWI757864B (en) | Package structure and method of forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |