CN111863641A - Chip packaging method - Google Patents
Chip packaging method Download PDFInfo
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- CN111863641A CN111863641A CN202010740314.0A CN202010740314A CN111863641A CN 111863641 A CN111863641 A CN 111863641A CN 202010740314 A CN202010740314 A CN 202010740314A CN 111863641 A CN111863641 A CN 111863641A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004033 plastic Substances 0.000 claims abstract description 48
- 239000010410 layer Substances 0.000 claims description 226
- 238000000465 moulding Methods 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 150000001875 compounds Chemical class 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 4
- 230000001680 brushing effect Effects 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 11
- 238000002161 passivation Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The application discloses a chip packaging method, which comprises the following steps: forming a first plastic package layer on the side surfaces and one side of the functional surfaces of the chips, wherein the surface of one side, far away from the functional surfaces, of the first plastic package layer is flat, and the bonding pads on the functional surfaces of the chips are exposed out of the first plastic package layer; forming a first redistribution layer on the first plastic package layer, wherein the first redistribution layer is electrically connected with the bonding pad exposed from the first plastic package layer; forming first conductive columns on the first redistribution layer corresponding to positions between adjacent chips, wherein the first conductive columns are electrically connected with the bonding pads through the first redistribution layer; and cutting off part of the first plastic packaging layer, part of the first rewiring layer and part of the first conductive columns among the adjacent chips to obtain a package body containing the single chip, wherein the first conductive columns are provided with surfaces exposed from the side surfaces of the package body. Through the mode, the bonding pad on the functional surface of the chip can be led out from the side surface of the chip, and then is electrically connected with other elements, so that the connection reliability and the chip strength are improved.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a chip packaging method.
Background
With the upgrading of electronic products, the functions of the electronic products are increasingly required to be diversified and the volume of the electronic products is required to be more compact, so that the volume of stacked chips needs to be compressed as much as possible in a stacking manner capable of realizing the non-functional chips.
In the prior art, when 3D stacking is performed, a Through hole is usually drilled in a stacked chip by using a Through Silicon Via (TSV) technique, and a conductive material is filled in the Through hole so that a pad on the chip can be electrically connected to pads of other chips; or, the bonding pads on the front surface of the chip are exposed in a staggered and laminated mode, and then the bonding pads between the chip and the chip can be electrically connected in a routing mode.
However, the precision requirement of the through silicon via technology for the process is very high, the yield of the chip is reduced, the strength of the chip is reduced, and the staggered lamination and routing manner has the problems that the occupied volume of the chip after staggered lamination is large, and the routing connection is not firm.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a chip packaging method, which can lead out a bonding pad on a functional surface of a chip from the side surface of the chip so as to be electrically connected with other electric elements.
In order to solve the technical problem, the application adopts a technical scheme that: a chip packaging method is provided, which comprises the following steps: forming a first plastic package layer on the side surfaces and one side of a functional surface of a plurality of chips, wherein the surface of one side, far away from the functional surface, of the first plastic package layer is flat, and a bonding pad on the functional surface of each chip is exposed out of the first plastic package layer; forming a first redistribution layer on the first plastic package layer, the first redistribution layer being electrically connected to the pads exposed from the first plastic package layer; forming first conductive pillars on the first redistribution layer corresponding to positions between adjacent chips, the first conductive pillars being electrically connected to the pads through the first redistribution layer; and cutting off a part of the first plastic packaging layer, a part of the first redistribution layer and a part of the first conductive column between the adjacent chips to obtain a package body containing the single chip, wherein the first conductive column has a surface exposed from a side surface of the package body.
Wherein, form first plastic envelope layer in the side of a plurality of chips and functional surface one side, include: forming a continuous first plastic package layer on the front surface of a wafer, wherein the wafer is provided with a plurality of chips arranged in an array manner, the functional surfaces of the chips are the front surface of the wafer, scribing grooves are formed between the adjacent chips, and the first plastic package layer covers the scribing grooves; the cutting away a portion of the first molding layer, a portion of the first redistribution layer, and a portion of the first conductive pillar between adjacent chips to obtain a package including a single chip includes: and cutting off at least part of the first plastic packaging layer, part of the first redistribution layer and part of the first conductive column at the scribing groove position to obtain a package body containing a single chip.
Wherein the width of the first conductive pillar is greater than the width of the scribing groove at the corresponding position; the cutting away at least part of the first plastic package layer, part of the first redistribution layer and part of the first conductive pillar at the scribing slot position includes: and cutting along the side wall of the scribing groove to remove all the first plastic package layer, the first rewiring layer and the first conductive columns at the position of the scribing groove.
Wherein, the cutting off a portion of the first molding layer, a portion of the first redistribution layer, and a portion of the first conductive pillar between the adjacent chips to obtain a package including a single chip, previously, includes: and grinding the side of the wafer far away from the chip to reduce the thickness of the wafer.
Wherein, after forming a first redistribution layer on the first plastic package layer, the method includes: and forming a first insulating layer on the first rewiring layer, wherein a first opening is formed in the first insulating layer at a position corresponding to the scribing groove, and the first rewiring layer is exposed out of the first opening.
Wherein forming first conductive pillars on the first redistribution layer at locations corresponding to between adjacent chips comprises: and electroplating to form the first conductive column in the first opening, wherein one end of the first conductive column is electrically connected with the first redistribution layer, and the other end of the first conductive column is flush with one side, away from the chip, of the first insulating layer. Wherein the first insulating layer forms a protective layer.
Wherein the first insulating layer is a photoresist layer, and the forming of the first conductive pillars on the first redistribution layer at positions corresponding to positions between adjacent chips includes: removing the photoresist layer; and forming a second insulating layer on one side of the first rewiring layer, which is far away from the chip, wherein the second insulating layer covers the first conductive columns and forms a protective layer.
Wherein the forming of the second insulating layer on the side of the first redistribution layer away from the chip includes: and forming the second insulating layer on the first rewiring layer in a glue brushing mode.
Wherein the first insulating layer is a photoresist layer, and the forming of the first conductive pillars on the first redistribution layer at positions corresponding to positions between adjacent chips includes: removing the photoresist layer; forming a first planarization layer on the first rewiring layer; and forming a second plastic packaging layer on the first planarization layer and the first conductive column, wherein the first planarization layer and the second plastic packaging layer form a protective layer.
The beneficial effect of this application is: this application forms first rewiring layer and first conductive pillar of being connected with the pad electricity on the functional surface in chip functional surface one side, wherein, first conductive pillar includes the part that exposes from the side of the packaging body that contains single chip, so that the pad on the chip functional surface is drawn forth from the side of chip, and then be connected with other electric elements electricity, the through-hole has not been seted up on the chip to this application, the integrality of chip structure has been ensured, and after being connected with the first conductive pillar electricity of a plurality of packaging body sides through other electric connection pieces, make to realize interconnecting between the chip, this mode is compared and is connected more reliably in the mode of routing, structural strength in the mode chip of seting up the through-hole is higher.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a chip packaging method according to the present application;
FIG. 2a is a schematic cross-sectional view of an embodiment corresponding to step S101 in FIG. 1;
FIG. 2b is a schematic cross-sectional view of another embodiment corresponding to step S101 in FIG. 1;
FIG. 3 is a schematic cross-sectional view of an embodiment corresponding to step S102 in FIG. 1;
FIG. 4 is a schematic cross-sectional view of one embodiment after step S102 in FIG. 1;
FIG. 5 is a schematic cross-sectional view of an embodiment corresponding to step S103 in FIG. 1;
FIG. 6a is a schematic cross-sectional view of one embodiment after step S103 in FIG. 1;
FIG. 6b is a schematic cross-sectional structural view of another corresponding embodiment after step S103 in FIG. 1;
FIG. 7a is a schematic cross-sectional view of one embodiment of the structure before step S104 in FIG. 1;
fig. 7b is a schematic cross-sectional structural diagram of an embodiment corresponding to step S104 in fig. 1.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart diagram illustrating an embodiment of a chip packaging method according to the present application, the method including:
step S101: form first plastic envelope layer in the side of a plurality of chips and functional surface one side, wherein, one side surfacing that functional surface was kept away from to first plastic envelope layer, and the pad on the functional surface of chip exposes from first plastic envelope layer.
Specifically, referring to fig. 2a, fig. 2a is a schematic cross-sectional structure view of an embodiment corresponding to step S101 in fig. 1, wherein a side of the chip 10 where the bonding pad 100 is disposed is a functional surface, and a side opposite to the functional surface is a non-functional surface, a first molding compound layer 12 is formed on a side surface and a functional surface of the chip 10, and in order to expose the bonding pad 100 from the first molding compound layer 12, the first molding compound layer 12 may be further ground to expose the bonding pad 100.
In an application manner, please continue to refer to fig. 2a, step S101 specifically includes: a continuous first plastic package layer 12 is formed on the front surface of the wafer 20, wherein the wafer 20 is provided with a plurality of chips 10 arranged in an array, the functional surface of the chip 10 is the front surface of the wafer 20, a scribing groove 200 is formed between adjacent chips 10, and the first plastic package layer 12 covers the scribing groove 200.
Specifically, a first molding compound layer 12 is formed on the surface of the wafer 20, the first molding compound layer 12 covers the scribe lines 200 between the chips 10 on the wafer 20 and the functional surfaces of the chips 10, and one side of the first molding compound layer 12 away from the chips 10 is ground, so that the pads 100 on the functional surfaces of the chips 10 are exposed from the first molding compound layer 12.
In another application, please refer to fig. 2b, where fig. 2b is a schematic cross-sectional structure diagram of another embodiment corresponding to step S101 in fig. 1, and step S101 specifically includes: the non-functional surfaces of the chips 10 are attached to the first carrier 30, a first molding compound layer 12a is formed on the side surfaces and the functional surfaces of the chips 10, the first molding compound layer 12a covers the functional surfaces of the chips 10, and the side of the first molding compound layer 12a away from the first carrier 30 is ground to expose the pads 100 on the functional surfaces of the chips 10.
Step S102: and forming a first redistribution layer on the first plastic packaging layer, wherein the first redistribution layer is electrically connected with the bonding pad exposed from the first plastic packaging layer.
Specifically, referring to fig. 3, fig. 3 is a schematic cross-sectional structural diagram of an embodiment corresponding to step S102 in fig. 1, for facilitating understanding, the following steps are continued with the structure shown in fig. 2a, and step S102 specifically includes: forming a first passivation layer 13 on the first plastic package layer 12, forming a first gap (not labeled) on the surface of the first passivation layer 13 corresponding to the pad 100, forming a first redistribution layer 14 on the first passivation layer 13, forming the first redistribution layer 14 by sputtering, etching the first redistribution layer 14 after forming the first redistribution layer 14 to retain a required portion of the first redistribution layer 14, so that the pad 100 is independent, and the first redistribution layer 14 is finer and more tightly combined with the first plastic package layer 12 made of resin. The first redistribution layer 14 covers a side of the first passivation layer 13 away from the chip 10, and is electrically connected to the pad 100 on the functional surface of the chip 10 through the first gap.
Further, referring to fig. 4, fig. 4 is a schematic cross-sectional structure diagram of an embodiment corresponding to step S102 in fig. 1, and the step S102 further includes: a first insulating layer 15 is formed on the first rewiring layer 14, a first opening 150 is formed in a position of the first insulating layer 15 corresponding to the scribe line 200, and the first rewiring layer 14 is exposed from the first opening 150.
Specifically, an insulating material is coated on the first redistribution layer 14 to form a first insulating layer 15, a first opening 150 is opened on the first insulating layer 15 at a position corresponding to the scribe line 200 between the chips 10, and the width of the first opening 150 is greater than the width of the scribe line 200 between the chips 10 on the wafer 20.
Step S103: and forming first conductive columns on the first redistribution layer corresponding to positions between adjacent chips, wherein the first conductive columns are electrically connected with the bonding pads through the first redistribution layer.
Specifically, referring to fig. 5, fig. 5 is a schematic cross-sectional structure diagram of an embodiment corresponding to step S103 in fig. 1, where step S103 specifically includes: first conductive pillars 16 are formed in the first openings 150 by electroplating, one end of each first conductive pillar 16 is electrically connected to the first redistribution layer 14, and the other end of each first conductive pillar 16 is flush with the side of the first insulating layer 15 away from the chip 10. First conductive pillars 16 are formed in the first openings 150 on the first insulating layer 15 by electroplating, the first conductive pillars 16 are electrically connected to the first redistribution layer 14, and further the first conductive pillars 16 are electrically connected to the pads 100 on the functional surface of the chip 10 through the first redistribution layer 14. The first conductive pillars 16 are associated with the first openings 150 on the first insulating layer 15, and when the width of the first openings 150 is controlled to be greater than the width of the scribe grooves 200 on the wafer 20, the width of the first conductive pillars 16 is greater than the width of the scribe grooves 200 at the corresponding positions. The width of the first conductive pillar 16 is larger to facilitate the dicing at the position corresponding to the dicing groove 200 during the subsequent dicing.
In a specific application scenario, please continue to refer to fig. 5, the material of the first insulating layer 15 may be epoxy resin, the first insulating layer 15 forms a protection layer, and the first insulating layer 15 covers and protects a side of the first redistribution layer 14 away from the chip 10 and a side surface of the first conductive pillar 16 to prevent short circuit caused by accidental touch. The side of the first conductive pillar 16 away from the chip 10 can still be electrically connected to other chips 10 by wire bonding, and after subsequent cutting, the exposed portion of the first conductive pillar 16 from the side of the chip 10 can be connected to each other by an electrical connector.
In another specific application scenario, referring to fig. 6a, fig. 6a is a schematic cross-sectional structure diagram of an embodiment corresponding to step S103 in fig. 1, where the first insulating layer 15 shown in fig. 5 is a photoresist layer (not labeled), and after step S103, the method specifically includes: and removing the photoresist layer, forming a second insulating layer 17 on the side of the first redistribution layer 14 away from the chip 10, wherein the second insulating layer 17 covers the first conductive pillars 16, and the second insulating layer 17 forms a protective layer. When the first conductive pillars 16 are formed, a material for forming the first conductive pillars 16 may remain on the photoresist layer, a surface of the first conductive pillars 16, which is formed away from the chip 10, may also be uneven, a surface of the first redistribution layer 14, which is away from the chip 10, is exposed after the photoresist layer is removed, a second insulating layer 17 is formed on a side of the first redistribution layer 14, which is away from the chip 10, and the second insulating layer 17 covers a side of the first redistribution layer 14, which is away from the chip 10, and a surface of the first conductive pillars 16, which is away from the chip 10. The second insulating layer 17 protects the first conductive pillars 16 and the first redistribution layer 14 on the side away from the chip 10, and the surface of the second insulating layer 17 on the side away from the chip 10 is relatively flat.
Specifically, forming the second insulating layer 17 on the side of the first rewiring layer 14 away from the chip 10 includes: a second insulating layer 17 is formed on the first rewiring layer 14 by means of a brush paste. An insulating paste is applied to the first rewiring layer 14, and a second insulating layer 17 is formed after the insulating paste is cured. The method for uniformly brushing glue on the side far away from the wafer 20 has low cost and high efficiency.
In another specific application scenario, referring to fig. 6b, fig. 6b is a schematic cross-sectional structure diagram of another embodiment after step S103 in fig. 1, where the first insulating layer 15 shown in fig. 5 is a photoresist layer (not labeled), and after step S103, the method specifically includes: the photoresist layer is removed, a first planarizing layer 18 is formed on the first redistribution layer 14, a second molding layer 19 is formed on the first planarizing layer 18 and the first conductive pillars 16, and the first planarizing layer 18 and the second molding layer 19 form a protection layer. One side of the first planarizing layer 18 contacts with a side of the first redistribution layer 14 away from the chip 10 to fill the uneven part on the surface of the first redistribution layer 14, the first planarizing layer 18 is flat on the side away from the first redistribution layer 14, and the second molding layer 19 formed on the first planarizing layer is more tightly bonded to the first planarizing layer, of course, the second molding layer 19 may also be directly formed on the side of the first redistribution layer 14 away from the chip 10, which is not specifically limited in this application.
Step S104: and cutting off part of the first plastic packaging layer, part of the first rewiring layer and part of the first conductive columns among the adjacent chips to obtain a package body containing the single chip, wherein the first conductive columns are provided with surfaces exposed from the side surfaces of the package body.
Specifically, when the chips 10 are disposed on the wafer 20, before step S104, please refer to fig. 7a, fig. 7a is a schematic cross-sectional structure diagram of an embodiment corresponding to step S104 in fig. 1, and before step S401, the method further includes: the side of the wafer 20 remote from the chips 10 is ground to reduce the thickness of the wafer 20. Taking the structure shown in fig. 6b as an example, the silicon material on the side of the wafer 20 far from the chip 10 is ground by mechanical grinding on the back surface of the wafer 20, so that the thickness of the non-functional surface of the chip 10 is reduced, thereby forming the structure shown in fig. 7 a. The scribing grooves 200 between the chips 10 are exposed from the bottom of the wafer 20, and the thickness of the whole chip 10 is reduced to 100-200 μm, thereby reducing the whole volume after packaging.
Further, referring to fig. 7b, fig. 7b is a schematic cross-sectional structure diagram of an embodiment corresponding to step S104 in fig. 1, and referring to fig. 7a in combination, step S104 specifically includes: at least a portion of the first molding layer 12, a portion of the first redistribution layer 14, and a portion of the first conductive pillar 16 at the position of the scribe line 200 are cut away to obtain a package 300 containing a single chip 10.
Specifically, the package 300 including a single chip 10 as shown in fig. 7b can be obtained by using a portion of the first molding layer 12, a portion of the first redistribution layer 14, and a portion of the first conductive pillar 16 among the chips 10, where the chip 10 may be one or more of an ASIC chip, a CPU chip, a GPU chip, an FPGA chip, and an MCU chip.
Optionally, a cut is made along the sidewall of the scribe line 200 to remove all of the first molding layer 12, the first redistribution layer 14 and the first conductive pillar 16 at the position of the scribe line 200. Cutting along the positions of the dotted line a and the dotted line B shown in fig. 7a, and removing a portion of the first molding layer 12, a portion of the first redistribution layer 14, and a portion of the first conductive pillar 16 between the sidewalls of the scribe line 200 to obtain the package 300 shown in fig. 7B, where originally, when the first conductive pillar 16 is disposed, the width of the first conductive pillar 16 is greater than the width of the scribe line 200, and therefore, after the portion of the first conductive pillar 16 corresponding to the width of the scribe line 200 is cut, a portion of the first conductive pillar 16 remains on the side surface of the package 300 and is exposed from the side surface of the package 300. The first conductive pillars 16 on the package body 300 are electrically connected to the pads 100 through the first redistribution layer 14, so that the pads 100 are led out from the side surface of the package body 300, and the side surface of the first conductive pillars 16 exposed from the package body 300 is flush with the side surfaces of the first plastic package layer 12 and the second plastic package layer 19.
It is understood that, referring to fig. 2 b-fig. 7b again, when the chip 10 is disposed on the first carrier 30, the first redistribution layer 14, the first conductive pillars 16 and the passivation layer are formed on a side of the chip 10 away from the first carrier 30. The first redistribution layer 14 is electrically connected to the pad 100, the adjacent positions of the first conductive pillars 16 between the chips are electrically connected to the first redistribution layer 14, and the width of the first conductive pillars 16 is actually set, so that a portion of the first plastic encapsulation layer 12, a portion of the first redistribution layer 14, and a portion of the first conductive pillars 16 are cut off corresponding to the region between the adjacent chips 10, which is not described herein again.
In summary, the first redistribution layer 14 and the first conductive pillar 16 electrically connected to the pad 100 on the functional surface are formed on one side of the functional surface of the chip 10, wherein the first conductive pillar 16 includes a portion exposed from a side surface of the package 300 including a single chip 10, so that the pad 100 on the functional surface of the chip 10 is led out from the side surface of the chip 10, and is further electrically connected to other electrical elements.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A chip packaging method is characterized by comprising the following steps:
forming a first plastic package layer on the side surfaces and one side of a functional surface of a plurality of chips, wherein the surface of one side, far away from the functional surface, of the first plastic package layer is flat, and a bonding pad on the functional surface of each chip is exposed out of the first plastic package layer;
forming a first redistribution layer on the first plastic package layer, the first redistribution layer being electrically connected to the pads exposed from the first plastic package layer;
forming first conductive pillars on the first redistribution layer corresponding to positions between adjacent chips, the first conductive pillars being electrically connected to the pads through the first redistribution layer;
and cutting off a part of the first plastic packaging layer, a part of the first redistribution layer and a part of the first conductive column between the adjacent chips to obtain a package body containing the single chip, wherein the first conductive column has a surface exposed from a side surface of the package body.
2. The chip packaging method according to claim 1,
the side of a plurality of chips and functional surface one side form first plastic envelope layer, include:
forming a continuous first plastic package layer on the front surface of a wafer, wherein the wafer is provided with a plurality of chips arranged in an array manner, the functional surfaces of the chips are the front surface of the wafer, scribing grooves are formed between the adjacent chips, and the first plastic package layer covers the scribing grooves;
the cutting away a portion of the first molding layer, a portion of the first redistribution layer, and a portion of the first conductive pillar between adjacent chips to obtain a package including a single chip includes: and cutting off at least part of the first plastic packaging layer, part of the first redistribution layer and part of the first conductive column at the scribing groove position to obtain a package body containing a single chip.
3. The chip packaging method according to claim 2,
the width of the first conductive column is larger than that of the scribing groove at the corresponding position;
the cutting away at least part of the first plastic package layer, part of the first redistribution layer and part of the first conductive pillar at the scribing slot position includes: and cutting along the side wall of the scribing groove to remove all the first plastic package layer, the first rewiring layer and the first conductive columns at the position of the scribing groove.
4. The chip packaging method according to claim 2, wherein the cutting away a portion of the first molding layer, a portion of the first redistribution layer, and a portion of the first conductive pillar between adjacent chips to obtain a package containing a single chip previously comprises:
and grinding the side of the wafer far away from the chip to reduce the thickness of the wafer.
5. The chip packaging method according to claim 2, wherein the forming a first redistribution layer on the first molding compound layer, thereafter, comprises:
and forming a first insulating layer on the first rewiring layer, wherein a first opening is formed in the first insulating layer at a position corresponding to the scribing groove, and the first rewiring layer is exposed out of the first opening.
6. The chip packaging method according to claim 5, wherein the forming of the first conductive pillars on the first redistribution layer at positions corresponding to positions between adjacent chips comprises:
and electroplating to form the first conductive column in the first opening, wherein one end of the first conductive column is electrically connected with the first redistribution layer, and the other end of the first conductive column is flush with one side, away from the chip, of the first insulating layer.
7. The chip packaging method according to claim 6,
the first insulating layer forms a protective layer.
8. The chip packaging method according to claim 5,
the first insulating layer is a photoresist layer, and the first redistribution layer is formed with first conductive pillars at positions corresponding to positions between adjacent chips, and then includes:
removing the photoresist layer;
and forming a second insulating layer on one side of the first rewiring layer, which is far away from the chip, wherein the second insulating layer covers the first conductive columns and forms a protective layer.
9. The chip packaging method according to claim 8,
the forming a second insulating layer on a side of the first redistribution layer away from the chip includes: and forming the second insulating layer on the first rewiring layer in a glue brushing mode.
10. The chip packaging method according to claim 5,
the first insulating layer is a photoresist layer, and the first redistribution layer is formed with first conductive pillars at positions corresponding to positions between adjacent chips, and then includes:
removing the photoresist layer;
forming a first planarization layer on the first rewiring layer;
and forming a second plastic packaging layer on the first planarization layer and the first conductive column, wherein the first planarization layer and the second plastic packaging layer form a protective layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113380637A (en) * | 2021-05-20 | 2021-09-10 | 苏州通富超威半导体有限公司 | Fan-out type packaging method and fan-out type packaging device |
| WO2024001429A1 (en) * | 2022-06-30 | 2024-01-04 | 华进半导体封装先导技术研发中心有限公司 | System-on-wafer packaging structure |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5571754A (en) * | 1995-07-26 | 1996-11-05 | International Business Machines Corporation | Method of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack |
| CN101465343A (en) * | 2007-12-18 | 2009-06-24 | 财团法人工业技术研究院 | Three-dimensional stack chip structure with vertical electrical self-connection and manufacturing method thereof |
| CN101542726A (en) * | 2008-11-19 | 2009-09-23 | 香港应用科技研究院有限公司 | Semiconductor chip with silicon through holes and side bonding pads |
| CN103413798A (en) * | 2013-08-02 | 2013-11-27 | 南通富士通微电子股份有限公司 | Chip structure and chip packaging structure |
| US20170077016A1 (en) * | 2015-07-17 | 2017-03-16 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
| CN107104058A (en) * | 2017-06-21 | 2017-08-29 | 中芯长电半导体（江阴）有限公司 | Fan-out-type list die package structure and preparation method thereof |
| CN108269768A (en) * | 2017-01-03 | 2018-07-10 | 南亚科技股份有限公司 | Semiconductor packages and its manufacturing method |
| CN110943041A (en) * | 2019-12-16 | 2020-03-31 | 山东砚鼎电子科技有限公司 | Semiconductor structure with side surface led out, manufacturing method thereof and stacking structure |
-
2020
- 2020-07-28 CN CN202010740314.0A patent/CN111863641B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5571754A (en) * | 1995-07-26 | 1996-11-05 | International Business Machines Corporation | Method of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack |
| CN101465343A (en) * | 2007-12-18 | 2009-06-24 | 财团法人工业技术研究院 | Three-dimensional stack chip structure with vertical electrical self-connection and manufacturing method thereof |
| CN101542726A (en) * | 2008-11-19 | 2009-09-23 | 香港应用科技研究院有限公司 | Semiconductor chip with silicon through holes and side bonding pads |
| CN103413798A (en) * | 2013-08-02 | 2013-11-27 | 南通富士通微电子股份有限公司 | Chip structure and chip packaging structure |
| US20170077016A1 (en) * | 2015-07-17 | 2017-03-16 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
| CN108269768A (en) * | 2017-01-03 | 2018-07-10 | 南亚科技股份有限公司 | Semiconductor packages and its manufacturing method |
| CN107104058A (en) * | 2017-06-21 | 2017-08-29 | 中芯长电半导体（江阴）有限公司 | Fan-out-type list die package structure and preparation method thereof |
| CN110943041A (en) * | 2019-12-16 | 2020-03-31 | 山东砚鼎电子科技有限公司 | Semiconductor structure with side surface led out, manufacturing method thereof and stacking structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113380637A (en) * | 2021-05-20 | 2021-09-10 | 苏州通富超威半导体有限公司 | Fan-out type packaging method and fan-out type packaging device |
| CN113380637B (en) * | 2021-05-20 | 2023-11-17 | 苏州通富超威半导体有限公司 | Fan-out type packaging method and fan-out type packaging device |
| WO2024001429A1 (en) * | 2022-06-30 | 2024-01-04 | 华进半导体封装先导技术研发中心有限公司 | System-on-wafer packaging structure |
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|---|---|
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